clk/renesas/r9a09g057-cpg.c

1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/renesas,r9a09g057-cpg.h>
15 #include "rzv2h-cpg.h"
56 	{0, 1},
57 	{1, 2},
65 	{1, 4},
71 	{1, 4},
92 	DEF_FIXED(".pllcm33_div4", CLK_PLLCM33_DIV4, CLK_PLLCM33, 1, 4),
95 	DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16),
97 	DEF_FIXED(".pllcln_div2", CLK_PLLCLN_DIV2, CLK_PLLCLN, 1, 2),
98 	DEF_FIXED(".pllcln_div8", CLK_PLLCLN_DIV8, CLK_PLLCLN, 1, 8),
99 	DEF_FIXED(".pllcln_div16", CLK_PLLCLN_DIV16, CLK_PLLCLN, 1, 16),
102 	DEF_FIXED(".plldty_acpu_div2", CLK_PLLDTY_ACPU_DIV2, CLK_PLLDTY_ACPU, 1, 2),
103 	DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4),
104 	DEF_FIXED(".plldty_div16", CLK_PLLDTY_DIV16, CLK_PLLDTY, 1, 16),
106 	DEF_FIXED(".plldty_rcpu_div4", CLK_PLLDTY_RCPU_DIV4, CLK_PLLDTY_RCPU, 1, 4),
114 	DEF_FIXED("sys_0_pclk", R9A09G057_SYS_0_PCLK, CLK_QEXTAL, 1, 1),
123 	DEF_FIXED("iotop_0_shclk", R9A09G057_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1, 1),
128 						BUS_MSTOP(5, BIT(9))),
129 	DEF_MOD("dmac_1_aclk",			CLK_PLLDTY_ACPU_DIV2, 0, 1, 0, 1,
139 	DEF_MOD_CRITICAL("gic_0_gicclk",	CLK_PLLDTY_ACPU_DIV4, 1, 3, 0, 19,
153 	DEF_MOD("gtm_6_pclk",			CLK_PLLCLN_DIV16, 4, 9, 2, 9,
162 						BUS_MSTOP(1, BIT(0))),
164 						BUS_MSTOP(1, BIT(0))),
169 	DEF_MOD("wdt_3_clkp",			CLK_PLLCLN_DIV16, 5, 1, 2, 17,
175 	DEF_MOD("riic_8_ckm",			CLK_PLLCM33_DIV16, 9, 3, 4, 19,
177 	DEF_MOD("riic_0_ckm",			CLK_PLLCLN_DIV16, 9, 4, 4, 20,
178 						BUS_MSTOP(1, BIT(1))),
179 	DEF_MOD("riic_1_ckm",			CLK_PLLCLN_DIV16, 9, 5, 4, 21,
180 						BUS_MSTOP(1, BIT(2))),
181 	DEF_MOD("riic_2_ckm",			CLK_PLLCLN_DIV16, 9, 6, 4, 22,
182 						BUS_MSTOP(1, BIT(3))),
183 	DEF_MOD("riic_3_ckm",			CLK_PLLCLN_DIV16, 9, 7, 4, 23,
184 						BUS_MSTOP(1, BIT(4))),
185 	DEF_MOD("riic_4_ckm",			CLK_PLLCLN_DIV16, 9, 8, 4, 24,
186 						BUS_MSTOP(1, BIT(5))),
187 	DEF_MOD("riic_5_ckm",			CLK_PLLCLN_DIV16, 9, 9, 4, 25,
188 						BUS_MSTOP(1, BIT(6))),
189 	DEF_MOD("riic_6_ckm",			CLK_PLLCLN_DIV16, 9, 10, 4, 26,
190 						BUS_MSTOP(1, BIT(7))),
191 	DEF_MOD("riic_7_ckm",			CLK_PLLCLN_DIV16, 9, 11, 4, 27,
192 						BUS_MSTOP(1, BIT(8))),
205 	DEF_MOD("sdhi_1_clk_hs",		CLK_PLLCLN_DIV2, 10, 9, 5, 9,
218 						BUS_MSTOP(9, BIT(4))),
220 						BUS_MSTOP(9, BIT(4))),
222 						BUS_MSTOP(9, BIT(4))),
224 						BUS_MSTOP(9, BIT(5))),
226 						BUS_MSTOP(9, BIT(5))),
228 						BUS_MSTOP(9, BIT(5))),
230 						BUS_MSTOP(9, BIT(6))),
231 	DEF_MOD_NO_PM("cru_2_vclk",		CLK_PLLVDO_CRU2, 13, 9, 6, 25,
232 						BUS_MSTOP(9, BIT(6))),
234 						BUS_MSTOP(9, BIT(6))),
236 						BUS_MSTOP(9, BIT(7))),
238 						BUS_MSTOP(9, BIT(7))),
240 						BUS_MSTOP(9, BIT(7))),
244 	DEF_RST(3, 0, 1, 1),		/* SYS_0_PRESETN */
245 	DEF_RST(3, 1, 1, 2),		/* DMAC_0_ARESETN */
246 	DEF_RST(3, 2, 1, 3),		/* DMAC_1_ARESETN */
247 	DEF_RST(3, 3, 1, 4),		/* DMAC_2_ARESETN */
248 	DEF_RST(3, 4, 1, 5),		/* DMAC_3_ARESETN */
249 	DEF_RST(3, 5, 1, 6),		/* DMAC_4_ARESETN */
250 	DEF_RST(3, 6, 1, 7),		/* ICU_0_PRESETN_I */
251 	DEF_RST(3, 8, 1, 9),		/* GIC_0_GICRESET_N */
252 	DEF_RST(3, 9, 1, 10),		/* GIC_0_DBG_GICRESET_N */
256 	DEF_RST(7, 0, 3, 1),		/* GTM_3_PRESETZ */
257 	DEF_RST(7, 1, 3, 2),		/* GTM_4_PRESETZ */
264 	DEF_RST(7, 8, 3, 9),		/* WDT_3_RESET */
265 	DEF_RST(9, 5, 4, 6),		/* SCIF_0_RST_SYSTEM_N */
266 	DEF_RST(9, 8, 4, 9),		/* RIIC_0_MRST */
267 	DEF_RST(9, 9, 4, 10),		/* RIIC_1_MRST */
268 	DEF_RST(9, 10, 4, 11),		/* RIIC_2_MRST */
269 	DEF_RST(9, 11, 4, 12),		/* RIIC_3_MRST */
270 	DEF_RST(9, 12, 4, 13),		/* RIIC_4_MRST */
271 	DEF_RST(9, 13, 4, 14),		/* RIIC_5_MRST */
272 	DEF_RST(9, 14, 4, 15),		/* RIIC_6_MRST */
273 	DEF_RST(9, 15, 4, 16),		/* RIIC_7_MRST */
277 	DEF_RST(10, 9, 4, 26),		/* SDHI_2_IXRST */
282 	DEF_RST(12, 9, 5, 26),		/* CRU_1_ARESETN */
289 	DEF_RST(13, 0, 6, 1),		/* CRU_3_S_RESETN */