Lines Matching +full:1 +full:- +full:5
1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/renesas,r9a09g057-cpg.h>
15 #include "rzv2h-cpg.h"
56 {0, 1},
57 {1, 2},
65 {1, 4},
71 {1, 4},
92 DEF_FIXED(".pllcm33_div4", CLK_PLLCM33_DIV4, CLK_PLLCM33, 1, 4),
95 DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16),
97 DEF_FIXED(".pllcln_div2", CLK_PLLCLN_DIV2, CLK_PLLCLN, 1, 2),
98 DEF_FIXED(".pllcln_div8", CLK_PLLCLN_DIV8, CLK_PLLCLN, 1, 8),
99 DEF_FIXED(".pllcln_div16", CLK_PLLCLN_DIV16, CLK_PLLCLN, 1, 16),
102 DEF_FIXED(".plldty_acpu_div2", CLK_PLLDTY_ACPU_DIV2, CLK_PLLDTY_ACPU, 1, 2),
103 DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4),
104 DEF_FIXED(".plldty_div16", CLK_PLLDTY_DIV16, CLK_PLLDTY, 1, 16),
106 DEF_FIXED(".plldty_rcpu_div4", CLK_PLLDTY_RCPU_DIV4, CLK_PLLDTY_RCPU, 1, 4),
114 DEF_FIXED("sys_0_pclk", R9A09G057_SYS_0_PCLK, CLK_QEXTAL, 1, 1),
123 DEF_FIXED("iotop_0_shclk", R9A09G057_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1, 1),
128 BUS_MSTOP(5, BIT(9))),
129 DEF_MOD("dmac_1_aclk", CLK_PLLDTY_ACPU_DIV2, 0, 1, 0, 1,
137 DEF_MOD_CRITICAL("icu_0_pclk_i", CLK_PLLCM33_DIV16, 0, 5, 0, 5,
139 DEF_MOD_CRITICAL("gic_0_gicclk", CLK_PLLDTY_ACPU_DIV4, 1, 3, 0, 19,
140 BUS_MSTOP(3, BIT(5))),
142 BUS_MSTOP(5, BIT(10))),
144 BUS_MSTOP(5, BIT(11))),
145 DEF_MOD("gtm_2_pclk", CLK_PLLCLN_DIV16, 4, 5, 2, 5,
162 BUS_MSTOP(1, BIT(0))),
164 BUS_MSTOP(1, BIT(0))),
166 BUS_MSTOP(5, BIT(12))),
167 DEF_MOD("wdt_2_clk_loco", CLK_QEXTAL, 5, 0, 2, 16,
168 BUS_MSTOP(5, BIT(12))),
169 DEF_MOD("wdt_3_clkp", CLK_PLLCLN_DIV16, 5, 1, 2, 17,
170 BUS_MSTOP(5, BIT(13))),
171 DEF_MOD("wdt_3_clk_loco", CLK_QEXTAL, 5, 2, 2, 18,
172 BUS_MSTOP(5, BIT(13))),
178 BUS_MSTOP(1, BIT(1))),
179 DEF_MOD("riic_1_ckm", CLK_PLLCLN_DIV16, 9, 5, 4, 21,
180 BUS_MSTOP(1, BIT(2))),
182 BUS_MSTOP(1, BIT(3))),
184 BUS_MSTOP(1, BIT(4))),
186 BUS_MSTOP(1, BIT(5))),
188 BUS_MSTOP(1, BIT(6))),
190 BUS_MSTOP(1, BIT(7))),
192 BUS_MSTOP(1, BIT(8))),
193 DEF_MOD("sdhi_0_imclk", CLK_PLLCLN_DIV8, 10, 3, 5, 3,
195 DEF_MOD("sdhi_0_imclk2", CLK_PLLCLN_DIV8, 10, 4, 5, 4,
197 DEF_MOD("sdhi_0_clk_hs", CLK_PLLCLN_DIV2, 10, 5, 5, 5,
199 DEF_MOD("sdhi_0_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 6, 5, 6,
201 DEF_MOD("sdhi_1_imclk", CLK_PLLCLN_DIV8, 10, 7, 5, 7,
203 DEF_MOD("sdhi_1_imclk2", CLK_PLLCLN_DIV8, 10, 8, 5, 8,
205 DEF_MOD("sdhi_1_clk_hs", CLK_PLLCLN_DIV2, 10, 9, 5, 9,
207 DEF_MOD("sdhi_1_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 10, 5, 10,
209 DEF_MOD("sdhi_2_imclk", CLK_PLLCLN_DIV8, 10, 11, 5, 11,
211 DEF_MOD("sdhi_2_imclk2", CLK_PLLCLN_DIV8, 10, 12, 5, 12,
213 DEF_MOD("sdhi_2_clk_hs", CLK_PLLCLN_DIV2, 10, 13, 5, 13,
215 DEF_MOD("sdhi_2_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14,
223 DEF_MOD("cru_1_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 5, 6, 21,
224 BUS_MSTOP(9, BIT(5))),
226 BUS_MSTOP(9, BIT(5))),
228 BUS_MSTOP(9, BIT(5))),
244 DEF_RST(3, 0, 1, 1), /* SYS_0_PRESETN */
245 DEF_RST(3, 1, 1, 2), /* DMAC_0_ARESETN */
246 DEF_RST(3, 2, 1, 3), /* DMAC_1_ARESETN */
247 DEF_RST(3, 3, 1, 4), /* DMAC_2_ARESETN */
248 DEF_RST(3, 4, 1, 5), /* DMAC_3_ARESETN */
249 DEF_RST(3, 5, 1, 6), /* DMAC_4_ARESETN */
250 DEF_RST(3, 6, 1, 7), /* ICU_0_PRESETN_I */
251 DEF_RST(3, 8, 1, 9), /* GIC_0_GICRESET_N */
252 DEF_RST(3, 9, 1, 10), /* GIC_0_DBG_GICRESET_N */
256 DEF_RST(7, 0, 3, 1), /* GTM_3_PRESETZ */
257 DEF_RST(7, 1, 3, 2), /* GTM_4_PRESETZ */
260 DEF_RST(7, 4, 3, 5), /* GTM_7_PRESETZ */
261 DEF_RST(7, 5, 3, 6), /* WDT_0_RESET */
265 DEF_RST(9, 5, 4, 6), /* SCIF_0_RST_SYSTEM_N */
278 DEF_RST(12, 5, 5, 22), /* CRU_0_PRESETN */
279 DEF_RST(12, 6, 5, 23), /* CRU_0_ARESETN */
280 DEF_RST(12, 7, 5, 24), /* CRU_0_S_RESETN */
281 DEF_RST(12, 8, 5, 25), /* CRU_1_PRESETN */
282 DEF_RST(12, 9, 5, 26), /* CRU_1_ARESETN */
283 DEF_RST(12, 10, 5, 27), /* CRU_1_S_RESETN */
284 DEF_RST(12, 11, 5, 28), /* CRU_2_PRESETN */
285 DEF_RST(12, 12, 5, 29), /* CRU_2_ARESETN */
286 DEF_RST(12, 13, 5, 30), /* CRU_2_S_RESETN */
287 DEF_RST(12, 14, 5, 31), /* CRU_3_PRESETN */
289 DEF_RST(13, 0, 6, 1), /* CRU_3_S_RESETN */