clk/renesas/r9a09g047-cpg.c

1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/renesas,r9a09g047-cpg.h>
15 #include "rzv2h-cpg.h"
53 	{3, 8},
66 	{2, 8},
89 	DEF_FIXED(".pllcln_div8", CLK_PLLCLN_DIV8, CLK_PLLCLN, 1, 8),
130 	DEF_MOD("scif_0_clk_pck",		CLK_PLLCM33_DIV16, 8, 15, 4, 15,
132 	DEF_MOD("riic_8_ckm",			CLK_PLLCM33_DIV16, 9, 3, 4, 19,
134 	DEF_MOD("riic_0_ckm",			CLK_PLLCLN_DIV16, 9, 4, 4, 20,
136 	DEF_MOD("riic_1_ckm",			CLK_PLLCLN_DIV16, 9, 5, 4, 21,
138 	DEF_MOD("riic_2_ckm",			CLK_PLLCLN_DIV16, 9, 6, 4, 22,
140 	DEF_MOD("riic_3_ckm",			CLK_PLLCLN_DIV16, 9, 7, 4, 23,
142 	DEF_MOD("riic_4_ckm",			CLK_PLLCLN_DIV16, 9, 8, 4, 24,
144 	DEF_MOD("riic_5_ckm",			CLK_PLLCLN_DIV16, 9, 9, 4, 25,
146 	DEF_MOD("riic_6_ckm",			CLK_PLLCLN_DIV16, 9, 10, 4, 26,
148 	DEF_MOD("riic_7_ckm",			CLK_PLLCLN_DIV16, 9, 11, 4, 27,
149 						BUS_MSTOP(1, BIT(8))),
150 	DEF_MOD("canfd_0_pclk",			CLK_PLLCLN_DIV16, 9, 12, 4, 28,
152 	DEF_MOD("canfd_0_clk_ram",		CLK_PLLCLN_DIV8, 9, 13, 4, 29,
154 	DEF_MOD("canfd_0_clkc",			CLK_PLLCLN_DIV20, 9, 14, 4, 30,
157 						BUS_MSTOP(8, BIT(2))),
159 						BUS_MSTOP(8, BIT(2))),
161 						BUS_MSTOP(8, BIT(2))),
163 						BUS_MSTOP(8, BIT(2))),
165 						BUS_MSTOP(8, BIT(3))),
166 	DEF_MOD("sdhi_1_imclk2",		CLK_PLLCLN_DIV8, 10, 8, 5, 8,
167 						BUS_MSTOP(8, BIT(3))),
168 	DEF_MOD("sdhi_1_clk_hs",		CLK_PLLCLN_DIV2, 10, 9, 5, 9,
169 						BUS_MSTOP(8, BIT(3))),
171 						BUS_MSTOP(8, BIT(3))),
173 						BUS_MSTOP(8, BIT(4))),
175 						BUS_MSTOP(8, BIT(4))),
177 						BUS_MSTOP(8, BIT(4))),
179 						BUS_MSTOP(8, BIT(4))),
181 						BUS_MSTOP(9, BIT(4))),
183 						BUS_MSTOP(9, BIT(4))),
185 						BUS_MSTOP(9, BIT(4))),
186 	DEF_MOD("tsu_1_pclk",			CLK_QEXTAL, 16, 10, 8, 10,
193 	DEF_RST(3, 8, 1, 9),		/* GIC_0_GICRESET_N */
194 	DEF_RST(3, 9, 1, 10),		/* GIC_0_DBG_GICRESET_N */
196 	DEF_RST(7, 7, 3, 8),		/* WDT_2_RESET */
197 	DEF_RST(7, 8, 3, 9),		/* WDT_3_RESET */
198 	DEF_RST(9, 5, 4, 6),		/* SCIF_0_RST_SYSTEM_N */
199 	DEF_RST(9, 8, 4, 9),		/* RIIC_0_MRST */
200 	DEF_RST(9, 9, 4, 10),		/* RIIC_1_MRST */
201 	DEF_RST(9, 10, 4, 11),		/* RIIC_2_MRST */
202 	DEF_RST(9, 11, 4, 12),		/* RIIC_3_MRST */
203 	DEF_RST(9, 12, 4, 13),		/* RIIC_4_MRST */
204 	DEF_RST(9, 13, 4, 14),		/* RIIC_5_MRST */
205 	DEF_RST(9, 14, 4, 15),		/* RIIC_6_MRST */
206 	DEF_RST(9, 15, 4, 16),		/* RIIC_7_MRST */
211 	DEF_RST(10, 8, 4, 25),		/* SDHI_1_IXRST */
212 	DEF_RST(10, 9, 4, 26),		/* SDHI_2_IXRST */
216 	DEF_RST(15, 8, 7, 9),		/* TSU_1_PRESETN */