clk/renesas/r9a09g047-cpg.c

1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/renesas,r9a09g047-cpg.h>
15 #include "rzv2h-cpg.h"
117 						BUS_MSTOP(3, BIT(5))),
119 						BUS_MSTOP(1, BIT(0))),
121 						BUS_MSTOP(1, BIT(0))),
123 						BUS_MSTOP(5, BIT(12))),
125 						BUS_MSTOP(5, BIT(12))),
127 						BUS_MSTOP(5, BIT(13))),
129 						BUS_MSTOP(5, BIT(13))),
131 						BUS_MSTOP(3, BIT(14))),
133 						BUS_MSTOP(3, BIT(13))),
135 						BUS_MSTOP(1, BIT(1))),
137 						BUS_MSTOP(1, BIT(2))),
139 						BUS_MSTOP(1, BIT(3))),
141 						BUS_MSTOP(1, BIT(4))),
143 						BUS_MSTOP(1, BIT(5))),
145 						BUS_MSTOP(1, BIT(6))),
146 	DEF_MOD("riic_6_ckm",			CLK_PLLCLN_DIV16, 9, 10, 4, 26,
147 						BUS_MSTOP(1, BIT(7))),
149 						BUS_MSTOP(1, BIT(8))),
151 						BUS_MSTOP(10, BIT(14))),
153 						BUS_MSTOP(10, BIT(14))),
155 						BUS_MSTOP(10, BIT(14))),
156 	DEF_MOD("sdhi_0_imclk",			CLK_PLLCLN_DIV8, 10, 3, 5, 3,
157 						BUS_MSTOP(8, BIT(2))),
158 	DEF_MOD("sdhi_0_imclk2",		CLK_PLLCLN_DIV8, 10, 4, 5, 4,
159 						BUS_MSTOP(8, BIT(2))),
160 	DEF_MOD("sdhi_0_clk_hs",		CLK_PLLCLN_DIV2, 10, 5, 5, 5,
161 						BUS_MSTOP(8, BIT(2))),
162 	DEF_MOD("sdhi_0_aclk",			CLK_PLLDTY_ACPU_DIV4, 10, 6, 5, 6,
163 						BUS_MSTOP(8, BIT(2))),
164 	DEF_MOD("sdhi_1_imclk",			CLK_PLLCLN_DIV8, 10, 7, 5, 7,
165 						BUS_MSTOP(8, BIT(3))),
166 	DEF_MOD("sdhi_1_imclk2",		CLK_PLLCLN_DIV8, 10, 8, 5, 8,
167 						BUS_MSTOP(8, BIT(3))),
168 	DEF_MOD("sdhi_1_clk_hs",		CLK_PLLCLN_DIV2, 10, 9, 5, 9,
169 						BUS_MSTOP(8, BIT(3))),
170 	DEF_MOD("sdhi_1_aclk",			CLK_PLLDTY_ACPU_DIV4, 10, 10, 5, 10,
171 						BUS_MSTOP(8, BIT(3))),
172 	DEF_MOD("sdhi_2_imclk",			CLK_PLLCLN_DIV8, 10, 11, 5, 11,
173 						BUS_MSTOP(8, BIT(4))),
174 	DEF_MOD("sdhi_2_imclk2",		CLK_PLLCLN_DIV8, 10, 12, 5, 12,
175 						BUS_MSTOP(8, BIT(4))),
176 	DEF_MOD("sdhi_2_clk_hs",		CLK_PLLCLN_DIV2, 10, 13, 5, 13,
177 						BUS_MSTOP(8, BIT(4))),
178 	DEF_MOD("sdhi_2_aclk",			CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14,
179 						BUS_MSTOP(8, BIT(4))),
181 						BUS_MSTOP(9, BIT(4))),
183 						BUS_MSTOP(9, BIT(4))),
185 						BUS_MSTOP(9, BIT(4))),
186 	DEF_MOD("tsu_1_pclk",			CLK_QEXTAL, 16, 10, 8, 10,
187 						BUS_MSTOP(2, BIT(15))),
194 	DEF_RST(3, 9, 1, 10),		/* GIC_0_DBG_GICRESET_N */
200 	DEF_RST(9, 9, 4, 10),		/* RIIC_1_MRST */
201 	DEF_RST(9, 10, 4, 11),		/* RIIC_2_MRST */
207 	DEF_RST(10, 0, 4, 17),		/* RIIC_8_MRST */
208 	DEF_RST(10, 1, 4, 18),		/* CANFD_0_RSTP_N */
209 	DEF_RST(10, 2, 4, 19),		/* CANFD_0_RSTC_N */
210 	DEF_RST(10, 7, 4, 24),		/* SDHI_0_IXRST */
211 	DEF_RST(10, 8, 4, 25),		/* SDHI_1_IXRST */
212 	DEF_RST(10, 9, 4, 26),		/* SDHI_2_IXRST */