clk/renesas/r9a09g047-cpg.c

1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/renesas,r9a09g047-cpg.h>
15 #include "rzv2h-cpg.h"
50 	{0, 1},
51 	{1, 2},
59 	{1, 4},
65 	{1, 4},
86 	DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16),
88 	DEF_FIXED(".pllcln_div2", CLK_PLLCLN_DIV2, CLK_PLLCLN, 1, 2),
89 	DEF_FIXED(".pllcln_div8", CLK_PLLCLN_DIV8, CLK_PLLCLN, 1, 8),
90 	DEF_FIXED(".pllcln_div16", CLK_PLLCLN_DIV16, CLK_PLLCLN, 1, 16),
91 	DEF_FIXED(".pllcln_div20", CLK_PLLCLN_DIV20, CLK_PLLCLN, 1, 20),
94 	DEF_FIXED(".plldty_acpu_div2", CLK_PLLDTY_ACPU_DIV2, CLK_PLLDTY_ACPU, 1, 2),
95 	DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4),
96 	DEF_FIXED(".plldty_div16", CLK_PLLDTY_DIV16, CLK_PLLDTY, 1, 16),
101 	DEF_FIXED("sys_0_pclk", R9A09G047_SYS_0_PCLK, CLK_QEXTAL, 1, 1),
110 	DEF_FIXED("iotop_0_shclk", R9A09G047_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1, 1),
116 	DEF_MOD_CRITICAL("gic_0_gicclk",	CLK_PLLDTY_ACPU_DIV4, 1, 3, 0, 19,
119 						BUS_MSTOP(1, BIT(0))),
121 						BUS_MSTOP(1, BIT(0))),
126 	DEF_MOD("wdt_3_clkp",			CLK_PLLCLN_DIV16, 5, 1, 2, 17,
132 	DEF_MOD("riic_8_ckm",			CLK_PLLCM33_DIV16, 9, 3, 4, 19,
134 	DEF_MOD("riic_0_ckm",			CLK_PLLCLN_DIV16, 9, 4, 4, 20,
135 						BUS_MSTOP(1, BIT(1))),
136 	DEF_MOD("riic_1_ckm",			CLK_PLLCLN_DIV16, 9, 5, 4, 21,
137 						BUS_MSTOP(1, BIT(2))),
138 	DEF_MOD("riic_2_ckm",			CLK_PLLCLN_DIV16, 9, 6, 4, 22,
139 						BUS_MSTOP(1, BIT(3))),
140 	DEF_MOD("riic_3_ckm",			CLK_PLLCLN_DIV16, 9, 7, 4, 23,
141 						BUS_MSTOP(1, BIT(4))),
142 	DEF_MOD("riic_4_ckm",			CLK_PLLCLN_DIV16, 9, 8, 4, 24,
143 						BUS_MSTOP(1, BIT(5))),
144 	DEF_MOD("riic_5_ckm",			CLK_PLLCLN_DIV16, 9, 9, 4, 25,
145 						BUS_MSTOP(1, BIT(6))),
146 	DEF_MOD("riic_6_ckm",			CLK_PLLCLN_DIV16, 9, 10, 4, 26,
147 						BUS_MSTOP(1, BIT(7))),
148 	DEF_MOD("riic_7_ckm",			CLK_PLLCLN_DIV16, 9, 11, 4, 27,
149 						BUS_MSTOP(1, BIT(8))),
150 	DEF_MOD("canfd_0_pclk",			CLK_PLLCLN_DIV16, 9, 12, 4, 28,
152 	DEF_MOD("canfd_0_clk_ram",		CLK_PLLCLN_DIV8, 9, 13, 4, 29,
154 	DEF_MOD("canfd_0_clkc",			CLK_PLLCLN_DIV20, 9, 14, 4, 30,
168 	DEF_MOD("sdhi_1_clk_hs",		CLK_PLLCLN_DIV2, 10, 9, 5, 9,
181 						BUS_MSTOP(9, BIT(4))),
183 						BUS_MSTOP(9, BIT(4))),
185 						BUS_MSTOP(9, BIT(4))),
191 	DEF_RST(3, 0, 1, 1),		/* SYS_0_PRESETN */
192 	DEF_RST(3, 6, 1, 7),		/* ICU_0_PRESETN_I */
193 	DEF_RST(3, 8, 1, 9),		/* GIC_0_GICRESET_N */
194 	DEF_RST(3, 9, 1, 10),		/* GIC_0_DBG_GICRESET_N */
197 	DEF_RST(7, 8, 3, 9),		/* WDT_3_RESET */
198 	DEF_RST(9, 5, 4, 6),		/* SCIF_0_RST_SYSTEM_N */
199 	DEF_RST(9, 8, 4, 9),		/* RIIC_0_MRST */
200 	DEF_RST(9, 9, 4, 10),		/* RIIC_1_MRST */
201 	DEF_RST(9, 10, 4, 11),		/* RIIC_2_MRST */
202 	DEF_RST(9, 11, 4, 12),		/* RIIC_3_MRST */
203 	DEF_RST(9, 12, 4, 13),		/* RIIC_4_MRST */
204 	DEF_RST(9, 13, 4, 14),		/* RIIC_5_MRST */
205 	DEF_RST(9, 14, 4, 15),		/* RIIC_6_MRST */
206 	DEF_RST(9, 15, 4, 16),		/* RIIC_7_MRST */
208 	DEF_RST(10, 1, 4, 18),		/* CANFD_0_RSTP_N */
212 	DEF_RST(10, 9, 4, 26),		/* SDHI_2_IXRST */
216 	DEF_RST(15, 8, 7, 9),		/* TSU_1_PRESETN */