Lines Matching +full:0 +full:x29000
58 { P_XO, 0 },
70 .offset = 0x20000,
73 .enable_reg = 0x0b000,
74 .enable_mask = BIT(0),
98 .offset = 0x20000,
112 .offset = 0x20000,
126 .offset = 0x22000,
129 .enable_reg = 0x0b000,
141 .offset = 0x22000,
155 .offset = 0x21000,
158 .enable_reg = 0x0b000,
170 .offset = 0x21000,
184 .halt_reg = 0x3400c,
186 .enable_reg = 0x3400c,
205 { P_XO, 0 },
216 { P_XO, 0 },
227 { P_XO, 0 },
240 { P_XO, 0 },
254 { P_XO, 0 },
267 { P_XO, 0 },
280 { P_XO, 0 },
296 { P_XO, 0 },
309 { P_XO, 0 },
323 { P_XO, 0 },
335 { P_USB3PHY_0_PIPE, 0 },
348 { P_XO, 0 },
362 { P_XO, 0 },
376 { P_XO, 0 },
389 { P_XO, 0 },
403 { P_XO, 0 },
418 { P_XO, 0 },
425 F(24000000, P_XO, 1, 0, 0),
426 F(50000000, P_GPLL0, 16, 0, 0),
427 F(100000000, P_GPLL0, 8, 0, 0),
432 .cmd_rcgr = 0x2400c,
445 F(533000000, P_GPLL0, 1.5, 0, 0),
450 .cmd_rcgr = 0x24004,
463 F(9600000, P_XO, 2.5, 0, 0),
464 F(24000000, P_XO, 1, 0, 0),
465 F(50000000, P_GPLL0, 16, 0, 0),
470 .cmd_rcgr = 0x02018,
484 F(4800000, P_XO, 5, 0, 0),
487 F(24000000, P_XO, 1, 0, 0),
489 F(50000000, P_GPLL0, 16, 0, 0),
494 .cmd_rcgr = 0x02004,
508 .cmd_rcgr = 0x03018,
521 .cmd_rcgr = 0x03004,
535 .cmd_rcgr = 0x04018,
548 .cmd_rcgr = 0x04004,
562 .cmd_rcgr = 0x05018,
575 .cmd_rcgr = 0x05004,
589 .cmd_rcgr = 0x06018,
602 .cmd_rcgr = 0x06004,
616 .cmd_rcgr = 0x07018,
629 .cmd_rcgr = 0x07004,
646 F(24000000, P_XO, 1, 0, 0),
656 F(64000000, P_GPLL0, 12.5, 0, 0),
661 .cmd_rcgr = 0x0202c,
675 .cmd_rcgr = 0x0302c,
689 .cmd_rcgr = 0x0402c,
703 .cmd_rcgr = 0x0502c,
717 .cmd_rcgr = 0x0602c,
731 .cmd_rcgr = 0x0702c,
745 F(160000000, P_GPLL0, 5, 0, 0),
750 .cmd_rcgr = 0x16004,
763 .halt_reg = 0x1600c,
766 .enable_reg = 0x0b004,
780 .halt_reg = 0x24018,
783 .enable_reg = 0x0b004,
784 .enable_mask = BIT(0),
798 .halt_reg = 0x2401c,
801 .enable_reg = 0x0b004,
816 .halt_reg = 0x2024,
818 .enable_reg = 0x2024,
819 .enable_mask = BIT(0),
833 .halt_reg = 0x02020,
835 .enable_reg = 0x02020,
836 .enable_mask = BIT(0),
850 .halt_reg = 0x03024,
852 .enable_reg = 0x03024,
853 .enable_mask = BIT(0),
867 .halt_reg = 0x03020,
869 .enable_reg = 0x03020,
870 .enable_mask = BIT(0),
884 .halt_reg = 0x04024,
886 .enable_reg = 0x04024,
887 .enable_mask = BIT(0),
901 .halt_reg = 0x04020,
903 .enable_reg = 0x04020,
904 .enable_mask = BIT(0),
918 .halt_reg = 0x05024,
920 .enable_reg = 0x05024,
921 .enable_mask = BIT(0),
935 .halt_reg = 0x05020,
937 .enable_reg = 0x05020,
938 .enable_mask = BIT(0),
952 .halt_reg = 0x06024,
954 .enable_reg = 0x06024,
955 .enable_mask = BIT(0),
969 .halt_reg = 0x06020,
971 .enable_reg = 0x06020,
972 .enable_mask = BIT(0),
986 .halt_reg = 0x07024,
988 .enable_reg = 0x07024,
989 .enable_mask = BIT(0),
1003 .halt_reg = 0x07020,
1005 .enable_reg = 0x07020,
1006 .enable_mask = BIT(0),
1020 .halt_reg = 0x02040,
1022 .enable_reg = 0x02040,
1023 .enable_mask = BIT(0),
1037 .halt_reg = 0x03040,
1039 .enable_reg = 0x03040,
1040 .enable_mask = BIT(0),
1054 .halt_reg = 0x04054,
1056 .enable_reg = 0x04054,
1057 .enable_mask = BIT(0),
1071 .halt_reg = 0x05040,
1073 .enable_reg = 0x05040,
1074 .enable_mask = BIT(0),
1088 .halt_reg = 0x06040,
1090 .enable_reg = 0x06040,
1091 .enable_mask = BIT(0),
1105 .halt_reg = 0x07040,
1107 .enable_reg = 0x07040,
1108 .enable_mask = BIT(0),
1122 F(240000000, P_GPLL4, 5, 0, 0),
1127 .cmd_rcgr = 0x28018,
1140 .halt_reg = 0x28038,
1142 .enable_reg = 0x28038,
1143 .enable_mask = BIT(0),
1157 .halt_reg = 0x2e07c,
1159 .enable_reg = 0x2e07c,
1160 .enable_mask = BIT(0),
1174 .cmd_rcgr = 0x29018,
1187 .halt_reg = 0x29038,
1189 .enable_reg = 0x29038,
1190 .enable_mask = BIT(0),
1204 .halt_reg = 0x2e08c,
1206 .enable_reg = 0x2e08c,
1207 .enable_mask = BIT(0),
1221 F(342857143, P_GPLL4, 3.5, 0, 0),
1226 .cmd_rcgr = 0x2a018,
1239 .halt_reg = 0x2a038,
1241 .enable_reg = 0x2a038,
1242 .enable_mask = BIT(0),
1256 .halt_reg = 0x2e080,
1258 .enable_reg = 0x2e080,
1259 .enable_mask = BIT(0),
1273 .cmd_rcgr = 0x2b018,
1286 .halt_reg = 0x2b038,
1288 .enable_reg = 0x2b038,
1289 .enable_mask = BIT(0),
1303 .halt_reg = 0x2e090,
1305 .enable_reg = 0x2e090,
1306 .enable_mask = BIT(0),
1320 .cmd_rcgr = 0x28020,
1333 .halt_reg = 0x2803c,
1335 .enable_reg = 0x2803c,
1336 .enable_mask = BIT(0),
1350 .halt_reg = 0x28040,
1352 .enable_reg = 0x28040,
1353 .enable_mask = BIT(0),
1367 .halt_reg = 0x2e048,
1369 .enable_reg = 0x2e048,
1370 .enable_mask = BIT(0),
1384 .cmd_rcgr = 0x29020,
1397 .halt_reg = 0x2903c,
1399 .enable_reg = 0x2903c,
1400 .enable_mask = BIT(0),
1414 .halt_reg = 0x29040,
1416 .enable_reg = 0x29040,
1417 .enable_mask = BIT(0),
1431 .halt_reg = 0x2e04c,
1433 .enable_reg = 0x2e04c,
1434 .enable_mask = BIT(0),
1448 .cmd_rcgr = 0x2a020,
1461 .halt_reg = 0x2a03c,
1463 .enable_reg = 0x2a03c,
1464 .enable_mask = BIT(0),
1478 .halt_reg = 0x2a040,
1480 .enable_reg = 0x2a040,
1481 .enable_mask = BIT(0),
1495 .halt_reg = 0x2e050,
1497 .enable_reg = 0x2e050,
1498 .enable_mask = BIT(0),
1512 .cmd_rcgr = 0x2b020,
1525 .halt_reg = 0x2b03c,
1527 .enable_reg = 0x2b03c,
1528 .enable_mask = BIT(0),
1542 .halt_reg = 0x2b040,
1544 .enable_reg = 0x2b040,
1545 .enable_mask = BIT(0),
1559 .halt_reg = 0x2e054,
1561 .enable_reg = 0x2e054,
1562 .enable_mask = BIT(0),
1576 .reg = 0x28064,
1590 .halt_reg = 0x28044,
1593 .enable_reg = 0x28044,
1594 .enable_mask = BIT(0),
1608 .reg = 0x29064,
1622 .halt_reg = 0x29044,
1625 .enable_reg = 0x29044,
1626 .enable_mask = BIT(0),
1640 .reg = 0x2a064,
1654 .halt_reg = 0x2a044,
1657 .enable_reg = 0x2a044,
1658 .enable_mask = BIT(0),
1672 .reg = 0x2b064,
1686 .halt_reg = 0x2b044,
1689 .enable_reg = 0x2b044,
1690 .enable_mask = BIT(0),
1704 F(24000000, P_XO, 1, 0, 0),
1705 F(100000000, P_GPLL0, 8, 0, 0),
1710 .cmd_rcgr = 0x28028,
1723 .halt_reg = 0x28028,
1725 .enable_reg = 0x28028,
1741 .cmd_rcgr = 0x29028,
1754 .halt_reg = 0x29028,
1756 .enable_reg = 0x29028,
1771 .cmd_rcgr = 0x2a028,
1784 .halt_reg = 0x2a028,
1786 .enable_reg = 0x2a028,
1801 .cmd_rcgr = 0x2b028,
1814 .halt_reg = 0x2b028,
1816 .enable_reg = 0x2b028,
1836 .cmd_rcgr = 0x28004,
1850 .halt_reg = 0x28034,
1852 .enable_reg = 0x28034,
1853 .enable_mask = BIT(0),
1867 .halt_reg = 0x29034,
1869 .enable_reg = 0x29034,
1870 .enable_mask = BIT(0),
1884 .halt_reg = 0x2a034,
1886 .enable_reg = 0x2a034,
1887 .enable_mask = BIT(0),
1901 .halt_reg = 0x2b034,
1903 .enable_reg = 0x2b034,
1904 .enable_mask = BIT(0),
1918 F(24000000, P_XO, 1, 0, 0),
1923 .cmd_rcgr = 0x2c018,
1937 .halt_reg = 0x2c048,
1939 .enable_reg = 0x2c048,
1940 .enable_mask = BIT(0),
1954 F(100000000, P_GPLL0, 8, 0, 0),
1955 F(200000000, P_GPLL0, 4, 0, 0),
1960 .cmd_rcgr = 0x2c004,
1974 .halt_reg = 0x2c044,
1976 .enable_reg = 0x2c044,
1977 .enable_mask = BIT(0),
1991 .halt_reg = 0x2e058,
1993 .enable_reg = 0x2e058,
1994 .enable_mask = BIT(0),
2008 .halt_reg = 0x2e084,
2010 .enable_reg = 0x2e084,
2011 .enable_mask = BIT(0),
2025 F(24000000, P_XO, 1, 0, 0),
2031 .cmd_rcgr = 0x2c02c,
2045 .reg = 0x2c040,
2046 .shift = 0,
2060 .halt_reg = 0x2c04c,
2062 .enable_reg = 0x2c04c,
2063 .enable_mask = BIT(0),
2077 .reg = 0x2C074,
2093 .halt_reg = 0x2c054,
2096 .enable_reg = 0x2c054,
2097 .enable_mask = BIT(0),
2111 .halt_reg = 0x2c058,
2113 .enable_reg = 0x2c058,
2114 .enable_mask = BIT(0),
2132 F(96000000, P_GPLL2, 12, 0, 0),
2133 F(177777778, P_GPLL0, 4.5, 0, 0),
2134 F(192000000, P_GPLL2, 6, 0, 0),
2135 F(384000000, P_GPLL2, 3, 0, 0),
2136 F(400000000, P_GPLL0, 2, 0, 0),
2141 .cmd_rcgr = 0x33004,
2155 .halt_reg = 0x3302c,
2157 .enable_reg = 0x3302c,
2158 .enable_mask = BIT(0),
2172 F(150000000, P_GPLL4, 8, 0, 0),
2173 F(300000000, P_GPLL4, 4, 0, 0),
2178 .cmd_rcgr = 0x33018,
2192 .halt_reg = 0x33030,
2194 .enable_reg = 0x33030,
2195 .enable_mask = BIT(0),
2209 F(24000000, P_XO, 1, 0, 0),
2210 F(50000000, P_GPLL0, 16, 0, 0),
2211 F(80000000, P_GPLL0, 10, 0, 0),
2212 F(100000000, P_GPLL0, 8, 0, 0),
2217 .cmd_rcgr = 0x31004,
2231 .halt_reg = 0x16010,
2234 .enable_reg = 0xb004,
2248 .halt_reg = 0x16014,
2251 .enable_reg = 0xb004,
2265 .halt_reg = 0x1702c,
2267 .enable_reg = 0x1702c,
2268 .enable_mask = BIT(0),
2282 .halt_reg = 0x17030,
2284 .enable_reg = 0x17030,
2285 .enable_mask = BIT(0),
2299 .halt_reg = 0x17034,
2301 .enable_reg = 0x17034,
2302 .enable_mask = BIT(0),
2316 .halt_reg = 0x17080,
2318 .enable_reg = 0x17080,
2319 .enable_mask = BIT(0),
2333 .halt_reg = 0x2d064,
2335 .enable_reg = 0x2d064,
2336 .enable_mask = BIT(0),
2350 .halt_reg = 0x2d068,
2352 .enable_reg = 0x2d068,
2353 .enable_mask = BIT(0),
2367 .halt_reg = 0x32010,
2369 .enable_reg = 0x32010,
2370 .enable_mask = BIT(0),
2384 .halt_reg = 0x32014,
2386 .enable_reg = 0x32014,
2387 .enable_mask = BIT(0),
2401 .halt_reg = 0x01004,
2404 .enable_reg = 0x0b004,
2419 .halt_reg = 0x17040,
2421 .enable_reg = 0x17040,
2422 .enable_mask = BIT(0),
2436 .halt_reg = 0x13024,
2439 .enable_reg = 0x0b004,
2454 .halt_reg = 0x1704c,
2456 .enable_reg = 0x1704c,
2457 .enable_mask = BIT(0),
2471 .halt_reg = 0x1705c,
2473 .enable_reg = 0x1705c,
2474 .enable_mask = BIT(0),
2488 .halt_reg = 0x1706c,
2490 .enable_reg = 0x1706c,
2491 .enable_mask = BIT(0),
2505 .halt_reg = 0x3a004,
2507 .enable_reg = 0x3a004,
2508 .enable_mask = BIT(0),
2522 .halt_reg = 0x3a00c,
2524 .enable_reg = 0x3a00c,
2525 .enable_mask = BIT(0),
2539 .halt_reg = 0x28030,
2541 .enable_reg = 0x28030,
2542 .enable_mask = BIT(0),
2556 .halt_reg = 0x29030,
2558 .enable_reg = 0x29030,
2559 .enable_mask = BIT(0),
2573 .halt_reg = 0x2a030,
2575 .enable_reg = 0x2a030,
2576 .enable_mask = BIT(0),
2590 .halt_reg = 0x2b030,
2592 .enable_reg = 0x2b030,
2593 .enable_mask = BIT(0),
2607 .halt_reg = 0x2c05c,
2609 .enable_reg = 0x2c05c,
2610 .enable_mask = BIT(0),
2624 .halt_reg = 0x33034,
2626 .enable_reg = 0x33034,
2627 .enable_mask = BIT(0),
2641 F(24000000, P_XO, 1, 0, 0),
2642 F(133333333, P_GPLL0, 6, 0, 0),
2643 F(200000000, P_GPLL0, 4, 0, 0),
2644 F(342850000, P_GPLL4, 3.5, 0, 0),
2649 .cmd_rcgr = 0x2e004,
2663 .halt_reg = 0x17028,
2665 .enable_reg = 0x17028,
2666 .enable_mask = BIT(0),
2680 .halt_reg = 0x1707c,
2682 .enable_reg = 0x1707c,
2683 .enable_mask = BIT(0),
2697 .halt_reg = 0x2d060,
2699 .enable_reg = 0x2d060,
2700 .enable_mask = BIT(0),
2714 F(24000000, P_XO, 1, 0, 0),
2715 F(133333333, P_GPLL0, 6, 0, 0),
2720 .cmd_rcgr = 0x25030,
2733 F(24000000, P_XO, 1, 0, 0),
2734 F(133333333, P_GPLL0, 6, 0, 0),
2735 F(266666667, P_GPLL0, 3, 0, 0),
2740 .cmd_rcgr = 0x25078,
2753 F(240000000, P_GPLL4, 5, 0, 0),
2758 .cmd_rcgr = 0x2d004,
2771 .halt_reg = 0x17014,
2773 .enable_reg = 0x17014,
2774 .enable_mask = BIT(0),
2788 .halt_reg = 0x2d038,
2790 .enable_reg = 0x2d038,
2791 .enable_mask = BIT(0),
2805 .halt_reg = 0x2e038,
2807 .enable_reg = 0x2e038,
2808 .enable_mask = BIT(0),
2822 .halt_reg = 0x31024,
2824 .enable_reg = 0x31024,
2825 .enable_mask = BIT(0),
2853 .halt_reg = 0x30004,
2855 .enable_reg = 0x30004,
2856 .enable_mask = BIT(0),
2870 .halt_reg = 0x2d06c,
2872 .enable_reg = 0x2d06c,
2873 .enable_mask = BIT(0),
2887 F(24000000, P_XO, 1, 0, 0),
2888 F(200000000, P_GPLL0, 4, 0, 0),
2893 .cmd_rcgr = 0x2d00c,
2906 .halt_reg = 0x2d03c,
2908 .enable_reg = 0x2d03c,
2909 .enable_mask = BIT(0),
2923 .halt_reg = 0x2e034,
2925 .enable_reg = 0x2e034,
2926 .enable_mask = BIT(0),
2940 F(300000000, P_GPLL4, 4, 0, 0),
2945 .cmd_rcgr = 0x2d014,
2958 .halt_reg = 0x2d040,
2960 .enable_reg = 0x2d040,
2961 .enable_mask = BIT(0),
2975 F(600000000, P_GPLL4, 2, 0, 0),
2980 .cmd_rcgr = 0x2d01c,
3007 .halt_reg = 0x2d044,
3009 .enable_reg = 0x2d044,
3010 .enable_mask = BIT(0),
3024 F(24000000, P_XO, 1, 0, 0),
3029 .cmd_rcgr = 0x17090,
3043 .cmd_rcgr = 0x17088,
3057 .halt_reg = 0x2d078,
3059 .enable_reg = 0x2d078,
3060 .enable_mask = BIT(0),
3087 .halt_reg = 0x2d04c,
3089 .enable_reg = 0x2d04c,
3090 .enable_mask = BIT(0),
3117 .halt_reg = 0x17018,
3119 .enable_reg = 0x17018,
3120 .enable_mask = BIT(0),
3134 .halt_reg = 0x2d050,
3136 .enable_reg = 0x2d050,
3137 .enable_mask = BIT(0),
3164 .halt_reg = 0x2d054,
3166 .enable_reg = 0x2d054,
3167 .enable_mask = BIT(0),
3181 .halt_reg = 0x2d058,
3183 .enable_reg = 0x2d058,
3184 .enable_mask = BIT(0),
3198 .halt_reg = 0x2d05c,
3200 .enable_reg = 0x2d05c,
3201 .enable_mask = BIT(0),
3228 .halt_reg = 0x2d048,
3230 .enable_reg = 0x2d048,
3231 .enable_mask = BIT(0),
3245 F(24000000, P_XO, 1, 0, 0),
3246 F(100000000, P_GPLL0, 8, 0, 0),
3247 F(200000000, P_GPLL0, 4, 0, 0),
3248 F(320000000, P_GPLL0, 2.5, 0, 0),
3249 F(400000000, P_GPLL0, 2, 0, 0),
3254 .cmd_rcgr = 0x32004,
3267 .halt_reg = 0x3200c,
3269 .enable_reg = 0x3200c,
3270 .enable_mask = BIT(0),
3284 F(533333333, P_GPLL0, 1.5, 0, 0),
3289 .cmd_rcgr = 0x25004,
3302 F(342857143, P_GPLL4, 3.5, 0, 0),
3307 { P_XO, 0 },
3314 .cmd_rcgr = 0x25028,
3327 F(533333333, P_GPLL0, 1.5, 0, 0),
3332 .cmd_rcgr = 0x17004,
3345 .halt_reg = 0x17024,
3347 .enable_reg = 0x17024,
3348 .enable_mask = BIT(0),
3362 .halt_reg = 0x17084,
3364 .enable_reg = 0x17084,
3365 .enable_mask = BIT(0),
3379 .halt_reg = 0x12040,
3381 .enable_reg = 0xb00c,
3396 .halt_reg = 0x19014,
3398 .enable_reg = 0x19014,
3399 .enable_mask = BIT(0),
3413 F(133333333, P_GPLL0, 6, 0, 0),
3418 .cmd_rcgr = 0x2700c,
3431 .cmd_rcgr = 0x27004,
3444 F(24000000, P_XO, 1, 0, 0),
3445 F(100000000, P_GPLL0, 8, 0, 0),
3450 .cmd_rcgr = 0x1c004,
3463 .halt_reg = 0x1c00c,
3465 .enable_reg = 0x1c00c,
3466 .enable_mask = BIT(0),
3480 F(24000000, P_XO, 1, 0, 0),
3481 F(200000000, P_GPLL0, 4, 0, 0),
3486 .cmd_rcgr = 0x8004,
3499 .cmd_rcgr = 0x9004,
3512 .cmd_rcgr = 0xa004,
3525 .halt_reg = 0x34004,
3527 .enable_reg = 0x34004,
3540 .halt_reg = 0x17074,
3542 .enable_reg = 0x17074,
3543 .enable_mask = BIT(0),
3557 .halt_reg = 0x34018,
3559 .enable_reg = 0x34018,
3560 .enable_mask = BIT(0),
3574 .halt_reg = 0x17048,
3576 .enable_reg = 0x17048,
3577 .enable_mask = BIT(0),
3591 .halt_reg = 0x17058,
3593 .enable_reg = 0x17058,
3594 .enable_mask = BIT(0),
3608 .halt_reg = 0x17068,
3610 .enable_reg = 0x17068,
3611 .enable_mask = BIT(0),
3625 .halt_reg = 0x3a008,
3627 .enable_reg = 0x3a008,
3628 .enable_mask = BIT(0),
3656 .halt_reg = 0x1701c,
3658 .enable_reg = 0x1701c,
3659 .enable_mask = BIT(0),
3673 .halt_reg = 0x17020,
3675 .enable_reg = 0x17020,
3676 .enable_mask = BIT(0),
3690 .halt_reg = 0x3401c,
3692 .enable_reg = 0x3401c,
3693 .enable_mask = BIT(0),
3917 [GCC_ADSS_BCR] = { 0x1c000, 0 },
3918 [GCC_ANOC0_TBU_BCR] = { 0x1203c, 0 },
3919 [GCC_ANOC1_TBU_BCR] = { 0x1204c, 0 },
3920 [GCC_ANOC_BCR] = { 0x2e074, 0 },
3921 [GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x38000, 0 },
3922 [GCC_APSS_TCU_BCR] = { 0x12014, 0 },
3923 [GCC_BLSP1_BCR] = { 0x01000, 0 },
3924 [GCC_BLSP1_QUP1_BCR] = { 0x02000, 0 },
3925 [GCC_BLSP1_QUP2_BCR] = { 0x03000, 0 },
3926 [GCC_BLSP1_QUP3_BCR] = { 0x04000, 0 },
3927 [GCC_BLSP1_QUP4_BCR] = { 0x05000, 0 },
3928 [GCC_BLSP1_QUP5_BCR] = { 0x06000, 0 },
3929 [GCC_BLSP1_QUP6_BCR] = { 0x07000, 0 },
3930 [GCC_BLSP1_UART1_BCR] = { 0x02028, 0 },
3931 [GCC_BLSP1_UART2_BCR] = { 0x03028, 0 },
3932 [GCC_BLSP1_UART3_BCR] = { 0x04028, 0 },
3933 [GCC_BLSP1_UART4_BCR] = { 0x05028, 0 },
3934 [GCC_BLSP1_UART5_BCR] = { 0x06028, 0 },
3935 [GCC_BLSP1_UART6_BCR] = { 0x07028, 0 },
3936 [GCC_BOOT_ROM_BCR] = { 0x13028, 0 },
3937 [GCC_CMN_BLK_BCR] = { 0x3a000, 0 },
3938 [GCC_CMN_BLK_AHB_ARES] = { 0x3a010, 0 },
3939 [GCC_CMN_BLK_SYS_ARES] = { 0x3a010, 1 },
3940 [GCC_CMN_BLK_APU_ARES] = { 0x3a010, 2 },
3941 [GCC_CRYPTO_BCR] = { 0x16000, 0 },
3942 [GCC_DCC_BCR] = { 0x35000, 0 },
3943 [GCC_DDRSS_BCR] = { 0x11000, 0 },
3944 [GCC_IMEM_BCR] = { 0x0e000, 0 },
3945 [GCC_LPASS_BCR] = { 0x27000, 0 },
3946 [GCC_MDIO_BCR] = { 0x1703c, 0 },
3947 [GCC_MPM_BCR] = { 0x37000, 0 },
3948 [GCC_MSG_RAM_BCR] = { 0x26000, 0 },
3949 [GCC_NSS_BCR] = { 0x17000, 0 },
3950 [GCC_NSS_TBU_BCR] = { 0x12044, 0 },
3951 [GCC_NSSNOC_MEMNOC_1_ARES] = { 0x17038, 13 },
3952 [GCC_NSSNOC_PCNOC_1_ARES] = { 0x17038, 12 },
3953 [GCC_NSSNOC_SNOC_1_ARES] = { 0x17038, 11 },
3954 [GCC_NSSNOC_XO_DCD_ARES] = { 0x17038, 10 },
3955 [GCC_NSSNOC_TS_ARES] = { 0x17038, 9 },
3956 [GCC_NSSCC_ARES] = { 0x17038, 8 },
3957 [GCC_NSSNOC_NSSCC_ARES] = { 0x17038, 7 },
3958 [GCC_NSSNOC_ATB_ARES] = { 0x17038, 6 },
3959 [GCC_NSSNOC_MEMNOC_ARES] = { 0x17038, 5 },
3960 [GCC_NSSNOC_QOSGEN_REF_ARES] = { 0x17038, 4 },
3961 [GCC_NSSNOC_SNOC_ARES] = { 0x17038, 3 },
3962 [GCC_NSSNOC_TIMEOUT_REF_ARES] = { 0x17038, 2 },
3963 [GCC_NSS_CFG_ARES] = { 0x17038, 1 },
3964 [GCC_UBI0_DBG_ARES] = { 0x17038, 0 },
3965 [GCC_PCIE0PHY_PHY_BCR] = { 0x2805c, 0 },
3966 [GCC_PCIE0_AHB_ARES] = { 0x28058, 7 },
3967 [GCC_PCIE0_AUX_ARES] = { 0x28058, 6 },
3968 [GCC_PCIE0_AXI_M_ARES] = { 0x28058, 5 },
3969 [GCC_PCIE0_AXI_M_STICKY_ARES] = { 0x28058, 4 },
3970 [GCC_PCIE0_AXI_S_ARES] = { 0x28058, 3 },
3971 [GCC_PCIE0_AXI_S_STICKY_ARES] = { 0x28058, 2 },
3972 [GCC_PCIE0_CORE_STICKY_ARES] = { 0x28058, 1 },
3973 [GCC_PCIE0_PIPE_ARES] = { 0x28058, 0 },
3974 [GCC_PCIE1_AHB_ARES] = { 0x29058, 7 },
3975 [GCC_PCIE1_AUX_ARES] = { 0x29058, 6 },
3976 [GCC_PCIE1_AXI_M_ARES] = { 0x29058, 5 },
3977 [GCC_PCIE1_AXI_M_STICKY_ARES] = { 0x29058, 4 },
3978 [GCC_PCIE1_AXI_S_ARES] = { 0x29058, 3 },
3979 [GCC_PCIE1_AXI_S_STICKY_ARES] = { 0x29058, 2 },
3980 [GCC_PCIE1_CORE_STICKY_ARES] = { 0x29058, 1 },
3981 [GCC_PCIE1_PIPE_ARES] = { 0x29058, 0 },
3982 [GCC_PCIE2_AHB_ARES] = { 0x2a058, 7 },
3983 [GCC_PCIE2_AUX_ARES] = { 0x2a058, 6 },
3984 [GCC_PCIE2_AXI_M_ARES] = { 0x2a058, 5 },
3985 [GCC_PCIE2_AXI_M_STICKY_ARES] = { 0x2a058, 4 },
3986 [GCC_PCIE2_AXI_S_ARES] = { 0x2a058, 3 },
3987 [GCC_PCIE2_AXI_S_STICKY_ARES] = { 0x2a058, 2 },
3988 [GCC_PCIE2_CORE_STICKY_ARES] = { 0x2a058, 1 },
3989 [GCC_PCIE2_PIPE_ARES] = { 0x2a058, 0 },
3990 [GCC_PCIE3_AHB_ARES] = { 0x2b058, 7 },
3991 [GCC_PCIE3_AUX_ARES] = { 0x2b058, 6 },
3992 [GCC_PCIE3_AXI_M_ARES] = { 0x2b058, 5 },
3993 [GCC_PCIE3_AXI_M_STICKY_ARES] = { 0x2b058, 4 },
3994 [GCC_PCIE3_AXI_S_ARES] = { 0x2b058, 3 },
3995 [GCC_PCIE3_AXI_S_STICKY_ARES] = { 0x2b058, 2 },
3996 [GCC_PCIE3_CORE_STICKY_ARES] = { 0x2b058, 1 },
3997 [GCC_PCIE3_PIPE_ARES] = { 0x2b058, 0 },
3998 [GCC_PCIE0_BCR] = { 0x28000, 0 },
3999 [GCC_PCIE0_LINK_DOWN_BCR] = { 0x28054, 0 },
4000 [GCC_PCIE0_PHY_BCR] = { 0x28060, 0 },
4001 [GCC_PCIE1_BCR] = { 0x29000, 0 },
4002 [GCC_PCIE1_LINK_DOWN_BCR] = { 0x29054, 0 },
4003 [GCC_PCIE1_PHY_BCR] = { 0x29060, 0 },
4004 [GCC_PCIE1PHY_PHY_BCR] = { 0x2905c, 0 },
4005 [GCC_PCIE2_BCR] = { 0x2a000, 0 },
4006 [GCC_PCIE2_LINK_DOWN_BCR] = { 0x2a054, 0 },
4007 [GCC_PCIE2_PHY_BCR] = { 0x2a060, 0 },
4008 [GCC_PCIE2PHY_PHY_BCR] = { 0x2a05c, 0 },
4009 [GCC_PCIE3_BCR] = { 0x2b000, 0 },
4010 [GCC_PCIE3_LINK_DOWN_BCR] = { 0x2b054, 0 },
4011 [GCC_PCIE3PHY_PHY_BCR] = { 0x2b05c, 0 },
4012 [GCC_PCIE3_PHY_BCR] = { 0x2b060, 0 },
4013 [GCC_PCNOC_BCR] = { 0x31000, 0 },
4014 [GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x31030, 0 },
4015 [GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x31038, 0 },
4016 [GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x31040, 0 },
4017 [GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x31048, 0 },
4018 [GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x31050, 0 },
4019 [GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x31058, 0 },
4020 [GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x31060, 0 },
4021 [GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x31068, 0 },
4022 [GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x31070, 0 },
4023 [GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x31078, 0 },
4024 [GCC_PCNOC_TBU_BCR] = { 0x12034, 0 },
4025 [GCC_PRNG_BCR] = { 0x13020, 0 },
4026 [GCC_Q6SS_DBG_ARES] = { 0x2506c, 4 },
4027 [GCC_Q6_AHB_ARES] = { 0x2506c, 3 },
4028 [GCC_Q6_AHB_S_ARES] = { 0x2506c, 2 },
4029 [GCC_Q6_AXIM2_ARES] = { 0x2506c, 1 },
4030 [GCC_Q6_AXIM_ARES] = { 0x2506c, 0 },
4031 [GCC_QDSS_BCR] = { 0x2d000, 0 },
4032 [GCC_QPIC_BCR] = { 0x32000, 0 },
4033 [GCC_QPIC_AHB_ARES] = { 0x3201c, 1 },
4034 [GCC_QPIC_ARES] = { 0x3201c, 0 },
4035 [GCC_QUSB2_0_PHY_BCR] = { 0x2c068, 0 },
4036 [GCC_RBCPR_BCR] = { 0x39000, 0 },
4037 [GCC_RBCPR_MX_BCR] = { 0x39014, 0 },
4038 [GCC_SDCC_BCR] = { 0x33000, 0 },
4039 [GCC_SEC_CTRL_BCR] = { 0x1a000, 0 },
4040 [GCC_SMMU_CFG_BCR] = { 0x1202c, 0 },
4041 [GCC_SNOC_BCR] = { 0x2e000, 0 },
4042 [GCC_SPDM_BCR] = { 0x36000, 0 },
4043 [GCC_TCSR_BCR] = { 0x3d000, 0 },
4044 [GCC_TLMM_BCR] = { 0x3e000, 0 },
4045 [GCC_TME_BCR] = { 0x10000, 0 },
4046 [GCC_UNIPHY0_BCR] = { 0x17044, 0 },
4047 [GCC_UNIPHY0_SYS_RESET] = { 0x17050, 0 },
4048 [GCC_UNIPHY0_AHB_RESET] = { 0x17050, 1 },
4049 [GCC_UNIPHY0_XPCS_RESET] = { 0x17050, 2 },
4050 [GCC_UNIPHY1_SYS_RESET] = { 0x17060, 0 },
4051 [GCC_UNIPHY1_AHB_RESET] = { 0x17060, 1 },
4052 [GCC_UNIPHY1_XPCS_RESET] = { 0x17060, 2 },
4053 [GCC_UNIPHY2_SYS_RESET] = { 0x17070, 0 },
4054 [GCC_UNIPHY2_AHB_RESET] = { 0x17070, 1 },
4055 [GCC_UNIPHY2_XPCS_RESET] = { 0x17070, 2 },
4056 [GCC_UNIPHY1_BCR] = { 0x17054, 0 },
4057 [GCC_UNIPHY2_BCR] = { 0x17064, 0 },
4058 [GCC_USB0_PHY_BCR] = { 0x2c06c, 0 },
4059 [GCC_USB3PHY_0_PHY_BCR] = { 0x2c070, 0 },
4060 [GCC_USB_BCR] = { 0x2c000, 0 },
4061 [GCC_USB_MISC_RESET] = { 0x2c064, 0 },
4062 [GCC_WCSSAON_RESET] = { 0x25074, 0 },
4063 [GCC_WCSS_ACMT_ARES] = { 0x25070, 5 },
4064 [GCC_WCSS_AHB_S_ARES] = { 0x25070, 4 },
4065 [GCC_WCSS_AXI_M_ARES] = { 0x25070, 3 },
4066 [GCC_WCSS_BCR] = { 0x18004, 0 },
4067 [GCC_WCSS_DBG_ARES] = { 0x25070, 2 },
4068 [GCC_WCSS_DBG_BDG_ARES] = { 0x25070, 1 },
4069 [GCC_WCSS_ECAHB_ARES] = { 0x25070, 0 },
4070 [GCC_WCSS_Q6_BCR] = { 0x18000, 0 },
4071 [GCC_WCSS_Q6_TBU_BCR] = { 0x12054, 0 },
4110 .max_register = 0x7fffc,