Lines Matching full:pll
13 #include "clk-alpha-pll.h"
338 /* TRION PLL specific settings and offsets */
342 /* LUCID PLL specific settings and offsets */
345 /* LUCID 5LPE PLL specific settings and offsets */
351 /* LUCID EVO PLL specific settings and offsets */
358 /* PONGO ELU PLL specific setting and offsets */
364 /* ZONDA PLL specific */
381 static int wait_for_pll(struct clk_alpha_pll *pll, u32 mask, bool inverse, in wait_for_pll() argument
387 const char *name = clk_hw_get_name(&pll->clkr.hw); in wait_for_pll()
389 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in wait_for_pll()
395 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in wait_for_pll()
410 #define wait_for_pll_enable_active(pll) \ argument
411 wait_for_pll(pll, PLL_ACTIVE_FLAG, 0, "enable")
413 #define wait_for_pll_enable_lock(pll) \ argument
414 wait_for_pll(pll, PLL_LOCK_DET, 0, "enable")
416 #define wait_for_zonda_pll_freq_lock(pll) \ argument
417 wait_for_pll(pll, ZONDA_PLL_FREQ_LOCK_DET, 0, "freq enable")
419 #define wait_for_pll_disable(pll) \ argument
420 wait_for_pll(pll, PLL_ACTIVE_FLAG, 1, "disable")
422 #define wait_for_pll_offline(pll) \ argument
423 wait_for_pll(pll, PLL_OFFLINE_ACK, 0, "offline")
425 #define wait_for_pll_update(pll) \ argument
426 wait_for_pll(pll, PLL_UPDATE, 1, "update")
428 #define wait_for_pll_update_ack_set(pll) \ argument
429 wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 0, "update_ack_set")
431 #define wait_for_pll_update_ack_clear(pll) \ argument
432 wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 1, "update_ack_clear")
441 void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, in clk_alpha_pll_configure() argument
446 regmap_write(regmap, PLL_L_VAL(pll), config->l); in clk_alpha_pll_configure()
447 regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha); in clk_alpha_pll_configure()
448 regmap_write(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); in clk_alpha_pll_configure()
450 if (pll_has_64bit_config(pll)) in clk_alpha_pll_configure()
451 regmap_write(regmap, PLL_CONFIG_CTL_U(pll), in clk_alpha_pll_configure()
454 if (pll_alpha_width(pll) > 32) in clk_alpha_pll_configure()
455 regmap_write(regmap, PLL_ALPHA_VAL_U(pll), config->alpha_hi); in clk_alpha_pll_configure()
477 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val); in clk_alpha_pll_configure()
480 regmap_update_bits(regmap, PLL_TEST_CTL(pll), in clk_alpha_pll_configure()
484 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), in clk_alpha_pll_configure()
488 regmap_update_bits(regmap, PLL_TEST_CTL_U(pll), in clk_alpha_pll_configure()
492 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), in clk_alpha_pll_configure()
495 if (pll->flags & SUPPORTS_FSM_MODE) in clk_alpha_pll_configure()
496 qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0); in clk_alpha_pll_configure()
503 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_alpha_pll_hwfsm_enable() local
506 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in clk_alpha_pll_hwfsm_enable()
512 if (pll->flags & SUPPORTS_OFFLINE_REQ) in clk_alpha_pll_hwfsm_enable()
515 ret = regmap_write(pll->clkr.regmap, PLL_MODE(pll), val); in clk_alpha_pll_hwfsm_enable()
522 return wait_for_pll_enable_active(pll); in clk_alpha_pll_hwfsm_enable()
528 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_alpha_pll_hwfsm_disable() local
531 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in clk_alpha_pll_hwfsm_disable()
535 if (pll->flags & SUPPORTS_OFFLINE_REQ) { in clk_alpha_pll_hwfsm_disable()
536 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), in clk_alpha_pll_hwfsm_disable()
541 ret = wait_for_pll_offline(pll); in clk_alpha_pll_hwfsm_disable()
547 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), in clk_alpha_pll_hwfsm_disable()
552 wait_for_pll_disable(pll); in clk_alpha_pll_hwfsm_disable()
558 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in pll_is_enabled() local
561 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in pll_is_enabled()
581 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_alpha_pll_enable() local
585 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in clk_alpha_pll_enable()
594 return wait_for_pll_enable_active(pll); in clk_alpha_pll_enable()
601 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), in clk_alpha_pll_enable()
613 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), in clk_alpha_pll_enable()
618 ret = wait_for_pll_enable_lock(pll); in clk_alpha_pll_enable()
622 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), in clk_alpha_pll_enable()
633 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_alpha_pll_disable() local
636 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in clk_alpha_pll_disable()
647 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0); in clk_alpha_pll_disable()
654 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0); in clk_alpha_pll_disable()
692 alpha_pll_find_vco(const struct clk_alpha_pll *pll, unsigned long rate) in alpha_pll_find_vco() argument
694 const struct pll_vco *v = pll->vco_table; in alpha_pll_find_vco()
695 const struct pll_vco *end = v + pll->num_vco; in alpha_pll_find_vco()
709 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_alpha_pll_recalc_rate() local
710 u32 alpha_width = pll_alpha_width(pll); in clk_alpha_pll_recalc_rate()
712 if (regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l)) in clk_alpha_pll_recalc_rate()
715 if (regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl)) in clk_alpha_pll_recalc_rate()
719 if (regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &low)) in clk_alpha_pll_recalc_rate()
722 if (regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), in clk_alpha_pll_recalc_rate()
738 static int __clk_alpha_pll_update_latch(struct clk_alpha_pll *pll) in __clk_alpha_pll_update_latch() argument
743 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &mode); in __clk_alpha_pll_update_latch()
745 /* Latch the input to the PLL */ in __clk_alpha_pll_update_latch()
746 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, in __clk_alpha_pll_update_latch()
753 * PLL will latch the new L, Alpha and freq control word. in __clk_alpha_pll_update_latch()
754 * PLL will respond by raising PLL_ACK_LATCH output when new programming in __clk_alpha_pll_update_latch()
755 * has been latched in and PLL is being updated. When in __clk_alpha_pll_update_latch()
757 * automatically by hardware when PLL_ACK_LATCH is asserted by PLL. in __clk_alpha_pll_update_latch()
760 ret = wait_for_pll_update_ack_set(pll); in __clk_alpha_pll_update_latch()
764 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, 0); in __clk_alpha_pll_update_latch()
766 ret = wait_for_pll_update(pll); in __clk_alpha_pll_update_latch()
771 ret = wait_for_pll_update_ack_clear(pll); in __clk_alpha_pll_update_latch()
775 /* Wait for PLL output to stabilize */ in __clk_alpha_pll_update_latch()
781 static int clk_alpha_pll_update_latch(struct clk_alpha_pll *pll, in clk_alpha_pll_update_latch() argument
784 if (!is_enabled(&pll->clkr.hw) || in clk_alpha_pll_update_latch()
785 !(pll->flags & SUPPORTS_DYNAMIC_UPDATE)) in clk_alpha_pll_update_latch()
788 return __clk_alpha_pll_update_latch(pll); in clk_alpha_pll_update_latch()
795 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in __clk_alpha_pll_set_rate() local
797 u32 l, alpha_width = pll_alpha_width(pll); in __clk_alpha_pll_set_rate()
801 vco = alpha_pll_find_vco(pll, rate); in __clk_alpha_pll_set_rate()
802 if (pll->vco_table && !vco) { in __clk_alpha_pll_set_rate()
803 pr_err("%s: alpha pll not in a valid vco range\n", in __clk_alpha_pll_set_rate()
808 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); in __clk_alpha_pll_set_rate()
814 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), a >> 32); in __clk_alpha_pll_set_rate()
816 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); in __clk_alpha_pll_set_rate()
819 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), in __clk_alpha_pll_set_rate()
824 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), in __clk_alpha_pll_set_rate()
827 return clk_alpha_pll_update_latch(pll, is_enabled); in __clk_alpha_pll_set_rate()
847 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_alpha_pll_round_rate() local
848 u32 l, alpha_width = pll_alpha_width(pll); in clk_alpha_pll_round_rate()
853 if (!pll->vco_table || alpha_pll_find_vco(pll, rate)) in clk_alpha_pll_round_rate()
856 min_freq = pll->vco_table[0].min_freq; in clk_alpha_pll_round_rate()
857 max_freq = pll->vco_table[pll->num_vco - 1].max_freq; in clk_alpha_pll_round_rate()
862 void clk_huayra_2290_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, in clk_huayra_2290_pll_configure() argument
867 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); in clk_huayra_2290_pll_configure()
868 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); in clk_huayra_2290_pll_configure()
869 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); in clk_huayra_2290_pll_configure()
870 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); in clk_huayra_2290_pll_configure()
871 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); in clk_huayra_2290_pll_configure()
872 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val); in clk_huayra_2290_pll_configure()
873 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); in clk_huayra_2290_pll_configure()
874 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); in clk_huayra_2290_pll_configure()
875 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); in clk_huayra_2290_pll_configure()
878 regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, PLL_BYPASSNL); in clk_huayra_2290_pll_configure()
879 regmap_read(regmap, PLL_MODE(pll), &val); in clk_huayra_2290_pll_configure()
884 /* Take PLL out from reset state */ in clk_huayra_2290_pll_configure()
885 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in clk_huayra_2290_pll_configure()
886 regmap_read(regmap, PLL_MODE(pll), &val); in clk_huayra_2290_pll_configure()
891 /* Enable PLL output */ in clk_huayra_2290_pll_configure()
892 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); in clk_huayra_2290_pll_configure()
947 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_huayra_recalc_rate() local
950 if (regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l)) in alpha_pll_huayra_recalc_rate()
953 if (regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl)) in alpha_pll_huayra_recalc_rate()
957 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &alpha); in alpha_pll_huayra_recalc_rate()
1003 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_huayra_set_rate() local
1008 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); in alpha_pll_huayra_set_rate()
1011 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &cur_alpha); in alpha_pll_huayra_set_rate()
1014 * Huayra PLL supports PLL dynamic programming. User can change L_VAL, in alpha_pll_huayra_set_rate()
1024 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); in alpha_pll_huayra_set_rate()
1027 return wait_for_pll_enable_lock(pll); in alpha_pll_huayra_set_rate()
1030 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); in alpha_pll_huayra_set_rate()
1031 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); in alpha_pll_huayra_set_rate()
1034 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), in alpha_pll_huayra_set_rate()
1037 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), in alpha_pll_huayra_set_rate()
1051 static int trion_pll_is_enabled(struct clk_alpha_pll *pll, in trion_pll_is_enabled() argument
1057 ret = regmap_read(regmap, PLL_MODE(pll), &mode_val); in trion_pll_is_enabled()
1058 ret |= regmap_read(regmap, PLL_OPMODE(pll), &opmode_val); in trion_pll_is_enabled()
1067 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_trion_pll_is_enabled() local
1069 return trion_pll_is_enabled(pll, pll->clkr.regmap); in clk_trion_pll_is_enabled()
1074 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_trion_pll_enable() local
1075 struct regmap *regmap = pll->clkr.regmap; in clk_trion_pll_enable()
1079 ret = regmap_read(regmap, PLL_MODE(pll), &val); in clk_trion_pll_enable()
1088 return wait_for_pll_enable_active(pll); in clk_trion_pll_enable()
1092 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); in clk_trion_pll_enable()
1094 ret = wait_for_pll_enable_lock(pll); in clk_trion_pll_enable()
1098 /* Enable the PLL outputs */ in clk_trion_pll_enable()
1099 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), in clk_trion_pll_enable()
1104 /* Enable the global PLL outputs */ in clk_trion_pll_enable()
1105 return regmap_update_bits(regmap, PLL_MODE(pll), in clk_trion_pll_enable()
1111 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_trion_pll_disable() local
1112 struct regmap *regmap = pll->clkr.regmap; in clk_trion_pll_disable()
1116 ret = regmap_read(regmap, PLL_MODE(pll), &val); in clk_trion_pll_disable()
1126 /* Disable the global PLL output */ in clk_trion_pll_disable()
1127 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in clk_trion_pll_disable()
1131 /* Disable the PLL outputs */ in clk_trion_pll_disable()
1132 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), in clk_trion_pll_disable()
1137 /* Place the PLL mode in STANDBY */ in clk_trion_pll_disable()
1138 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in clk_trion_pll_disable()
1139 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in clk_trion_pll_disable()
1145 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_trion_pll_recalc_rate() local
1146 u32 l, frac, alpha_width = pll_alpha_width(pll); in clk_trion_pll_recalc_rate()
1148 if (regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l)) in clk_trion_pll_recalc_rate()
1151 if (regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &frac)) in clk_trion_pll_recalc_rate()
1207 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_alpha_pll_postdiv_recalc_rate() local
1210 if (regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl)) in clk_alpha_pll_postdiv_recalc_rate()
1214 ctl &= PLL_POST_DIV_MASK(pll); in clk_alpha_pll_postdiv_recalc_rate()
1239 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_alpha_pll_postdiv_round_rate() local
1242 if (pll->width == 2) in clk_alpha_pll_postdiv_round_rate()
1248 pll->width, CLK_DIVIDER_POWER_OF_TWO); in clk_alpha_pll_postdiv_round_rate()
1255 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_alpha_pll_postdiv_round_ro_rate() local
1258 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); in clk_alpha_pll_postdiv_round_ro_rate()
1261 ctl &= BIT(pll->width) - 1; in clk_alpha_pll_postdiv_round_ro_rate()
1273 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_alpha_pll_postdiv_set_rate() local
1279 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), in clk_alpha_pll_postdiv_set_rate()
1280 PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT, in clk_alpha_pll_postdiv_set_rate()
1297 void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, in clk_fabia_pll_configure() argument
1302 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); in clk_fabia_pll_configure()
1303 clk_alpha_pll_write_config(regmap, PLL_FRAC(pll), config->alpha); in clk_fabia_pll_configure()
1304 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), in clk_fabia_pll_configure()
1306 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), in clk_fabia_pll_configure()
1308 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), in clk_fabia_pll_configure()
1310 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), in clk_fabia_pll_configure()
1312 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), in clk_fabia_pll_configure()
1314 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), in clk_fabia_pll_configure()
1320 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val); in clk_fabia_pll_configure()
1323 if (pll->flags & SUPPORTS_FSM_LEGACY_MODE) in clk_fabia_pll_configure()
1324 regmap_update_bits(regmap, PLL_MODE(pll), PLL_FSM_LEGACY_MODE, in clk_fabia_pll_configure()
1327 regmap_update_bits(regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS, in clk_fabia_pll_configure()
1330 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in clk_fabia_pll_configure()
1337 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_fabia_enable() local
1339 struct regmap *regmap = pll->clkr.regmap; in alpha_pll_fabia_enable()
1341 ret = regmap_read(regmap, PLL_MODE(pll), &val); in alpha_pll_fabia_enable()
1350 return wait_for_pll_enable_active(pll); in alpha_pll_fabia_enable()
1353 ret = regmap_read(regmap, PLL_OPMODE(pll), &opmode_val); in alpha_pll_fabia_enable()
1357 /* Skip If PLL is already running */ in alpha_pll_fabia_enable()
1361 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in alpha_pll_fabia_enable()
1365 ret = regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in alpha_pll_fabia_enable()
1369 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, in alpha_pll_fabia_enable()
1374 ret = regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); in alpha_pll_fabia_enable()
1378 ret = wait_for_pll_enable_lock(pll); in alpha_pll_fabia_enable()
1382 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), in alpha_pll_fabia_enable()
1387 return regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, in alpha_pll_fabia_enable()
1394 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_fabia_disable() local
1396 struct regmap *regmap = pll->clkr.regmap; in alpha_pll_fabia_disable()
1398 ret = regmap_read(regmap, PLL_MODE(pll), &val); in alpha_pll_fabia_disable()
1408 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in alpha_pll_fabia_disable()
1413 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0); in alpha_pll_fabia_disable()
1417 /* Place the PLL in STANDBY */ in alpha_pll_fabia_disable()
1418 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in alpha_pll_fabia_disable()
1424 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_fabia_recalc_rate() local
1425 u32 l, frac, alpha_width = pll_alpha_width(pll); in alpha_pll_fabia_recalc_rate()
1427 if (regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l)) in alpha_pll_fabia_recalc_rate()
1430 if (regmap_read(pll->clkr.regmap, PLL_FRAC(pll), &frac)) in alpha_pll_fabia_recalc_rate()
1457 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_fabia_set_rate() local
1458 u32 l, alpha_width = pll_alpha_width(pll); in alpha_pll_fabia_set_rate()
1469 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); in alpha_pll_fabia_set_rate()
1470 regmap_write(pll->clkr.regmap, PLL_FRAC(pll), a); in alpha_pll_fabia_set_rate()
1472 return __clk_alpha_pll_update_latch(pll); in alpha_pll_fabia_set_rate()
1477 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_fabia_prepare() local
1481 u32 cal_l, val, alpha_width = pll_alpha_width(pll); in alpha_pll_fabia_prepare()
1486 /* Check if calibration needs to be done i.e. PLL is in reset */ in alpha_pll_fabia_prepare()
1487 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in alpha_pll_fabia_prepare()
1495 vco = alpha_pll_find_vco(pll, clk_hw_get_rate(hw)); in alpha_pll_fabia_prepare()
1497 pr_err("%s: alpha pll not in a valid vco range\n", name); in alpha_pll_fabia_prepare()
1501 cal_freq = DIV_ROUND_CLOSEST((pll->vco_table[0].min_freq + in alpha_pll_fabia_prepare()
1502 pll->vco_table[0].max_freq) * 54, 100); in alpha_pll_fabia_prepare()
1515 /* Setup PLL for calibration frequency */ in alpha_pll_fabia_prepare()
1516 regmap_write(pll->clkr.regmap, PLL_CAL_L_VAL(pll), cal_l); in alpha_pll_fabia_prepare()
1518 /* Bringup the PLL at calibration frequency */ in alpha_pll_fabia_prepare()
1521 pr_err("%s: alpha pll calibration failed\n", name); in alpha_pll_fabia_prepare()
1553 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_alpha_pll_postdiv_fabia_recalc_rate() local
1557 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val); in clk_alpha_pll_postdiv_fabia_recalc_rate()
1561 val >>= pll->post_div_shift; in clk_alpha_pll_postdiv_fabia_recalc_rate()
1562 val &= BIT(pll->width) - 1; in clk_alpha_pll_postdiv_fabia_recalc_rate()
1564 for (i = 0; i < pll->num_post_div; i++) { in clk_alpha_pll_postdiv_fabia_recalc_rate()
1565 if (pll->post_div_table[i].val == val) { in clk_alpha_pll_postdiv_fabia_recalc_rate()
1566 div = pll->post_div_table[i].div; in clk_alpha_pll_postdiv_fabia_recalc_rate()
1577 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_trion_pll_postdiv_recalc_rate() local
1578 struct regmap *regmap = pll->clkr.regmap; in clk_trion_pll_postdiv_recalc_rate()
1581 if (regmap_read(regmap, PLL_USER_CTL(pll), &val)) in clk_trion_pll_postdiv_recalc_rate()
1584 val >>= pll->post_div_shift; in clk_trion_pll_postdiv_recalc_rate()
1585 val &= PLL_POST_DIV_MASK(pll); in clk_trion_pll_postdiv_recalc_rate()
1587 for (i = 0; i < pll->num_post_div; i++) { in clk_trion_pll_postdiv_recalc_rate()
1588 if (pll->post_div_table[i].val == val) { in clk_trion_pll_postdiv_recalc_rate()
1589 div = pll->post_div_table[i].div; in clk_trion_pll_postdiv_recalc_rate()
1601 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_trion_pll_postdiv_round_rate() local
1603 return divider_round_rate(hw, rate, prate, pll->post_div_table, in clk_trion_pll_postdiv_round_rate()
1604 pll->width, CLK_DIVIDER_ROUND_CLOSEST); in clk_trion_pll_postdiv_round_rate()
1611 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_trion_pll_postdiv_set_rate() local
1612 struct regmap *regmap = pll->clkr.regmap; in clk_trion_pll_postdiv_set_rate()
1616 for (i = 0; i < pll->num_post_div; i++) { in clk_trion_pll_postdiv_set_rate()
1617 if (pll->post_div_table[i].div == div) { in clk_trion_pll_postdiv_set_rate()
1618 val = pll->post_div_table[i].val; in clk_trion_pll_postdiv_set_rate()
1623 return regmap_update_bits(regmap, PLL_USER_CTL(pll), in clk_trion_pll_postdiv_set_rate()
1624 PLL_POST_DIV_MASK(pll) << pll->post_div_shift, in clk_trion_pll_postdiv_set_rate()
1625 val << pll->post_div_shift); in clk_trion_pll_postdiv_set_rate()
1638 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_alpha_pll_postdiv_fabia_round_rate() local
1640 return divider_round_rate(hw, rate, prate, pll->post_div_table, in clk_alpha_pll_postdiv_fabia_round_rate()
1641 pll->width, CLK_DIVIDER_ROUND_CLOSEST); in clk_alpha_pll_postdiv_fabia_round_rate()
1647 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_alpha_pll_postdiv_fabia_set_rate() local
1651 * If the PLL is in FSM mode, then treat set_rate callback as a in clk_alpha_pll_postdiv_fabia_set_rate()
1654 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in clk_alpha_pll_postdiv_fabia_set_rate()
1662 for (i = 0; i < pll->num_post_div; i++) { in clk_alpha_pll_postdiv_fabia_set_rate()
1663 if (pll->post_div_table[i].div == div) { in clk_alpha_pll_postdiv_fabia_set_rate()
1664 val = pll->post_div_table[i].val; in clk_alpha_pll_postdiv_fabia_set_rate()
1669 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), in clk_alpha_pll_postdiv_fabia_set_rate()
1670 (BIT(pll->width) - 1) << pll->post_div_shift, in clk_alpha_pll_postdiv_fabia_set_rate()
1671 val << pll->post_div_shift); in clk_alpha_pll_postdiv_fabia_set_rate()
1682 * clk_trion_pll_configure - configure the trion pll
1684 * @pll: clk alpha pll
1686 * @config: configuration to apply for pll
1688 void clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, in clk_trion_pll_configure() argument
1692 * If the bootloader left the PLL enabled it's likely that there are in clk_trion_pll_configure()
1693 * RCGs that will lock up if we disable the PLL below. in clk_trion_pll_configure()
1695 if (trion_pll_is_enabled(pll, regmap)) { in clk_trion_pll_configure()
1696 pr_debug("Trion PLL is already enabled, skipping configuration\n"); in clk_trion_pll_configure()
1700 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); in clk_trion_pll_configure()
1701 regmap_write(regmap, PLL_CAL_L_VAL(pll), TRION_PLL_CAL_VAL); in clk_trion_pll_configure()
1702 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); in clk_trion_pll_configure()
1703 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), in clk_trion_pll_configure()
1705 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), in clk_trion_pll_configure()
1707 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), in clk_trion_pll_configure()
1709 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), in clk_trion_pll_configure()
1711 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), in clk_trion_pll_configure()
1713 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll), in clk_trion_pll_configure()
1715 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), in clk_trion_pll_configure()
1717 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), in clk_trion_pll_configure()
1719 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), in clk_trion_pll_configure()
1722 regmap_update_bits(regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS, in clk_trion_pll_configure()
1725 /* Disable PLL output */ in clk_trion_pll_configure()
1726 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in clk_trion_pll_configure()
1729 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in clk_trion_pll_configure()
1731 /* Place the PLL in STANDBY mode */ in clk_trion_pll_configure()
1732 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in clk_trion_pll_configure()
1737 * The TRION PLL requires a power-on self-calibration which happens when the
1738 * PLL comes out of reset. Calibrate in case it is not completed.
1742 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in __alpha_pll_trion_prepare() local
1747 regmap_read(pll->clkr.regmap, PLL_STATUS(pll), &val); in __alpha_pll_trion_prepare()
1772 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in __alpha_pll_trion_set_rate() local
1774 u32 val, l, alpha_width = pll_alpha_width(pll); in __alpha_pll_trion_set_rate()
1784 regmap_update_bits(pll->clkr.regmap, PLL_L_VAL(pll), LUCID_EVO_PLL_L_VAL_MASK, l); in __alpha_pll_trion_set_rate()
1785 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); in __alpha_pll_trion_set_rate()
1787 /* Latch the PLL input */ in __alpha_pll_trion_set_rate()
1788 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), latch_bit, latch_bit); in __alpha_pll_trion_set_rate()
1794 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in __alpha_pll_trion_set_rate()
1796 pr_err("Lucid PLL latch failed. Output may be unstable!\n"); in __alpha_pll_trion_set_rate()
1801 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), latch_bit, 0); in __alpha_pll_trion_set_rate()
1806 ret = wait_for_pll_enable_lock(pll); in __alpha_pll_trion_set_rate()
1811 /* Wait for PLL output to stabilize */ in __alpha_pll_trion_set_rate()
1851 void clk_agera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, in clk_agera_pll_configure() argument
1854 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); in clk_agera_pll_configure()
1855 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); in clk_agera_pll_configure()
1856 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), in clk_agera_pll_configure()
1858 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), in clk_agera_pll_configure()
1860 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), in clk_agera_pll_configure()
1862 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), in clk_agera_pll_configure()
1864 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), in clk_agera_pll_configure()
1872 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_alpha_pll_agera_set_rate() local
1873 u32 l, alpha_width = pll_alpha_width(pll); in clk_alpha_pll_agera_set_rate()
1884 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); in clk_alpha_pll_agera_set_rate()
1885 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); in clk_alpha_pll_agera_set_rate()
1888 return wait_for_pll_enable_lock(pll); in clk_alpha_pll_agera_set_rate()
1904 * clk_lucid_5lpe_pll_configure - configure the lucid 5lpe pll
1906 * @pll: clk alpha pll
1908 * @config: configuration to apply for pll
1910 void clk_lucid_5lpe_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, in clk_lucid_5lpe_pll_configure() argument
1914 * If the bootloader left the PLL enabled it's likely that there are in clk_lucid_5lpe_pll_configure()
1915 * RCGs that will lock up if we disable the PLL below. in clk_lucid_5lpe_pll_configure()
1917 if (trion_pll_is_enabled(pll, regmap)) { in clk_lucid_5lpe_pll_configure()
1918 pr_debug("Lucid 5LPE PLL is already enabled, skipping configuration\n"); in clk_lucid_5lpe_pll_configure()
1922 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); in clk_lucid_5lpe_pll_configure()
1923 regmap_write(regmap, PLL_CAL_L_VAL(pll), TRION_PLL_CAL_VAL); in clk_lucid_5lpe_pll_configure()
1924 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); in clk_lucid_5lpe_pll_configure()
1925 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), in clk_lucid_5lpe_pll_configure()
1927 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), in clk_lucid_5lpe_pll_configure()
1929 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), in clk_lucid_5lpe_pll_configure()
1931 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), in clk_lucid_5lpe_pll_configure()
1933 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), in clk_lucid_5lpe_pll_configure()
1935 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll), in clk_lucid_5lpe_pll_configure()
1937 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), in clk_lucid_5lpe_pll_configure()
1939 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), in clk_lucid_5lpe_pll_configure()
1941 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), in clk_lucid_5lpe_pll_configure()
1944 /* Disable PLL output */ in clk_lucid_5lpe_pll_configure()
1945 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in clk_lucid_5lpe_pll_configure()
1948 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in clk_lucid_5lpe_pll_configure()
1950 /* Place the PLL in STANDBY mode */ in clk_lucid_5lpe_pll_configure()
1951 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in clk_lucid_5lpe_pll_configure()
1957 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_lucid_5lpe_enable() local
1961 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val); in alpha_pll_lucid_5lpe_enable()
1970 return wait_for_pll_enable_lock(pll); in alpha_pll_lucid_5lpe_enable()
1973 /* Check if PLL is already enabled, return if enabled */ in alpha_pll_lucid_5lpe_enable()
1974 if (trion_pll_is_enabled(pll, pll->clkr.regmap)) in alpha_pll_lucid_5lpe_enable()
1977 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in alpha_pll_lucid_5lpe_enable()
1981 regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_RUN); in alpha_pll_lucid_5lpe_enable()
1983 ret = wait_for_pll_enable_lock(pll); in alpha_pll_lucid_5lpe_enable()
1987 /* Enable the PLL outputs */ in alpha_pll_lucid_5lpe_enable()
1988 ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, PLL_OUT_MASK); in alpha_pll_lucid_5lpe_enable()
1992 /* Enable the global PLL outputs */ in alpha_pll_lucid_5lpe_enable()
1993 return regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); in alpha_pll_lucid_5lpe_enable()
1998 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_lucid_5lpe_disable() local
2002 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val); in alpha_pll_lucid_5lpe_disable()
2012 /* Disable the global PLL output */ in alpha_pll_lucid_5lpe_disable()
2013 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in alpha_pll_lucid_5lpe_disable()
2017 /* Disable the PLL outputs */ in alpha_pll_lucid_5lpe_disable()
2018 ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0); in alpha_pll_lucid_5lpe_disable()
2022 /* Place the PLL mode in STANDBY */ in alpha_pll_lucid_5lpe_disable()
2023 regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_STANDBY); in alpha_pll_lucid_5lpe_disable()
2027 * The Lucid 5LPE PLL requires a power-on self-calibration which happens
2028 * when the PLL comes out of reset. Calibrate in case it is not completed.
2032 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_lucid_5lpe_prepare() local
2038 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in alpha_pll_lucid_5lpe_prepare()
2067 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in __clk_lucid_pll_postdiv_set_rate() local
2068 struct regmap *regmap = pll->clkr.regmap; in __clk_lucid_pll_postdiv_set_rate()
2073 * If the PLL is in FSM mode, then treat set_rate callback as a in __clk_lucid_pll_postdiv_set_rate()
2076 ret = regmap_read(regmap, PLL_USER_CTL(pll), &val); in __clk_lucid_pll_postdiv_set_rate()
2083 if (!pll->post_div_table) { in __clk_lucid_pll_postdiv_set_rate()
2084 pr_err("Missing the post_div_table for the %s PLL\n", in __clk_lucid_pll_postdiv_set_rate()
2085 clk_hw_get_name(&pll->clkr.hw)); in __clk_lucid_pll_postdiv_set_rate()
2090 for (i = 0; i < pll->num_post_div; i++) { in __clk_lucid_pll_postdiv_set_rate()
2091 if (pll->post_div_table[i].div == div) { in __clk_lucid_pll_postdiv_set_rate()
2092 val = pll->post_div_table[i].val; in __clk_lucid_pll_postdiv_set_rate()
2097 mask = GENMASK(pll->width + pll->post_div_shift - 1, pll->post_div_shift); in __clk_lucid_pll_postdiv_set_rate()
2098 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), in __clk_lucid_pll_postdiv_set_rate()
2099 mask, val << pll->post_div_shift); in __clk_lucid_pll_postdiv_set_rate()
2135 void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, in clk_zonda_pll_configure() argument
2138 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); in clk_zonda_pll_configure()
2139 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); in clk_zonda_pll_configure()
2140 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); in clk_zonda_pll_configure()
2141 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); in clk_zonda_pll_configure()
2142 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); in clk_zonda_pll_configure()
2143 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); in clk_zonda_pll_configure()
2144 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); in clk_zonda_pll_configure()
2145 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll), config->user_ctl_hi1_val); in clk_zonda_pll_configure()
2146 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); in clk_zonda_pll_configure()
2147 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); in clk_zonda_pll_configure()
2148 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val); in clk_zonda_pll_configure()
2150 regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, 0); in clk_zonda_pll_configure()
2152 /* Disable PLL output */ in clk_zonda_pll_configure()
2153 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in clk_zonda_pll_configure()
2156 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in clk_zonda_pll_configure()
2158 /* Place the PLL in STANDBY mode */ in clk_zonda_pll_configure()
2159 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in clk_zonda_pll_configure()
2165 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_zonda_pll_enable() local
2166 struct regmap *regmap = pll->clkr.regmap; in clk_zonda_pll_enable()
2170 regmap_read(regmap, PLL_MODE(pll), &val); in clk_zonda_pll_enable()
2177 return wait_for_pll_enable_active(pll); in clk_zonda_pll_enable()
2180 /* Get the PLL out of bypass mode */ in clk_zonda_pll_enable()
2181 regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, PLL_BYPASSNL); in clk_zonda_pll_enable()
2189 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in clk_zonda_pll_enable()
2192 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); in clk_zonda_pll_enable()
2194 regmap_read(regmap, PLL_TEST_CTL(pll), &val); in clk_zonda_pll_enable()
2198 ret = wait_for_zonda_pll_freq_lock(pll); in clk_zonda_pll_enable()
2200 ret = wait_for_pll_enable_lock(pll); in clk_zonda_pll_enable()
2204 /* Enable the PLL outputs */ in clk_zonda_pll_enable()
2205 regmap_update_bits(regmap, PLL_USER_CTL(pll), ZONDA_PLL_OUT_MASK, ZONDA_PLL_OUT_MASK); in clk_zonda_pll_enable()
2207 /* Enable the global PLL outputs */ in clk_zonda_pll_enable()
2208 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); in clk_zonda_pll_enable()
2215 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_zonda_pll_disable() local
2216 struct regmap *regmap = pll->clkr.regmap; in clk_zonda_pll_disable()
2219 regmap_read(regmap, PLL_MODE(pll), &val); in clk_zonda_pll_disable()
2227 /* Disable the global PLL output */ in clk_zonda_pll_disable()
2228 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in clk_zonda_pll_disable()
2230 /* Disable the PLL outputs */ in clk_zonda_pll_disable()
2231 regmap_update_bits(regmap, PLL_USER_CTL(pll), ZONDA_PLL_OUT_MASK, 0); in clk_zonda_pll_disable()
2233 /* Put the PLL in bypass and reset */ in clk_zonda_pll_disable()
2234 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N | PLL_BYPASSNL, 0); in clk_zonda_pll_disable()
2236 /* Place the PLL mode in OFF state */ in clk_zonda_pll_disable()
2237 regmap_write(regmap, PLL_OPMODE(pll), 0x0); in clk_zonda_pll_disable()
2253 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_zonda_pll_set_rate() local
2256 u32 l, alpha_width = pll_alpha_width(pll); in clk_zonda_pll_set_rate()
2269 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); in clk_zonda_pll_set_rate()
2270 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); in clk_zonda_pll_set_rate()
2279 regmap_read(pll->clkr.regmap, PLL_TEST_CTL(pll), &test_ctl_val); in clk_zonda_pll_set_rate()
2283 ret = wait_for_zonda_pll_freq_lock(pll); in clk_zonda_pll_set_rate()
2285 ret = wait_for_pll_enable_lock(pll); in clk_zonda_pll_set_rate()
2289 /* Wait for PLL output to stabilize */ in clk_zonda_pll_set_rate()
2304 void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, in clk_lucid_evo_pll_configure() argument
2310 * If the bootloader left the PLL enabled it's likely that there are in clk_lucid_evo_pll_configure()
2311 * RCGs that will lock up if we disable the PLL below. in clk_lucid_evo_pll_configure()
2313 if (trion_pll_is_enabled(pll, regmap)) { in clk_lucid_evo_pll_configure()
2314 pr_debug("Lucid Evo PLL is already enabled, skipping configuration\n"); in clk_lucid_evo_pll_configure()
2319 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), lval); in clk_lucid_evo_pll_configure()
2320 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); in clk_lucid_evo_pll_configure()
2321 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); in clk_lucid_evo_pll_configure()
2322 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); in clk_lucid_evo_pll_configure()
2323 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); in clk_lucid_evo_pll_configure()
2324 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); in clk_lucid_evo_pll_configure()
2325 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); in clk_lucid_evo_pll_configure()
2326 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); in clk_lucid_evo_pll_configure()
2327 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); in clk_lucid_evo_pll_configure()
2328 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val); in clk_lucid_evo_pll_configure()
2329 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U2(pll), config->test_ctl_hi2_val); in clk_lucid_evo_pll_configure()
2331 /* Disable PLL output */ in clk_lucid_evo_pll_configure()
2332 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in clk_lucid_evo_pll_configure()
2335 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in clk_lucid_evo_pll_configure()
2336 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in clk_lucid_evo_pll_configure()
2340 void clk_lucid_ole_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, in clk_lucid_ole_pll_configure() argument
2347 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), lval); in clk_lucid_ole_pll_configure()
2348 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); in clk_lucid_ole_pll_configure()
2349 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); in clk_lucid_ole_pll_configure()
2350 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); in clk_lucid_ole_pll_configure()
2351 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); in clk_lucid_ole_pll_configure()
2352 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); in clk_lucid_ole_pll_configure()
2353 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); in clk_lucid_ole_pll_configure()
2354 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); in clk_lucid_ole_pll_configure()
2355 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); in clk_lucid_ole_pll_configure()
2356 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val); in clk_lucid_ole_pll_configure()
2357 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U2(pll), config->test_ctl_hi2_val); in clk_lucid_ole_pll_configure()
2359 /* Disable PLL output */ in clk_lucid_ole_pll_configure()
2360 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in clk_lucid_ole_pll_configure()
2363 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in clk_lucid_ole_pll_configure()
2364 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in clk_lucid_ole_pll_configure()
2370 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_lucid_evo_enable() local
2371 struct regmap *regmap = pll->clkr.regmap; in alpha_pll_lucid_evo_enable()
2375 ret = regmap_read(regmap, PLL_USER_CTL(pll), &val); in alpha_pll_lucid_evo_enable()
2384 return wait_for_pll_enable_lock(pll); in alpha_pll_lucid_evo_enable()
2387 /* Check if PLL is already enabled */ in alpha_pll_lucid_evo_enable()
2388 if (trion_pll_is_enabled(pll, regmap)) in alpha_pll_lucid_evo_enable()
2391 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in alpha_pll_lucid_evo_enable()
2396 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); in alpha_pll_lucid_evo_enable()
2398 ret = wait_for_pll_enable_lock(pll); in alpha_pll_lucid_evo_enable()
2402 /* Enable the PLL outputs */ in alpha_pll_lucid_evo_enable()
2403 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, PLL_OUT_MASK); in alpha_pll_lucid_evo_enable()
2407 /* Enable the global PLL outputs */ in alpha_pll_lucid_evo_enable()
2408 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); in alpha_pll_lucid_evo_enable()
2419 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in _alpha_pll_lucid_evo_disable() local
2420 struct regmap *regmap = pll->clkr.regmap; in _alpha_pll_lucid_evo_disable()
2424 ret = regmap_read(regmap, PLL_USER_CTL(pll), &val); in _alpha_pll_lucid_evo_disable()
2434 /* Disable the global PLL output */ in _alpha_pll_lucid_evo_disable()
2435 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in _alpha_pll_lucid_evo_disable()
2439 /* Disable the PLL outputs */ in _alpha_pll_lucid_evo_disable()
2440 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0); in _alpha_pll_lucid_evo_disable()
2444 /* Place the PLL mode in STANDBY */ in _alpha_pll_lucid_evo_disable()
2445 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in _alpha_pll_lucid_evo_disable()
2448 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, 0); in _alpha_pll_lucid_evo_disable()
2453 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in _alpha_pll_lucid_evo_prepare() local
2459 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in _alpha_pll_lucid_evo_prepare()
2499 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_lucid_evo_recalc_rate() local
2500 struct regmap *regmap = pll->clkr.regmap; in alpha_pll_lucid_evo_recalc_rate()
2503 if (regmap_read(regmap, PLL_L_VAL(pll), &l)) in alpha_pll_lucid_evo_recalc_rate()
2507 if (regmap_read(regmap, PLL_ALPHA_VAL(pll), &frac)) in alpha_pll_lucid_evo_recalc_rate()
2510 return alpha_pll_calc_rate(parent_rate, l, frac, pll_alpha_width(pll)); in alpha_pll_lucid_evo_recalc_rate()
2559 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_pongo_elu_prepare() local
2560 struct regmap *regmap = pll->clkr.regmap; in alpha_pll_pongo_elu_prepare()
2563 /* Enable PLL intially to one-time calibrate against XO. */ in alpha_pll_pongo_elu_prepare()
2564 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); in alpha_pll_pongo_elu_prepare()
2565 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in alpha_pll_pongo_elu_prepare()
2566 regmap_update_bits(regmap, PLL_MODE(pll), PONGO_XO_PRESENT, PONGO_XO_PRESENT); in alpha_pll_pongo_elu_prepare()
2569 pll->clkr.regmap = regmap; in alpha_pll_pongo_elu_prepare()
2570 ret = wait_for_pll_enable_lock(pll); in alpha_pll_pongo_elu_prepare()
2572 /* Reverse calibration - disable PLL output */ in alpha_pll_pongo_elu_prepare()
2573 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in alpha_pll_pongo_elu_prepare()
2577 /* Disable PLL after one-time calibration. */ in alpha_pll_pongo_elu_prepare()
2578 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in alpha_pll_pongo_elu_prepare()
2581 regmap_update_bits(regmap, PLL_MODE(pll), PONGO_CLOCK_SELECT, in alpha_pll_pongo_elu_prepare()
2589 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_pongo_elu_enable() local
2590 struct regmap *regmap = pll->clkr.regmap; in alpha_pll_pongo_elu_enable()
2593 /* Check if PLL is already enabled */ in alpha_pll_pongo_elu_enable()
2594 if (trion_pll_is_enabled(pll, regmap)) in alpha_pll_pongo_elu_enable()
2597 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in alpha_pll_pongo_elu_enable()
2602 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); in alpha_pll_pongo_elu_enable()
2604 ret = wait_for_pll_enable_lock(pll); in alpha_pll_pongo_elu_enable()
2608 /* Enable the global PLL outputs */ in alpha_pll_pongo_elu_enable()
2609 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); in alpha_pll_pongo_elu_enable()
2621 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_pongo_elu_disable() local
2622 struct regmap *regmap = pll->clkr.regmap; in alpha_pll_pongo_elu_disable()
2625 /* Disable the global PLL output */ in alpha_pll_pongo_elu_disable()
2626 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in alpha_pll_pongo_elu_disable()
2630 /* Place the PLL mode in STANDBY */ in alpha_pll_pongo_elu_disable()
2631 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in alpha_pll_pongo_elu_disable()
2637 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_pongo_elu_recalc_rate() local
2638 struct regmap *regmap = pll->clkr.regmap; in alpha_pll_pongo_elu_recalc_rate()
2641 if (regmap_read(regmap, PLL_L_VAL(pll), &l)) in alpha_pll_pongo_elu_recalc_rate()
2646 return alpha_pll_calc_rate(parent_rate, l, 0, pll_alpha_width(pll)); in alpha_pll_pongo_elu_recalc_rate()
2657 void clk_pongo_elu_pll_configure(struct clk_alpha_pll *pll, in clk_pongo_elu_pll_configure() argument
2663 regmap_update_bits(regmap, PLL_USER_CTL(pll), PONGO_PLL_OUT_MASK, in clk_pongo_elu_pll_configure()
2666 if (trion_pll_is_enabled(pll, regmap)) in clk_pongo_elu_pll_configure()
2669 if (regmap_read(regmap, PLL_L_VAL(pll), &val)) in clk_pongo_elu_pll_configure()
2675 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); in clk_pongo_elu_pll_configure()
2676 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); in clk_pongo_elu_pll_configure()
2677 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); in clk_pongo_elu_pll_configure()
2678 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); in clk_pongo_elu_pll_configure()
2679 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); in clk_pongo_elu_pll_configure()
2680 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U2(pll), config->config_ctl_hi2_val); in clk_pongo_elu_pll_configure()
2681 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), in clk_pongo_elu_pll_configure()
2683 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); in clk_pongo_elu_pll_configure()
2684 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); in clk_pongo_elu_pll_configure()
2685 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); in clk_pongo_elu_pll_configure()
2686 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val); in clk_pongo_elu_pll_configure()
2687 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U2(pll), config->test_ctl_hi2_val); in clk_pongo_elu_pll_configure()
2688 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U3(pll), config->test_ctl_hi3_val); in clk_pongo_elu_pll_configure()
2690 /* Disable PLL output */ in clk_pongo_elu_pll_configure()
2691 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in clk_pongo_elu_pll_configure()
2695 void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, in clk_rivian_evo_pll_configure() argument
2698 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); in clk_rivian_evo_pll_configure()
2699 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); in clk_rivian_evo_pll_configure()
2700 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); in clk_rivian_evo_pll_configure()
2701 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); in clk_rivian_evo_pll_configure()
2702 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); in clk_rivian_evo_pll_configure()
2703 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); in clk_rivian_evo_pll_configure()
2704 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); in clk_rivian_evo_pll_configure()
2705 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); in clk_rivian_evo_pll_configure()
2707 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in clk_rivian_evo_pll_configure()
2709 regmap_update_bits(regmap, PLL_MODE(pll), in clk_rivian_evo_pll_configure()
2718 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_rivian_evo_pll_recalc_rate() local
2721 if (regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l)) in clk_rivian_evo_pll_recalc_rate()
2730 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_rivian_evo_pll_round_rate() local
2736 if (!pll->vco_table || alpha_pll_find_vco(pll, rate)) in clk_rivian_evo_pll_round_rate()
2739 min_freq = pll->vco_table[0].min_freq; in clk_rivian_evo_pll_round_rate()
2740 max_freq = pll->vco_table[pll->num_vco - 1].max_freq; in clk_rivian_evo_pll_round_rate()
2754 void clk_stromer_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, in clk_stromer_pll_configure() argument
2759 regmap_write(regmap, PLL_L_VAL(pll), config->l); in clk_stromer_pll_configure()
2760 regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha); in clk_stromer_pll_configure()
2761 regmap_write(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); in clk_stromer_pll_configure()
2763 if (pll_has_64bit_config(pll)) in clk_stromer_pll_configure()
2764 regmap_write(regmap, PLL_CONFIG_CTL_U(pll), in clk_stromer_pll_configure()
2767 if (pll_alpha_width(pll) > 32) in clk_stromer_pll_configure()
2768 regmap_write(regmap, PLL_ALPHA_VAL_U(pll), config->alpha_hi); in clk_stromer_pll_configure()
2790 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val); in clk_stromer_pll_configure()
2792 /* Stromer APSS PLL does not enable LOCK_DET by default, so enable it */ in clk_stromer_pll_configure()
2799 regmap_update_bits(regmap, PLL_USER_CTL_U(pll), mask_u, val_u); in clk_stromer_pll_configure()
2800 regmap_write(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); in clk_stromer_pll_configure()
2801 regmap_write(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); in clk_stromer_pll_configure()
2803 if (pll->flags & SUPPORTS_FSM_MODE) in clk_stromer_pll_configure()
2804 qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0); in clk_stromer_pll_configure()
2823 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_alpha_pll_stromer_set_rate() local
2830 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); in clk_alpha_pll_stromer_set_rate()
2833 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); in clk_alpha_pll_stromer_set_rate()
2834 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), in clk_alpha_pll_stromer_set_rate()
2837 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), in clk_alpha_pll_stromer_set_rate()
2844 * Stromer PLL supports Dynamic programming. in clk_alpha_pll_stromer_set_rate()
2845 * It allows the PLL frequency to be changed on-the-fly without first in clk_alpha_pll_stromer_set_rate()
2848 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, in clk_alpha_pll_stromer_set_rate()
2851 ret = wait_for_pll_update(pll); in clk_alpha_pll_stromer_set_rate()
2855 return wait_for_pll_enable_lock(pll); in clk_alpha_pll_stromer_set_rate()
2872 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_alpha_pll_stromer_plus_set_rate() local
2873 u32 l, alpha_width = pll_alpha_width(pll); in clk_alpha_pll_stromer_plus_set_rate()
2879 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &pll_mode); in clk_alpha_pll_stromer_plus_set_rate()
2883 regmap_write(pll->clkr.regmap, PLL_MODE(pll), 0); in clk_alpha_pll_stromer_plus_set_rate()
2888 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); in clk_alpha_pll_stromer_plus_set_rate()
2893 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); in clk_alpha_pll_stromer_plus_set_rate()
2894 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), in clk_alpha_pll_stromer_plus_set_rate()
2897 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), in clk_alpha_pll_stromer_plus_set_rate()
2900 regmap_write(pll->clkr.regmap, PLL_MODE(pll), PLL_BYPASSNL); in clk_alpha_pll_stromer_plus_set_rate()
2904 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_RESET_N, in clk_alpha_pll_stromer_plus_set_rate()
2910 ret = wait_for_pll_enable_lock(pll); in clk_alpha_pll_stromer_plus_set_rate()
2912 pr_err("Wait for PLL enable lock failed [%s] %d\n", in clk_alpha_pll_stromer_plus_set_rate()
2918 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, in clk_alpha_pll_stromer_plus_set_rate()
2934 void clk_regera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, in clk_regera_pll_configure() argument
2937 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); in clk_regera_pll_configure()
2938 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); in clk_regera_pll_configure()
2939 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); in clk_regera_pll_configure()
2940 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); in clk_regera_pll_configure()
2941 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); in clk_regera_pll_configure()
2942 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); in clk_regera_pll_configure()
2943 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); in clk_regera_pll_configure()
2944 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll), config->user_ctl_hi1_val); in clk_regera_pll_configure()
2945 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); in clk_regera_pll_configure()
2946 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); in clk_regera_pll_configure()
2947 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val); in clk_regera_pll_configure()
2950 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in clk_regera_pll_configure()