Lines Matching +full:hart +full:- +full:3
1 // SPDX-License-Identifier: GPL-2.0-only
24 #include <asm/text-patching.h>
32 #define NUM_ALPHA_EXTS ('z' - 'a' + 1)
42 /* Per-cpu ISA extensions. */
48 * riscv_isa_extension_base() - Get base extension word
62 * __riscv_isa_extension_available() - Check whether given extension
88 return -EPROBE_DEFER; in riscv_ext_f_depends()
95 pr_err("Zicbom detected in ISA string, disabling as no cbom-block-size found\n"); in riscv_ext_zicbom_validate()
96 return -EINVAL; in riscv_ext_zicbom_validate()
99 pr_err("Zicbom disabled as cbom-block-size present, but is not a power-of-2\n"); in riscv_ext_zicbom_validate()
100 return -EINVAL; in riscv_ext_zicbom_validate()
111 pr_err("Zicboz detected in ISA string, disabling as no cboz-block-size found\n"); in riscv_ext_zicboz_validate()
112 return -EINVAL; in riscv_ext_zicboz_validate()
115 pr_err("Zicboz disabled as cboz-block-size present, but is not a power-of-2\n"); in riscv_ext_zicboz_validate()
116 return -EINVAL; in riscv_ext_zicboz_validate()
126 return -EINVAL; in riscv_ext_f_validate()
134 return -EINVAL; in riscv_ext_f_validate()
144 return -EINVAL; in riscv_ext_d_validate()
153 return -EINVAL; in riscv_ext_vector_x_validate()
162 return -EINVAL; in riscv_ext_vector_float_validate()
165 return -EINVAL; in riscv_ext_vector_float_validate()
176 return -EINVAL; in riscv_ext_vector_float_validate()
185 return -EINVAL; in riscv_ext_vector_crypto_validate()
190 * enabled, which in-turn means that vector is usable in this kernel in riscv_ext_vector_crypto_validate()
193 return -EPROBE_DEFER; in riscv_ext_vector_crypto_validate()
204 return -EPROBE_DEFER; in riscv_ext_zca_depends()
213 return -EPROBE_DEFER; in riscv_ext_zcd_validate()
220 return -EINVAL; in riscv_ext_zcf_validate()
226 return -EPROBE_DEFER; in riscv_ext_zcf_validate()
233 return -EINVAL; in riscv_vector_f_validate()
238 return -EPROBE_DEFER; in riscv_vector_f_validate()
248 return -EPROBE_DEFER; in riscv_ext_zvfbfwma_validate()
256 return -EOPNOTSUPP; in riscv_ext_svadu_validate()
371 * While the [ms]envcfg CSRs were not defined until version 1.12 of the RISC-V
382 * - C always implies Zca
383 * - C+F implies Zcf (RV32 only)
384 * - C+D implies Zcd
399 * Ordinarily, for in-kernel data structures, this order is unimportant but
405 * 1. All multi-letter extensions must be separated from other extensions by an
409 * single-letter extensions and before any higher-privileged extensions.
411 * 3. The first letter following the 'Z' conventionally indicates the most
416 * 3. Standard supervisor-level extensions (starting with 'S') must be listed
417 * after standard unprivileged extensions. If multiple supervisor-level
420 * 4. Standard machine-level extensions (starting with 'Zxm') must be listed
421 * after any lower-privileged, standard extensions. If multiple
422 * machine-level extensions are listed, they must be ordered
425 * 5. Non-standard extensions (starting with 'X') must be listed after all
426 * standard extensions. If multiple non-standard extensions are listed, they
532 if (ext->id != RISCV_ISA_EXT_INVALID) in riscv_isa_set_ext()
533 set_bit(ext->id, bitmap); in riscv_isa_set_ext()
535 for (int i = 0; i < ext->subset_ext_size; i++) { in riscv_isa_set_ext()
536 if (ext->subset_ext_ids[i] != RISCV_ISA_EXT_INVALID) in riscv_isa_set_ext()
537 set_bit(ext->subset_ext_ids[i], bitmap); in riscv_isa_set_ext()
570 if (max_loop_count-- < 0) { in riscv_resolve_isa()
578 if (ext && ext->validate) { in riscv_resolve_isa()
579 ret = ext->validate(ext, resolved_isa); in riscv_resolve_isa()
580 if (ret == -EPROBE_DEFER) { in riscv_resolve_isa()
606 if ((name_end - name == strlen(ext->name)) && in match_isa_ext()
607 !strncasecmp(name, ext->name, name_end - name)) { in match_isa_ext()
633 pr_warn_once("Vendor extensions are ignored in riscv,isa. Use riscv,isa-extensions instead."); in riscv_parse_isa_string()
636 * As multi-letter extensions must be split from other multi-letter in riscv_parse_isa_string()
637 * extensions with an "_", the end of a multi-letter extension will in riscv_parse_isa_string()
639 * multi-letter extension. in riscv_parse_isa_string()
647 * Workaround for invalid single-letter 's' & 'u' (QEMU). in riscv_parse_isa_string()
650 * multi-letter extension in the ISA string begins with in riscv_parse_isa_string()
653 if (ext[-1] != '_' && ext[1] == 'u') { in riscv_parse_isa_string()
664 * As multi-letter extensions must be split from other multi-letter in riscv_parse_isa_string()
665 * extensions with an "_", the end of a multi-letter extension will in riscv_parse_isa_string()
667 * multi-letter extension. in riscv_parse_isa_string()
678 * A simple re-increment solves this problem. in riscv_parse_isa_string()
688 if (!isdigit(ext_end[-1])) in riscv_parse_isa_string()
691 while (isdigit(*--ext_end)) in riscv_parse_isa_string()
694 if (tolower(ext_end[0]) != 'p' || !isdigit(ext_end[-1])) { in riscv_parse_isa_string()
699 while (isdigit(*--ext_end)) in riscv_parse_isa_string()
706 * Things are a little easier for single-letter extensions, as they in riscv_parse_isa_string()
713 * If we are already on a non-digit, there is nothing to do. Either in riscv_parse_isa_string()
714 * we have a multi-letter extension's _, or the start of an in riscv_parse_isa_string()
738 --isa; in riscv_parse_isa_string()
751 * on meeting a non-alphanumeric character, an extra increment is needed in riscv_parse_isa_string()
752 * where the succeeding extension is a multi-letter prefixed with an "_". in riscv_parse_isa_string()
805 pr_warn("Unable to get ISA for the hart - %d\n", cpu); in riscv_fill_hwcap_from_isa_string()
814 * port & dt-bindings were upstreamed, and so can be set in riscv_fill_hwcap_from_isa_string()
826 * just the standard V-1.0 but vendors aren't well behaved. in riscv_fill_hwcap_from_isa_string()
827 * Many vendors with T-Head CPU cores which implement the 0.7.1 in riscv_fill_hwcap_from_isa_string()
829 * CPU cores with the ratified spec will contain non-zero in riscv_fill_hwcap_from_isa_string()
837 riscv_resolve_isa(source_isa, isainfo->isa, &this_hwcap, isa2hwcap); in riscv_fill_hwcap_from_isa_string()
840 * All "okay" hart should have same isa. Set HWCAP based on in riscv_fill_hwcap_from_isa_string()
841 * common capabilities of every "okay" hart, in case they don't in riscv_fill_hwcap_from_isa_string()
850 bitmap_copy(riscv_isa, isainfo->isa, RISCV_ISA_EXT_MAX); in riscv_fill_hwcap_from_isa_string()
852 bitmap_and(riscv_isa, riscv_isa, isainfo->isa, RISCV_ISA_EXT_MAX); in riscv_fill_hwcap_from_isa_string()
867 for (int j = 0; j < ext_list->ext_data_count; j++) { in riscv_fill_cpu_vendor_ext()
868 const struct riscv_isa_ext_data ext = ext_list->ext_data[j]; in riscv_fill_cpu_vendor_ext()
869 struct riscv_isavendorinfo *isavendorinfo = &ext_list->per_hart_isa_bitmap[cpu]; in riscv_fill_cpu_vendor_ext()
871 if (of_property_match_string(cpu_node, "riscv,isa-extensions", in riscv_fill_cpu_vendor_ext()
881 set_bit(ext.subset_ext_ids[k], isavendorinfo->isa); in riscv_fill_cpu_vendor_ext()
883 set_bit(ext.id, isavendorinfo->isa); in riscv_fill_cpu_vendor_ext()
900 if (!ext_list->is_initialized) { in riscv_fill_vendor_ext_list()
901 bitmap_copy(ext_list->all_harts_isa_bitmap.isa, in riscv_fill_vendor_ext_list()
902 ext_list->per_hart_isa_bitmap[cpu].isa, in riscv_fill_vendor_ext_list()
904 ext_list->is_initialized = true; in riscv_fill_vendor_ext_list()
906 bitmap_and(ext_list->all_harts_isa_bitmap.isa, in riscv_fill_vendor_ext_list()
907 ext_list->all_harts_isa_bitmap.isa, in riscv_fill_vendor_ext_list()
908 ext_list->per_hart_isa_bitmap[cpu].isa, in riscv_fill_vendor_ext_list()
930 return -ENOENT; in has_thead_homogeneous_vlenb()
937 return -ENOENT; in has_thead_homogeneous_vlenb()
943 return -ENOENT; in has_thead_homogeneous_vlenb()
971 if (!of_property_present(cpu_node, "riscv,isa-extensions")) { in riscv_fill_hwcap_from_ext_list()
979 if (of_property_match_string(cpu_node, "riscv,isa-extensions", in riscv_fill_hwcap_from_ext_list()
980 ext->property) < 0) in riscv_fill_hwcap_from_ext_list()
986 riscv_resolve_isa(source_isa, isainfo->isa, &this_hwcap, isa2hwcap); in riscv_fill_hwcap_from_ext_list()
993 * common capabilities of every "okay" hart, in case they don't. in riscv_fill_hwcap_from_ext_list()
1001 bitmap_copy(riscv_isa, isainfo->isa, RISCV_ISA_EXT_MAX); in riscv_fill_hwcap_from_ext_list()
1003 bitmap_and(riscv_isa, riscv_isa, isainfo->isa, RISCV_ISA_EXT_MAX); in riscv_fill_hwcap_from_ext_list()
1020 return -ENOENT; in riscv_fill_hwcap_from_ext_list()
1043 isa2hwcap['i' - 'a'] = COMPAT_HWCAP_ISA_I; in riscv_fill_hwcap()
1044 isa2hwcap['m' - 'a'] = COMPAT_HWCAP_ISA_M; in riscv_fill_hwcap()
1045 isa2hwcap['a' - 'a'] = COMPAT_HWCAP_ISA_A; in riscv_fill_hwcap()
1046 isa2hwcap['f' - 'a'] = COMPAT_HWCAP_ISA_F; in riscv_fill_hwcap()
1047 isa2hwcap['d' - 'a'] = COMPAT_HWCAP_ISA_D; in riscv_fill_hwcap()
1048 isa2hwcap['c' - 'a'] = COMPAT_HWCAP_ISA_C; in riscv_fill_hwcap()
1049 isa2hwcap['v' - 'a'] = COMPAT_HWCAP_ISA_V; in riscv_fill_hwcap()
1074 * This cannot fail when called on the boot hart in riscv_fill_hwcap()
1096 hwcap = (elf_hwcap & ((1UL << RISCV_ISA_EXT_BASE) - 1)); in riscv_get_elf_hwcap()
1107 current->thread.envcfg |= ENVCFG_CBZE; in riscv_user_isa_enable()
1112 current->thread.envcfg |= ENVCFG_CBCFE; in riscv_user_isa_enable()
1121 * 16-bit vendor ID and a 32-bit patch ID. A non-zero vendor ID means the
1122 * patch site is for an erratum, identified by the 32-bit patch ID. When
1124 * further break down patch ID into two 16-bit numbers. The lower 16 bits
1128 * patching on a per-site basis will provide non-zero values and implement
1163 id = PATCH_ID_CPUFEATURE_ID(alt->patch_id); in riscv_cpufeature_patch_func()
1164 vendor = PATCH_ID_CPUFEATURE_ID(alt->vendor_id); in riscv_cpufeature_patch_func()
1179 if (alt->vendor_id != 0) in riscv_cpufeature_patch_func()
1185 value = PATCH_ID_CPUFEATURE_VALUE(alt->patch_id); in riscv_cpufeature_patch_func()
1190 id - RISCV_VENDOR_EXT_ALTERNATIVES_BASE)) in riscv_cpufeature_patch_func()
1201 patch_text_nosync(oldptr, altptr, alt->alt_len); in riscv_cpufeature_patch_func()
1202 riscv_alternative_fix_offsets(oldptr, alt->alt_len, oldptr - altptr); in riscv_cpufeature_patch_func()