Lines Matching +full:imx7ulp +full:- +full:lpi2c
1 // SPDX-License-Identifier: (GPL-2.0-only OR MIT)
6 #include <dt-bindings/dma/fsl-edma.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/thermal/thermal.h>
12 #include "imx95-clock.h"
13 #include "imx95-pinfunc.h"
14 #include "imx95-power.h"
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
22 #address-cells = <1>;
23 #size-cells = <0>;
25 idle-states {
26 entry-method = "psci";
28 cpu_pd_wait: cpu-pd-wait {
29 compatible = "arm,idle-state";
30 arm,psci-suspend-param = <0x0010033>;
31 local-timer-stop;
32 entry-latency-us = <10000>;
33 exit-latency-us = <7000>;
34 min-residency-us = <27000>;
35 wakeup-latency-us = <15000>;
41 compatible = "arm,cortex-a55";
43 enable-method = "psci";
44 #cooling-cells = <2>;
45 cpu-idle-states = <&cpu_pd_wait>;
46 power-domains = <&scmi_perf IMX95_PERF_A55>;
47 power-domain-names = "perf";
48 i-cache-size = <32768>;
49 i-cache-line-size = <64>;
50 i-cache-sets = <128>;
51 d-cache-size = <32768>;
52 d-cache-line-size = <64>;
53 d-cache-sets = <128>;
54 next-level-cache = <&l2_cache_l0>;
59 compatible = "arm,cortex-a55";
61 enable-method = "psci";
62 #cooling-cells = <2>;
63 cpu-idle-states = <&cpu_pd_wait>;
64 power-domains = <&scmi_perf IMX95_PERF_A55>;
65 power-domain-names = "perf";
66 i-cache-size = <32768>;
67 i-cache-line-size = <64>;
68 i-cache-sets = <128>;
69 d-cache-size = <32768>;
70 d-cache-line-size = <64>;
71 d-cache-sets = <128>;
72 next-level-cache = <&l2_cache_l1>;
77 compatible = "arm,cortex-a55";
79 enable-method = "psci";
80 #cooling-cells = <2>;
81 cpu-idle-states = <&cpu_pd_wait>;
82 power-domains = <&scmi_perf IMX95_PERF_A55>;
83 power-domain-names = "perf";
84 i-cache-size = <32768>;
85 i-cache-line-size = <64>;
86 i-cache-sets = <128>;
87 d-cache-size = <32768>;
88 d-cache-line-size = <64>;
89 d-cache-sets = <128>;
90 next-level-cache = <&l2_cache_l2>;
95 compatible = "arm,cortex-a55";
97 enable-method = "psci";
98 #cooling-cells = <2>;
99 cpu-idle-states = <&cpu_pd_wait>;
100 power-domains = <&scmi_perf IMX95_PERF_A55>;
101 power-domain-names = "perf";
102 i-cache-size = <32768>;
103 i-cache-line-size = <64>;
104 i-cache-sets = <128>;
105 d-cache-size = <32768>;
106 d-cache-line-size = <64>;
107 d-cache-sets = <128>;
108 next-level-cache = <&l2_cache_l3>;
113 compatible = "arm,cortex-a55";
115 power-domains = <&scmi_perf IMX95_PERF_A55>;
116 power-domain-names = "perf";
117 enable-method = "psci";
118 #cooling-cells = <2>;
119 cpu-idle-states = <&cpu_pd_wait>;
120 i-cache-size = <32768>;
121 i-cache-line-size = <64>;
122 i-cache-sets = <128>;
123 d-cache-size = <32768>;
124 d-cache-line-size = <64>;
125 d-cache-sets = <128>;
126 next-level-cache = <&l2_cache_l4>;
131 compatible = "arm,cortex-a55";
133 power-domains = <&scmi_perf IMX95_PERF_A55>;
134 power-domain-names = "perf";
135 enable-method = "psci";
136 #cooling-cells = <2>;
137 cpu-idle-states = <&cpu_pd_wait>;
138 i-cache-size = <32768>;
139 i-cache-line-size = <64>;
140 i-cache-sets = <128>;
141 d-cache-size = <32768>;
142 d-cache-line-size = <64>;
143 d-cache-sets = <128>;
144 next-level-cache = <&l2_cache_l5>;
147 l2_cache_l0: l2-cache-l0 {
149 cache-size = <65536>;
150 cache-line-size = <64>;
151 cache-sets = <256>;
152 cache-level = <2>;
153 cache-unified;
154 next-level-cache = <&l3_cache>;
157 l2_cache_l1: l2-cache-l1 {
159 cache-size = <65536>;
160 cache-line-size = <64>;
161 cache-sets = <256>;
162 cache-level = <2>;
163 cache-unified;
164 next-level-cache = <&l3_cache>;
167 l2_cache_l2: l2-cache-l2 {
169 cache-size = <65536>;
170 cache-line-size = <64>;
171 cache-sets = <256>;
172 cache-level = <2>;
173 cache-unified;
174 next-level-cache = <&l3_cache>;
177 l2_cache_l3: l2-cache-l3 {
179 cache-size = <65536>;
180 cache-line-size = <64>;
181 cache-sets = <256>;
182 cache-level = <2>;
183 cache-unified;
184 next-level-cache = <&l3_cache>;
187 l2_cache_l4: l2-cache-l4 {
189 cache-size = <65536>;
190 cache-line-size = <64>;
191 cache-sets = <256>;
192 cache-level = <2>;
193 cache-unified;
194 next-level-cache = <&l3_cache>;
197 l2_cache_l5: l2-cache-l5 {
199 cache-size = <65536>;
200 cache-line-size = <64>;
201 cache-sets = <256>;
202 cache-level = <2>;
203 cache-unified;
204 next-level-cache = <&l3_cache>;
207 l3_cache: l3-cache {
209 cache-size = <524288>;
210 cache-line-size = <64>;
211 cache-sets = <512>;
212 cache-level = <3>;
213 cache-unified;
216 cpu-map {
245 dummy: clock-dummy {
246 compatible = "fixed-clock";
247 #clock-cells = <0>;
248 clock-frequency = <0>;
249 clock-output-names = "dummy";
252 clk_ext1: clock-ext1 {
253 compatible = "fixed-clock";
254 #clock-cells = <0>;
255 clock-frequency = <133000000>;
256 clock-output-names = "clk_ext1";
259 sai1_mclk: clock-sai-mclk1 {
260 compatible = "fixed-clock";
261 #clock-cells = <0>;
262 clock-frequency= <0>;
263 clock-output-names = "sai1_mclk";
266 sai2_mclk: clock-sai-mclk2 {
267 compatible = "fixed-clock";
268 #clock-cells = <0>;
269 clock-frequency= <0>;
270 clock-output-names = "sai2_mclk";
273 sai3_mclk: clock-sai-mclk3 {
274 compatible = "fixed-clock";
275 #clock-cells = <0>;
276 clock-frequency= <0>;
277 clock-output-names = "sai3_mclk";
280 sai4_mclk: clock-sai-mclk4 {
281 compatible = "fixed-clock";
282 #clock-cells = <0>;
283 clock-frequency= <0>;
284 clock-output-names = "sai4_mclk";
287 sai5_mclk: clock-sai-mclk5 {
288 compatible = "fixed-clock";
289 #clock-cells = <0>;
290 clock-frequency= <0>;
291 clock-output-names = "sai5_mclk";
294 clk_sys100m: clock-sys100m {
295 compatible = "fixed-clock";
296 #clock-cells = <0>;
297 clock-frequency = <100000000>;
298 clock-output-names = "clk_sys100m";
301 osc_24m: clock-24m {
302 compatible = "fixed-clock";
303 #clock-cells = <0>;
304 clock-frequency = <24000000>;
305 clock-output-names = "osc_24m";
309 compatible = "mmio-sram";
312 #address-cells = <1>;
313 #size-cells = <1>;
321 #address-cells = <1>;
322 #size-cells = <0>;
323 arm,max-rx-timeout-ms = <5000>;
327 #power-domain-cells = <1>;
336 #power-domain-cells = <1>;
341 #clock-cells = <1>;
346 #thermal-sensor-cells = <1>;
364 compatible = "arm,cortex-a55-pmu";
368 thermal_zones: thermal-zones {
369 a55-thermal {
370 polling-delay-passive = <250>;
371 polling-delay = <2000>;
372 thermal-sensors = <&scmi_sensor 1>;
388 cooling-maps {
391 cooling-device =
402 ana-thermal {
403 polling-delay-passive = <250>;
404 polling-delay = <2000>;
405 thermal-sensors = <&scmi_sensor 0>;
420 cooling-maps {
423 cooling-device =
436 compatible = "arm,psci-1.0";
441 compatible = "arm,armv8-timer";
446 clock-frequency = <24000000>;
447 arm,no-tick-in-suspend;
448 interrupt-parent = <&gic>;
451 gic: interrupt-controller@48000000 {
452 compatible = "arm,gic-v3";
455 #address-cells = <2>;
456 #size-cells = <2>;
457 #interrupt-cells = <3>;
458 interrupt-controller;
460 interrupt-parent = <&gic>;
461 dma-noncoherent;
464 its: msi-controller@48040000 {
465 compatible = "arm,gic-v3-its";
467 msi-controller;
468 #msi-cells = <1>;
469 dma-noncoherent;
474 compatible = "simple-bus";
475 #address-cells = <2>;
476 #size-cells = <2>;
480 compatible = "fsl,aips-bus", "simple-bus";
484 #address-cells = <1>;
485 #size-cells = <1>;
487 edma2: dma-controller@42000000 {
488 compatible = "fsl,imx95-edma5";
490 #dma-cells = <3>;
491 dma-channels = <64>;
557 clock-names = "dma";
560 edma3: dma-controller@42210000 {
561 compatible = "fsl,imx95-edma5";
563 #dma-cells = <3>;
564 dma-channels = <64>;
630 clock-names = "dma";
634 compatible = "fsl,imx95-mu";
638 #mbox-cells = <2>;
643 compatible = "fsl,imx93-wdt";
647 timeout-sec = <40>;
652 compatible = "fsl,imx7ulp-pwm";
655 #pwm-cells = <3>;
660 compatible = "fsl,imx7ulp-pwm";
663 #pwm-cells = <3>;
668 compatible = "fsl,imx7ulp-pwm";
671 #pwm-cells = <3>;
676 compatible = "fsl,imx7ulp-pwm";
679 #pwm-cells = <3>;
684 compatible = "silvaco,i3c-master-v1";
687 #address-cells = <3>;
688 #size-cells = <0>;
692 clock-names = "pclk", "fast_clk", "slow_clk";
697 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c";
702 clock-names = "per", "ipg";
703 #address-cells = <1>;
704 #size-cells = <0>;
706 dma-names = "tx", "rx";
711 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c";
716 clock-names = "per", "ipg";
717 #address-cells = <1>;
718 #size-cells = <0>;
720 dma-names = "tx", "rx";
725 #address-cells = <1>;
726 #size-cells = <0>;
727 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi";
732 clock-names = "per", "ipg";
734 dma-names = "tx", "rx";
739 #address-cells = <1>;
740 #size-cells = <0>;
741 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi";
746 clock-names = "per", "ipg";
748 dma-names = "tx", "rx";
753 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart",
754 "fsl,imx7ulp-lpuart";
758 clock-names = "ipg";
760 dma-names = "rx", "tx";
765 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart",
766 "fsl,imx7ulp-lpuart";
770 clock-names = "ipg";
772 dma-names = "rx", "tx";
777 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart",
778 "fsl,imx7ulp-lpuart";
782 clock-names = "ipg";
784 dma-names = "rx", "tx";
789 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart",
790 "fsl,imx7ulp-lpuart";
794 clock-names = "ipg";
796 dma-names = "rx", "tx";
801 compatible = "fsl,imx95-flexcan";
806 clock-names = "ipg", "per";
807 assigned-clocks = <&scmi_clk IMX95_CLK_CAN2>;
808 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;
809 assigned-clock-rates = <40000000>;
810 fsl,clk-source = /bits/ 8 <0>;
815 compatible = "fsl,imx95-flexcan";
820 clock-names = "ipg", "per";
821 assigned-clocks = <&scmi_clk IMX95_CLK_CAN3>;
822 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;
823 assigned-clock-rates = <40000000>;
824 fsl,clk-source = /bits/ 8 <0>;
829 compatible = "nxp,imx8mm-fspi";
831 reg-names = "fspi_base", "fspi_mmap";
832 #address-cells = <1>;
833 #size-cells = <0>;
837 clock-names = "fspi_en", "fspi";
838 assigned-clocks = <&scmi_clk IMX95_CLK_FLEXSPI1>;
839 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1>;
840 assigned-clock-rates = <200000000>;
845 compatible = "fsl,imx95-sai";
851 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
853 dma-names = "rx", "tx";
858 compatible = "fsl,imx95-sai";
864 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
866 dma-names = "rx", "tx";
871 compatible = "fsl,imx95-sai";
877 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
879 dma-names = "rx", "tx";
884 compatible = "fsl,imx95-xcvr";
887 reg-names = "ram", "regs", "rxfifo", "txfifo";
896 clock-names = "ipg", "phy", "spba", "pll_ipg";
898 dma-names = "rx", "tx";
903 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart",
904 "fsl,imx7ulp-lpuart";
908 clock-names = "ipg";
910 dma-names = "rx", "tx";
915 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart",
916 "fsl,imx7ulp-lpuart";
920 clock-names = "ipg";
922 dma-names = "rx", "tx";
927 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c";
932 clock-names = "per", "ipg";
933 #address-cells = <1>;
934 #size-cells = <0>;
936 dma-names = "tx", "rx";
941 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c";
946 clock-names = "per", "ipg";
947 #address-cells = <1>;
948 #size-cells = <0>;
950 dma-names = "tx", "rx";
955 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c";
960 clock-names = "per", "ipg";
961 #address-cells = <1>;
962 #size-cells = <0>;
964 dma-names = "tx", "rx";
969 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c";
974 clock-names = "per", "ipg";
975 #address-cells = <1>;
976 #size-cells = <0>;
978 dma-names = "tx", "rx";
983 #address-cells = <1>;
984 #size-cells = <0>;
985 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi";
990 clock-names = "per", "ipg";
992 dma-names = "tx", "rx";
997 #address-cells = <1>;
998 #size-cells = <0>;
999 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi";
1004 clock-names = "per", "ipg";
1006 dma-names = "tx", "rx";
1011 #address-cells = <1>;
1012 #size-cells = <0>;
1013 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi";
1018 clock-names = "per", "ipg";
1020 dma-names = "tx", "rx";
1025 #address-cells = <1>;
1026 #size-cells = <0>;
1027 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi";
1032 clock-names = "per", "ipg";
1034 dma-names = "tx", "rx";
1039 compatible = "fsl,imx95-mu";
1043 #mbox-cells = <2>;
1048 compatible = "fsl,imx95-flexcan";
1053 clock-names = "ipg", "per";
1054 assigned-clocks = <&scmi_clk IMX95_CLK_CAN4>;
1055 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;
1056 assigned-clock-rates = <40000000>;
1057 fsl,clk-source = /bits/ 8 <0>;
1062 compatible = "fsl,imx95-flexcan";
1067 clock-names = "ipg", "per";
1068 assigned-clocks = <&scmi_clk IMX95_CLK_CAN5>;
1069 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;
1070 assigned-clock-rates = <40000000>;
1071 fsl,clk-source = /bits/ 8 <0>;
1077 compatible = "fsl,aips-bus", "simple-bus";
1079 #address-cells = <1>;
1080 #size-cells = <1>;
1084 compatible = "fsl,imx95-usdhc", "fsl,imx8mm-usdhc";
1090 clock-names = "ipg", "ahb", "per";
1091 assigned-clocks = <&scmi_clk IMX95_CLK_USDHC1>;
1092 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1>;
1093 assigned-clock-rates = <400000000>;
1094 bus-width = <8>;
1095 fsl,tuning-start-tap = <1>;
1096 fsl,tuning-step= <2>;
1101 compatible = "fsl,imx95-usdhc", "fsl,imx8mm-usdhc";
1107 clock-names = "ipg", "ahb", "per";
1108 assigned-clocks = <&scmi_clk IMX95_CLK_USDHC2>;
1109 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1>;
1110 assigned-clock-rates = <400000000>;
1111 bus-width = <4>;
1112 fsl,tuning-start-tap = <1>;
1113 fsl,tuning-step= <2>;
1118 compatible = "fsl,imx95-usdhc", "fsl,imx8mm-usdhc";
1124 clock-names = "ipg", "ahb", "per";
1125 assigned-clocks = <&scmi_clk IMX95_CLK_USDHC3>;
1126 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1>;
1127 assigned-clock-rates = <400000000>;
1128 bus-width = <4>;
1129 fsl,tuning-start-tap = <1>;
1130 fsl,tuning-step= <2>;
1136 compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio";
1138 gpio-controller;
1139 #gpio-cells = <2>;
1142 interrupt-controller;
1143 #interrupt-cells = <2>;
1146 clock-names = "gpio", "port";
1147 gpio-ranges = <&scmi_iomuxc 0 4 32>;
1151 compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio";
1153 gpio-controller;
1154 #gpio-cells = <2>;
1157 interrupt-controller;
1158 #interrupt-cells = <2>;
1161 clock-names = "gpio", "port";
1162 gpio-ranges = <&scmi_iomuxc 0 104 8>, <&scmi_iomuxc 8 74 18>,
1167 compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio";
1169 gpio-controller;
1170 #gpio-cells = <2>;
1173 interrupt-controller;
1174 #interrupt-cells = <2>;
1177 clock-names = "gpio", "port";
1178 gpio-ranges = <&scmi_iomuxc 0 46 28>, <&scmi_iomuxc 28 44 2>;
1182 compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio";
1184 gpio-controller;
1185 #gpio-cells = <2>;
1188 interrupt-controller;
1189 #interrupt-cells = <2>;
1192 clock-names = "gpio", "port";
1193 gpio-ranges = <&scmi_iomuxc 0 92 12>, <&scmi_iomuxc 12 36 6>;
1197 compatible = "fsl,aips-bus", "simple-bus";
1200 #address-cells = <1>;
1201 #size-cells = <1>;
1203 edma1: dma-controller@44000000 {
1204 compatible = "fsl,imx93-edma3";
1206 #dma-cells = <3>;
1207 dma-channels = <31>;
1240 clock-names = "dma";
1244 compatible = "fsl,imx95-mu";
1248 #mbox-cells = <2>;
1253 compatible = "fsl,imx7ulp-pwm";
1256 #pwm-cells = <3>;
1261 compatible = "fsl,imx7ulp-pwm";
1264 #pwm-cells = <3>;
1269 compatible = "silvaco,i3c-master-v1";
1272 #address-cells = <3>;
1273 #size-cells = <0>;
1277 clock-names = "pclk", "fast_clk", "slow_clk";
1282 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c";
1287 clock-names = "per", "ipg";
1288 #address-cells = <1>;
1289 #size-cells = <0>;
1291 dma-names = "tx", "rx";
1296 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c";
1301 clock-names = "per", "ipg";
1302 #address-cells = <1>;
1303 #size-cells = <0>;
1305 dma-names = "tx", "rx";
1310 #address-cells = <1>;
1311 #size-cells = <0>;
1312 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi";
1317 clock-names = "per", "ipg";
1319 dma-names = "tx", "rx";
1324 #address-cells = <1>;
1325 #size-cells = <0>;
1326 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi";
1331 clock-names = "per", "ipg";
1333 dma-names = "tx", "rx";
1338 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart",
1339 "fsl,imx7ulp-lpuart";
1343 clock-names = "ipg";
1345 dma-names = "rx", "tx";
1350 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart",
1351 "fsl,imx7ulp-lpuart";
1355 clock-names = "ipg";
1357 dma-names = "rx", "tx";
1362 compatible = "fsl,imx95-flexcan";
1367 clock-names = "ipg", "per";
1368 assigned-clocks = <&scmi_clk IMX95_CLK_CAN1>;
1369 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;
1370 assigned-clock-rates = <40000000>;
1371 fsl,clk-source = /bits/ 8 <0>;
1376 compatible = "fsl,imx95-sai";
1382 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
1384 dma-names = "rx", "tx";
1389 compatible = "fsl,imx95-micfil", "fsl,imx93-micfil";
1400 clock-names = "ipg_clk", "ipg_clk_app",
1403 dma-names = "rx";
1408 compatible = "nxp,imx93-adc";
1414 clock-names = "ipg";
1415 #io-channel-cells = <1>;
1420 compatible = "fsl,imx95-mu";
1424 #address-cells = <1>;
1425 #size-cells = <1>;
1426 #mbox-cells = <2>;
1429 compatible = "mmio-sram";
1432 #address-cells = <1>;
1433 #size-cells = <1>;
1435 scmi_buf0: scmi-sram-section@0 {
1436 compatible = "arm,scmi-shmem";
1440 scmi_buf1: scmi-sram-section@80 {
1441 compatible = "arm,scmi-shmem";
1449 compatible = "fsl,imx95-mu";
1453 #mbox-cells = <2>;
1458 compatible = "fsl,imx95-mu";
1462 #mbox-cells = <2>;
1467 compatible = "fsl,imx95-mu";
1471 #mbox-cells = <2>;
1477 compatible = "fsl,imx95-mu-v2x";
1480 #mbox-cells = <2>;
1484 compatible = "fsl,imx95-mu-v2x";
1487 #mbox-cells = <2>;
1492 compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio";
1494 gpio-controller;
1495 #gpio-cells = <2>;
1498 interrupt-controller;
1499 #interrupt-cells = <2>;
1502 clock-names = "gpio", "port";
1503 gpio-ranges = <&scmi_iomuxc 0 112 16>;
1508 compatible = "fsl,imx95-mu-ele";
1511 #mbox-cells = <2>;
1516 compatible = "fsl,imx95-mu-ele";
1519 #mbox-cells = <2>;
1524 compatible = "fsl,imx95-mu-ele";
1527 #mbox-cells = <2>;
1532 compatible = "fsl,imx95-mu-ele";
1535 #mbox-cells = <2>;
1539 compatible = "fsl,imx95-mu-ele";
1542 #mbox-cells = <2>;
1547 compatible = "fsl,imx95-mu-ele";
1550 #mbox-cells = <2>;
1555 compatible = "fsl,aips-bus", "simple-bus";
1558 #address-cells = <1>;
1559 #size-cells = <1>;
1562 compatible = "arm,smmu-v3";
1568 interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
1569 #iommu-cells = <1>;
1575 compatible = "fsl,imx95-dwc3", "fsl,imx8mp-dwc3";
1580 clock-names = "hsio", "suspend";
1582 #address-cells = <2>;
1583 #size-cells = <2>;
1585 power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>;
1586 dma-ranges = <0x0 0x0 0x0 0x0 0x10 0x0>;
1595 clock-names = "bus_early", "ref", "suspend";
1598 phy-names = "usb2-phy", "usb3-phy";
1599 snps,gfladj-refclk-lpm-sel-quirk;
1600 snps,parkmode-disable-ss-quirk;
1606 compatible = "nxp,imx95-hsio-blk-ctl", "syscon";
1608 #clock-cells = <1>;
1610 power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>;
1614 compatible = "fsl,imx95-usb-phy", "fsl,imx8mp-usb-phy";
1618 clock-names = "phy";
1619 #phy-cells = <0>;
1620 power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>;
1625 compatible = "fsl,imx95-pcie";
1630 reg-names = "dbi", "config", "atu", "app";
1633 #address-cells = <3>;
1634 #size-cells = <2>;
1636 linux,pci-domain = <0>;
1637 bus-range = <0x00 0xff>;
1638 num-lanes = <1>;
1639 num-viewport = <8>;
1641 interrupt-names = "msi";
1642 #interrupt-cells = <1>;
1643 interrupt-map-mask = <0 0 0 0x7>;
1644 interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
1653 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref";
1654 assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
1657 assigned-clock-rates = <3600000000>, <100000000>, <10000000>;
1658 assigned-clock-parents = <0>, <0>,
1660 power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>;
1662 msi-map = <0x0 &its 0x10 0x1>,
1664 iommu-map = <0x000 &smmu 0x10 0x1>,
1666 iommu-map-mask = <0x1ff>;
1667 fsl,max-link-speed = <3>;
1671 pcie0_ep: pcie-ep@4c300000 {
1672 compatible = "fsl,imx95-pcie-ep";
1679 reg-names = "dbi","atu", "dbi2", "app", "dma", "addr_space";
1680 num-lanes = <1>;
1682 interrupt-names = "dma";
1687 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";
1688 assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
1691 assigned-clock-rates = <3600000000>, <100000000>, <10000000>;
1692 assigned-clock-parents = <0>, <0>,
1694 power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>;
1699 compatible = "fsl,imx95-pcie";
1704 reg-names = "dbi", "config", "atu", "app";
1707 #address-cells = <3>;
1708 #size-cells = <2>;
1710 linux,pci-domain = <1>;
1711 bus-range = <0x00 0xff>;
1712 num-lanes = <1>;
1713 num-viewport = <8>;
1715 interrupt-names = "msi";
1716 #interrupt-cells = <1>;
1717 interrupt-map-mask = <0 0 0 0x7>;
1718 interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
1727 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref";
1728 assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
1731 assigned-clock-rates = <3600000000>, <100000000>, <10000000>;
1732 assigned-clock-parents = <0>, <0>,
1734 power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>;
1736 msi-map = <0x0 &its 0x98 0x1>,
1738 msi-map-mask = <0x1ff>;
1740 iommu-map = <0x000 &smmu 0x18 0x1>,
1742 iommu-map-mask = <0x1ff>;
1743 fsl,max-link-speed = <3>;
1747 pcie1_ep: pcie-ep@4c380000 {
1748 compatible = "fsl,imx95-pcie-ep";
1755 reg-names = "dbi", "atu", "dbi2", "app", "dma", "addr_space";
1756 num-lanes = <1>;
1758 interrupt-names = "dma";
1763 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";
1764 assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
1767 assigned-clock-rates = <3600000000>, <100000000>, <10000000>;
1768 assigned-clock-parents = <0>, <0>,
1770 power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>;
1775 compatible = "nxp,imx95-netcmix-blk-ctrl", "syscon";
1777 #clock-cells = <1>;
1779 assigned-clocks = <&scmi_clk IMX95_CLK_BUSNETCMIX>;
1780 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;
1781 assigned-clock-rates = <133333333>;
1782 power-domains = <&scmi_devpd IMX95_PD_NETC>;
1787 compatible = "fsl,imx95-sai";
1793 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
1794 power-domains = <&scmi_devpd IMX95_PD_NETC>;
1796 dma-names = "rx", "tx";
1800 netc_blk_ctrl: system-controller@4cde0000 {
1801 compatible = "nxp,imx95-netc-blk-ctrl";
1805 reg-names = "ierb", "prb", "netcmix";
1806 #address-cells = <2>;
1807 #size-cells = <2>;
1809 power-domains = <&scmi_devpd IMX95_PD_NETC>;
1810 assigned-clocks = <&scmi_clk IMX95_CLK_ENET>,
1812 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD2>,
1814 assigned-clock-rates = <666666666>, <250000000>;
1816 clock-names = "ipg";
1820 compatible = "pci-host-ecam-generic";
1822 #address-cells = <3>;
1823 #size-cells = <2>;
1825 bus-range = <0x0 0x0>;
1826 msi-map = <0x0 &its 0x60 0x1>, //ENETC0 PF
1834 /* ENETC0~2 and Timer BAR0 - non-prefetchable memory */
1836 /* Timer BAR2 - prefetchable memory */
1838 /* ENETC0~2: VF0-1 BAR0 - non-prefetchable memory */
1840 /* ENETC0~2: VF0-1 BAR2 - prefetchable memory */
1847 clock-names = "ref";
1855 clock-names = "ref";
1872 compatible = "pci-host-ecam-generic";
1874 #address-cells = <3>;
1875 #size-cells = <2>;
1877 bus-range = <0x1 0x1>;
1878 /* EMDIO BAR0 - non-prefetchable memory */
1880 /* EMDIO BAR2 - prefetchable memory */
1886 #address-cells = <1>;
1887 #size-cells = <0>;
1893 ddr-pmu@4e090dc0 {
1894 compatible = "fsl,imx95-ddr-pmu", "fsl,imx93-ddr-pmu";