dts/exynos/exynosautov920.dtsi

1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/clock/samsung,exynosautov920.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/soc/samsung,exynos-usi.h>
15 	#address-cells = <2>;
16 	#size-cells = <1>;
18 	interrupt-parent = <&gic>;
31 	arm-pmu {
32 		compatible = "arm,cortex-a78-pmu";
37 		compatible = "fixed-clock";
38 		#clock-cells = <0>;
39 		clock-output-names = "oscclk";
43 		#address-cells = <2>;
44 		#size-cells = <0>;
46 		cpu-map {
89 			compatible = "arm,cortex-a78ae";
91 			enable-method = "psci";
92 			i-cache-size = <0x10000>;
93 			i-cache-line-size = <64>;
94 			i-cache-sets = <256>;
95 			d-cache-size = <0x10000>;
96 			d-cache-line-size = <64>;
97 			d-cache-sets = <256>;
98 			next-level-cache = <&l2_cache_cl0>;
103 			compatible = "arm,cortex-a78ae";
105 			enable-method = "psci";
106 			i-cache-size = <0x10000>;
107 			i-cache-line-size = <64>;
108 			i-cache-sets = <256>;
109 			d-cache-size = <0x10000>;
110 			d-cache-line-size = <64>;
111 			d-cache-sets = <256>;
112 			next-level-cache = <&l2_cache_cl0>;
117 			compatible = "arm,cortex-a78ae";
119 			enable-method = "psci";
120 			i-cache-size = <0x10000>;
121 			i-cache-line-size = <64>;
122 			i-cache-sets = <256>;
123 			d-cache-size = <0x10000>;
124 			d-cache-line-size = <64>;
125 			d-cache-sets = <256>;
126 			next-level-cache = <&l2_cache_cl0>;
131 			compatible = "arm,cortex-a78ae";
133 			enable-method = "psci";
134 			i-cache-size = <0x10000>;
135 			i-cache-line-size = <64>;
136 			i-cache-sets = <256>;
137 			d-cache-size = <0x10000>;
138 			d-cache-line-size = <64>;
139 			d-cache-sets = <256>;
140 			next-level-cache = <&l2_cache_cl0>;
145 			compatible = "arm,cortex-a78ae";
147 			enable-method = "psci";
148 			i-cache-size = <0x10000>;
149 			i-cache-line-size = <64>;
150 			i-cache-sets = <256>;
151 			d-cache-size = <0x10000>;
152 			d-cache-line-size = <64>;
153 			d-cache-sets = <256>;
154 			next-level-cache = <&l2_cache_cl1>;
159 			compatible = "arm,cortex-a78ae";
161 			enable-method = "psci";
162 			i-cache-size = <0x10000>;
163 			i-cache-line-size = <64>;
164 			i-cache-sets = <256>;
165 			d-cache-size = <0x10000>;
166 			d-cache-line-size = <64>;
167 			d-cache-sets = <256>;
168 			next-level-cache = <&l2_cache_cl1>;
173 			compatible = "arm,cortex-a78ae";
175 			enable-method = "psci";
176 			i-cache-size = <0x10000>;
177 			i-cache-line-size = <64>;
178 			i-cache-sets = <256>;
179 			d-cache-size = <0x10000>;
180 			d-cache-line-size = <64>;
181 			d-cache-sets = <256>;
182 			next-level-cache = <&l2_cache_cl1>;
187 			compatible = "arm,cortex-a78ae";
189 			enable-method = "psci";
190 			i-cache-size = <0x10000>;
191 			i-cache-line-size = <64>;
192 			i-cache-sets = <256>;
193 			d-cache-size = <0x10000>;
194 			d-cache-line-size = <64>;
195 			d-cache-sets = <256>;
196 			next-level-cache = <&l2_cache_cl1>;
201 			compatible = "arm,cortex-a78ae";
203 			enable-method = "psci";
204 			i-cache-size = <0x10000>;
205 			i-cache-line-size = <64>;
206 			i-cache-sets = <256>;
207 			d-cache-size = <0x10000>;
208 			d-cache-line-size = <64>;
209 			d-cache-sets = <256>;
210 			next-level-cache = <&l2_cache_cl2>;
215 			compatible = "arm,cortex-a78ae";
217 			enable-method = "psci";
218 			i-cache-size = <0x10000>;
219 			i-cache-line-size = <64>;
220 			i-cache-sets = <256>;
221 			d-cache-size = <0x10000>;
222 			d-cache-line-size = <64>;
223 			d-cache-sets = <256>;
224 			next-level-cache = <&l2_cache_cl2>;
227 		l2_cache_cl0: l2-cache0 {
228 			compatible = "cache";
229 			cache-level = <2>;
230 			cache-unified;
231 			cache-size = <0x40000>;
232 			cache-line-size = <64>;
233 			cache-sets = <512>;
234 			next-level-cache = <&l3_cache_cl0>;
237 		l2_cache_cl1: l2-cache1 {
238 			compatible = "cache";
239 			cache-level = <2>;
240 			cache-unified;
241 			cache-size = <0x40000>;
242 			cache-line-size = <64>;
243 			cache-sets = <512>;
244 			next-level-cache = <&l3_cache_cl1>;
247 		l2_cache_cl2: l2-cache2 {
248 			compatible = "cache";
249 			cache-level = <2>;
250 			cache-unified;
251 			cache-size = <0x40000>;
252 			cache-line-size = <64>;
253 			cache-sets = <512>;
254 			next-level-cache = <&l3_cache_cl2>;
257 		l3_cache_cl0: l3-cache0 {
258 			compatible = "cache";
259 			cache-level = <3>;
260 			cache-unified;
261 			cache-size = <0x200000>;/* 2MB L3 cache for cpu cluster-0 */
262 			cache-line-size = <64>;
263 			cache-sets = <2048>;
266 		l3_cache_cl1: l3-cache1 {
267 			compatible = "cache";
268 			cache-level = <3>;
269 			cache-unified;
270 			cache-size = <0x200000>;/* 2MB L3 cache for cpu cluster-1 */
271 			cache-line-size = <64>;
272 			cache-sets = <2048>;
275 		l3_cache_cl2: l3-cache2 {
276 			compatible = "cache";
277 			cache-level = <3>;
278 			cache-unified;
279 			cache-size = <0x100000>;/* 1MB L3 cache for cpu cluster-2 */
280 			cache-line-size = <64>;
281 			cache-sets = <1365>;
286 		compatible = "arm,psci-1.0";
291 		compatible = "simple-bus";
292 		#address-cells = <1>;
293 		#size-cells = <1>;
297 			compatible = "samsung,exynosautov920-chipid",
298 				     "samsung,exynos850-chipid";
302 		cmu_misc: clock-controller@10020000 {
303 			compatible = "samsung,exynosautov920-cmu-misc";
305 			#clock-cells = <1>;
309 			clock-names = "oscclk",
314 			compatible = "samsung,exynosautov920-wdt";
318 			clock-names = "watchdog", "watchdog_src";
319 			samsung,syscon-phandle = <&pmu_system_controller>;
320 			samsung,cluster-index = <0>;
324 			compatible = "samsung,exynosautov920-wdt";
328 			clock-names = "watchdog", "watchdog_src";
329 			samsung,syscon-phandle = <&pmu_system_controller>;
330 			samsung,cluster-index = <1>;
333 		gic: interrupt-controller@10400000 {
334 			compatible = "arm,gic-v3";
335 			#interrupt-cells = <3>;
336 			#address-cells = <0>;
337 			interrupt-controller;
343 		spdma0: dma-controller@10180000 {
348 			clock-names = "apb_pclk";
349 			#dma-cells = <1>;
352 		spdma1: dma-controller@10190000 {
357 			clock-names = "apb_pclk";
358 			#dma-cells = <1>;
361 		pdma0: dma-controller@101a0000 {
366 			clock-names = "apb_pclk";
367 			#dma-cells = <1>;
370 		pdma1: dma-controller@101b0000 {
375 			clock-names = "apb_pclk";
376 			#dma-cells = <1>;
379 		pdma2: dma-controller@101c0000 {
384 			clock-names = "apb_pclk";
385 			#dma-cells = <1>;
388 		pdma3: dma-controller@101d0000 {
393 			clock-names = "apb_pclk";
394 			#dma-cells = <1>;
397 		pdma4: dma-controller@101e0000 {
402 			clock-names = "apb_pclk";
403 			#dma-cells = <1>;
406 		cmu_peric0: clock-controller@10800000 {
407 			compatible = "samsung,exynosautov920-cmu-peric0";
409 			#clock-cells = <1>;
414 			clock-names = "oscclk",
420 			compatible = "samsung,exynosautov920-peric0-sysreg",
426 			compatible = "samsung,exynosautov920-pinctrl";
432 			compatible = "samsung,exynosautov920-usi",
433 				     "samsung,exynos850-usi";
437 			#address-cells = <1>;
438 			#size-cells = <1>;
442 			clock-names = "pclk", "ipclk";
446 				compatible = "samsung,exynosautov920-uart",
447 					     "samsung,exynos850-uart";
450 				pinctrl-names = "default";
451 				pinctrl-0 = <&uart0_bus>;
454 				clock-names = "uart", "clk_uart_baud0";
455 				samsung,uart-fifosize = <256>;
461 			compatible = "samsung,exynosautov920-pwm",
462 				     "samsung,exynos4210-pwm";
464 			samsung,pwm-outputs = <0>, <1>, <2>, <3>;
465 			#pwm-cells = <3>;
467 			clock-names = "timers";
471 		cmu_peric1: clock-controller@10c00000 {
472 			compatible = "samsung,exynosautov920-cmu-peric1";
474 			#clock-cells = <1>;
479 			clock-names = "oscclk",
485 			compatible = "samsung,exynosautov920-peric1-sysreg",
491 			compatible = "samsung,exynosautov920-pinctrl";
496 		cmu_top: clock-controller@11000000 {
497 			compatible = "samsung,exynosautov920-cmu-top";
499 			#clock-cells = <1>;
502 			clock-names = "oscclk";
506 			compatible = "samsung,exynosautov920-pinctrl";
509 			wakeup-interrupt-controller {
510 				compatible = "samsung,exynosautov920-wakeup-eint";
514 		pmu_system_controller: system-controller@11860000 {
515 			compatible = "samsung,exynosautov920-pmu",
516 				     "samsung,exynos7-pmu","syscon";
520 		cmu_hsi0: clock-controller@16000000 {
521 			compatible = "samsung,exynosautov920-cmu-hsi0";
523 			#clock-cells = <1>;
527 			clock-names = "oscclk",
532 			compatible = "samsung,exynosautov920-pinctrl";
537 		cmu_hsi1: clock-controller@16400000 {
538 			compatible = "samsung,exynosautov920-cmu-hsi1";
540 			#clock-cells = <1>;
546 			clock-names = "oscclk",
553 			compatible = "samsung,exynosautov920-pinctrl";
559 			compatible = "samsung,exynosautov920-pinctrl";
565 			compatible = "samsung,exynosautov920-pinctrl";
571 			compatible = "samsung,exynosautov920-ufs-phy";
573 			reg-names = "phy-pma";
575 			clock-names = "ref_clk";
576 			samsung,pmu-syscon = <&pmu_system_controller>;
577 			#phy-cells = <0>;
582 			compatible = "samsung,exynosautov920-pinctrl";
588 		compatible = "arm,armv8-timer";
597 #include "exynosautov920-pinctrl.dtsi"