dts/apple/t8015.dtsi

1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/apple-aic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/pinctrl/apple.h>
16 	interrupt-parent = <&aic>;
17 	#address-cells = <2>;
18 	#size-cells = <2>;
20 	clkref: clock-ref {
21 		compatible = "fixed-clock";
22 		#clock-cells = <0>;
23 		clock-frequency = <24000000>;
24 		clock-output-names = "clkref";
28 		#address-cells = <2>;
29 		#size-cells = <0>;
31 		cpu-map {
34 					cpu = <&cpu_e0>;
37 					cpu = <&cpu_e1>;
40 					cpu = <&cpu_e2>;
43 					cpu = <&cpu_e3>;
49 					cpu = <&cpu_p0>;
52 					cpu = <&cpu_p1>;
57 		cpu_e0: cpu@0 {
60 			cpu-release-addr = <0 0>; /* To be filled by loader */
61 			performance-domains = <&cpufreq_e>;
62 			operating-points-v2 = <&mistral_opp>;
63 			capacity-dmips-mhz = <633>;
64 			enable-method = "spin-table";
65 			device_type = "cpu";
68 		cpu_e1: cpu@1 {
71 			cpu-release-addr = <0 0>; /* To be filled by loader */
72 			performance-domains = <&cpufreq_e>;
73 			operating-points-v2 = <&mistral_opp>;
74 			capacity-dmips-mhz = <633>;
75 			enable-method = "spin-table";
76 			device_type = "cpu";
79 		cpu_e2: cpu@2 {
82 			cpu-release-addr = <0 0>; /* To be filled by loader */
83 			performance-domains = <&cpufreq_e>;
84 			operating-points-v2 = <&mistral_opp>;
85 			capacity-dmips-mhz = <633>;
86 			enable-method = "spin-table";
87 			device_type = "cpu";
90 		cpu_e3: cpu@3 {
93 			cpu-release-addr = <0 0>; /* To be filled by loader */
94 			performance-domains = <&cpufreq_e>;
95 			operating-points-v2 = <&mistral_opp>;
96 			capacity-dmips-mhz = <633>;
97 			enable-method = "spin-table";
98 			device_type = "cpu";
101 		cpu_p0: cpu@10004 {
104 			cpu-release-addr = <0 0>; /* To be filled by loader */
105 			performance-domains = <&cpufreq_p>;
106 			operating-points-v2 = <&monsoon_opp>;
107 			capacity-dmips-mhz = <1024>;
108 			enable-method = "spin-table";
109 			device_type = "cpu";
112 		cpu_p1: cpu@10005 {
115 			cpu-release-addr = <0 0>; /* To be filled by loader */
116 			performance-domains = <&cpufreq_p>;
117 			operating-points-v2 = <&monsoon_opp>;
118 			capacity-dmips-mhz = <1024>;
119 			enable-method = "spin-table";
120 			device_type = "cpu";
124 	mistral_opp: opp-table-0 {
125 		compatible = "operating-points-v2";
128 			opp-hz = /bits/ 64 <300000000>;
129 			opp-level = <1>;
130 			clock-latency-ns = <1800>;
133 			opp-hz = /bits/ 64 <453000000>;
134 			opp-level = <2>;
135 			clock-latency-ns = <140000>;
138 			opp-hz = /bits/ 64 <672000000>;
139 			opp-level = <3>;
140 			clock-latency-ns = <105000>;
143 			opp-hz = /bits/ 64 <972000000>;
144 			opp-level = <4>;
145 			clock-latency-ns = <115000>;
148 			opp-hz = /bits/ 64 <1272000000>;
149 			opp-level = <5>;
150 			clock-latency-ns = <125000>;
153 			opp-hz = /bits/ 64 <1572000000>;
154 			opp-level = <6>;
155 			clock-latency-ns = <135000>;
158 		/* Not available until CPU deep sleep is implemented */
160 			opp-hz = /bits/ 64 <1680000000>;
161 			opp-level = <7>;
162 			clock-latency-ns = <135000>;
163 			turbo-mode;
168 	monsoon_opp: opp-table-1 {
169 		compatible = "operating-points-v2";
172 			opp-hz = /bits/ 64 <300000000>;
173 			opp-level = <1>;
174 			clock-latency-ns = <1400>;
177 			opp-hz = /bits/ 64 <453000000>;
178 			opp-level = <2>;
179 			clock-latency-ns = <140000>;
182 			opp-hz = /bits/ 64 <853000000>;
183 			opp-level = <3>;
184 			clock-latency-ns = <110000>;
187 			opp-hz = /bits/ 64 <1332000000>;
188 			opp-level = <4>;
189 			clock-latency-ns = <110000>;
192 			opp-hz = /bits/ 64 <1812000000>;
193 			opp-level = <5>;
194 			clock-latency-ns = <125000>;
197 			opp-hz = /bits/ 64 <2064000000>;
198 			opp-level = <6>;
199 			clock-latency-ns = <130000>;
202 			opp-hz = /bits/ 64 <2304000000>;
203 			opp-level = <7>;
204 			clock-latency-ns = <140000>;
207 		/* Not available until CPU deep sleep is implemented */
209 			opp-hz = /bits/ 64 <2376000000>;
210 			opp-level = <8>;
211 			clock-latency-ns = <140000>;
212 			turbo-mode;
218 		compatible = "simple-bus";
219 		#address-cells = <2>;
220 		#size-cells = <2>;
221 		nonposted-mmio;
224 		cpufreq_e: performance-controller@208e20000 {
225 …compatible = "apple,t8015-cluster-cpufreq", "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq";
227 			#performance-domain-cells = <0>;
230 		cpufreq_p: performance-controller@208ea0000 {
231 …compatible = "apple,t8015-cluster-cpufreq", "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq";
233 			#performance-domain-cells = <0>;
237 			compatible = "apple,s5l-uart";
239 			reg-io-width = <4>;
240 			interrupt-parent = <&aic>;
242 			/* Use the bootloader-enabled clocks for now. */
244 			clock-names = "uart", "clk_uart_baud0";
245 			power-domains = <&ps_uart0>;
249 		aic: interrupt-controller@232100000 {
250 			compatible = "apple,t8015-aic", "apple,aic";
252 			#interrupt-cells = <3>;
253 			interrupt-controller;
254 			power-domains = <&ps_aic>;
257 		pmgr: power-management@232000000 {
258 			compatible = "apple,t8015-pmgr", "apple,pmgr", "syscon", "simple-mfd";
259 			#address-cells = <1>;
260 			#size-cells = <1>;
266 			compatible = "apple,t8015-dwi-bl", "apple,dwi-bl";
268 			power-domains = <&ps_dwi>;
273 			compatible = "apple,t8015-pinctrl", "apple,pinctrl";
275 			power-domains = <&ps_gpio>;
277 			gpio-controller;
278 			#gpio-cells = <2>;
279 			gpio-ranges = <&pinctrl_ap 0 0 223>;
282 			interrupt-controller;
283 			#interrupt-cells = <2>;
284 			interrupt-parent = <&aic>;
295 			compatible = "apple,t8015-pinctrl", "apple,pinctrl";
298 			gpio-controller;
299 			#gpio-cells = <2>;
300 			gpio-ranges = <&pinctrl_aop 0 0 49>;
303 			interrupt-controller;
304 			#interrupt-cells = <2>;
305 			interrupt-parent = <&aic>;
316 			compatible = "apple,t8015-pinctrl", "apple,pinctrl";
319 			gpio-controller;
320 			#gpio-cells = <2>;
321 			gpio-ranges = <&pinctrl_nub 0 0 8>;
324 			interrupt-controller;
325 			#interrupt-cells = <2>;
326 			interrupt-parent = <&aic>;
332 		pmgr_mini: power-management@235200000 {
333 			compatible = "apple,t8015-pmgr", "apple,pmgr", "syscon", "simple-mfd";
334 			#address-cells = <1>;
335 			#size-cells = <1>;
341 			compatible = "apple,t8015-wdt", "apple,wdt";
344 			interrupt-parent = <&aic>;
349 			compatible = "apple,t8015-pinctrl", "apple,pinctrl";
352 			gpio-controller;
353 			#gpio-cells = <2>;
354 			gpio-ranges = <&pinctrl_smc 0 0 6>;
357 			interrupt-controller;
358 			#interrupt-cells = <2>;
359 			interrupt-parent = <&aic>;
376 		compatible = "arm,armv8-timer";
377 		interrupt-parent = <&aic>;
378 		interrupt-names = "phys", "virt";
385 #include "t8015-pmgr.dtsi"