bindings/spi/qcom%2Cspi-qpic-snand.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/qcom,spi-qpic-snand.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm QPIC NAND controller
10   - Md sadre Alam <quic_mdalam@quicinc.com>
13   The QCOM QPIC-SPI-NAND flash controller is an extended version of
14   the QCOM QPIC NAND flash controller. It can work both in serial
15   and parallel mode. It supports typical SPI-NAND page cache
16   operations in single, dual or quad IO mode with pipelined ECC
17   encoding/decoding using the QPIC ECC HW engine.
20   - $ref: /schemas/spi/spi-controller.yaml#
25       - qcom,ipq9574-snand
33   clock-names:
35       - const: core
36       - const: aon
37       - const: iom
41       - description: tx DMA channel
42       - description: rx DMA channel
43       - description: cmd DMA channel
45   dma-names:
47       - const: tx
48       - const: rx
49       - const: cmd
52   - compatible
53   - reg
54   - clocks
55   - clock-names
60   - |
61     #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
63         compatible = "qcom,ipq9574-snand";
69         clock-names = "core", "aon", "iom";
71         #address-cells = <1>;
72         #size-cells = <0>;
75             compatible = "spi-nand";
77             #address-cells = <1>;
78             #size-cells = <1>;
79             nand-ecc-engine = <&qpic_nand>;
80             nand-ecc-strength = <4>;
81             nand-ecc-step-size = <512>;