Lines Matching +full:rk3568 +full:- +full:pipe +full:- +full:phy +full:- +full:grf
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-rockchip-naneng-combphy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip SoC Naneng Combo Phy
10 - Heiko Stuebner <heiko@sntech.de>
15 - rockchip,rk3562-naneng-combphy
16 - rockchip,rk3568-naneng-combphy
17 - rockchip,rk3576-naneng-combphy
18 - rockchip,rk3588-naneng-combphy
25 - description: reference clock
26 - description: apb clock
27 - description: pipe clock
29 clock-names:
31 - const: ref
32 - const: apb
33 - const: pipe
39 reset-names:
42 - const: phy
43 - const: apb
45 rockchip,enable-ssc:
51 rockchip,ext-refclk:
61 By default the internal clock is selected. The PCIe PHY provides a 100MHz
64 reference clock needs to be provided to the PCIe PHY.
66 rockchip,pipe-grf:
69 Some additional phy settings are accessed through GRF regs.
71 rockchip,pipe-phy-grf:
74 Some additional pipe settings are accessed through GRF regs.
76 "#phy-cells":
80 - compatible
81 - reg
82 - clocks
83 - clock-names
84 - resets
85 - rockchip,pipe-grf
86 - rockchip,pipe-phy-grf
87 - "#phy-cells"
90 - if:
94 const: rockchip,rk3568-naneng-combphy
99 reset-names:
101 - if:
105 const: rockchip,rk3588-naneng-combphy
110 reset-names:
113 - reset-names
118 - |
119 #include <dt-bindings/clock/rk3568-cru.h>
122 compatible = "rockchip,rk3568-pipe-grf", "syscon";
127 compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
131 combphy0: phy@fe820000 {
132 compatible = "rockchip,rk3568-naneng-combphy";
137 clock-names = "ref", "apb", "pipe";
138 assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>;
139 assigned-clock-rates = <100000000>;
141 rockchip,pipe-grf = <&pipegrf>;
142 rockchip,pipe-phy-grf = <&pipe_phy_grf0>;
143 #phy-cells = <1>;