Lines Matching +full:next +full:- +full:level +full:- +full:cache
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/cpufreq/cpufreq-qcom-hw.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
21 - description: v1 of CPUFREQ HW
23 - enum:
24 - qcom,qcm2290-cpufreq-hw
25 - qcom,sc7180-cpufreq-hw
26 - qcom,sc8180x-cpufreq-hw
27 - qcom,sdm670-cpufreq-hw
28 - qcom,sdm845-cpufreq-hw
29 - qcom,sm6115-cpufreq-hw
30 - qcom,sm6350-cpufreq-hw
31 - qcom,sm8150-cpufreq-hw
32 - const: qcom,cpufreq-hw
34 - description: v2 of CPUFREQ HW (EPSS)
36 - enum:
37 - qcom,qcs8300-cpufreq-epss
38 - qcom,qdu1000-cpufreq-epss
39 - qcom,sa8255p-cpufreq-epss
40 - qcom,sa8775p-cpufreq-epss
41 - qcom,sar2130p-cpufreq-epss
42 - qcom,sc7280-cpufreq-epss
43 - qcom,sc8280xp-cpufreq-epss
44 - qcom,sdx75-cpufreq-epss
45 - qcom,sm4450-cpufreq-epss
46 - qcom,sm6375-cpufreq-epss
47 - qcom,sm8250-cpufreq-epss
48 - qcom,sm8350-cpufreq-epss
49 - qcom,sm8450-cpufreq-epss
50 - qcom,sm8550-cpufreq-epss
51 - qcom,sm8650-cpufreq-epss
52 - const: qcom,cpufreq-epss
57 - description: Frequency domain 0 register region
58 - description: Frequency domain 1 register region
59 - description: Frequency domain 2 register region
60 - description: Frequency domain 3 register region
62 reg-names:
65 - const: freq-domain0
66 - const: freq-domain1
67 - const: freq-domain2
68 - const: freq-domain3
72 - description: XO Clock
73 - description: GPLL0 Clock
75 clock-names:
77 - const: xo
78 - const: alternate
84 interrupt-names:
87 - const: dcvsh-irq-0
88 - const: dcvsh-irq-1
89 - const: dcvsh-irq-2
90 - const: dcvsh-irq-3
92 '#freq-domain-cells':
95 '#clock-cells':
99 - compatible
100 - reg
101 - clocks
102 - clock-names
103 - '#freq-domain-cells'
108 - if:
113 - qcom,qcm2290-cpufreq-hw
114 - qcom,sar2130p-cpufreq-epss
115 - qcom,sdx75-cpufreq-epss
121 reg-names:
127 interrupt-names:
130 - if:
135 - qcom,qdu1000-cpufreq-epss
136 - qcom,sa8255p-cpufreq-epss
137 - qcom,sa8775p-cpufreq-epss
138 - qcom,sc7180-cpufreq-hw
139 - qcom,sc8180x-cpufreq-hw
140 - qcom,sc8280xp-cpufreq-epss
141 - qcom,sdm670-cpufreq-hw
142 - qcom,sdm845-cpufreq-hw
143 - qcom,sm4450-cpufreq-epss
144 - qcom,sm6115-cpufreq-hw
145 - qcom,sm6350-cpufreq-hw
146 - qcom,sm6375-cpufreq-epss
153 reg-names:
161 interrupt-names:
165 - if:
170 - qcom,qcs8300-cpufreq-epss
171 - qcom,sc7280-cpufreq-epss
172 - qcom,sm8250-cpufreq-epss
173 - qcom,sm8350-cpufreq-epss
174 - qcom,sm8450-cpufreq-epss
175 - qcom,sm8550-cpufreq-epss
182 reg-names:
190 interrupt-names:
194 - if:
199 - qcom,sm8150-cpufreq-hw
206 reg-names:
215 interrupt-names:
219 - if:
224 - qcom,sm8650-cpufreq-epss
231 reg-names:
239 interrupt-names:
244 - |
245 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
246 #include <dt-bindings/clock/qcom,rpmh.h>
248 // Example 1: Dual-cluster, Quad-core per cluster. CPUs within a cluster
251 #address-cells = <2>;
252 #size-cells = <0>;
258 enable-method = "psci";
259 next-level-cache = <&L2_0>;
260 qcom,freq-domain = <&cpufreq_hw 0>;
262 L2_0: l2-cache {
263 compatible = "cache";
264 cache-unified;
265 cache-level = <2>;
266 next-level-cache = <&L3_0>;
267 L3_0: l3-cache {
268 compatible = "cache";
269 cache-unified;
270 cache-level = <3>;
279 enable-method = "psci";
280 next-level-cache = <&L2_100>;
281 qcom,freq-domain = <&cpufreq_hw 0>;
283 L2_100: l2-cache {
284 compatible = "cache";
285 cache-unified;
286 cache-level = <2>;
287 next-level-cache = <&L3_0>;
295 enable-method = "psci";
296 next-level-cache = <&L2_200>;
297 qcom,freq-domain = <&cpufreq_hw 0>;
299 L2_200: l2-cache {
300 compatible = "cache";
301 cache-unified;
302 cache-level = <2>;
303 next-level-cache = <&L3_0>;
311 enable-method = "psci";
312 next-level-cache = <&L2_300>;
313 qcom,freq-domain = <&cpufreq_hw 0>;
315 L2_300: l2-cache {
316 compatible = "cache";
317 cache-unified;
318 cache-level = <2>;
319 next-level-cache = <&L3_0>;
327 enable-method = "psci";
328 next-level-cache = <&L2_400>;
329 qcom,freq-domain = <&cpufreq_hw 1>;
331 L2_400: l2-cache {
332 compatible = "cache";
333 cache-unified;
334 cache-level = <2>;
335 next-level-cache = <&L3_0>;
343 enable-method = "psci";
344 next-level-cache = <&L2_500>;
345 qcom,freq-domain = <&cpufreq_hw 1>;
347 L2_500: l2-cache {
348 compatible = "cache";
349 cache-unified;
350 cache-level = <2>;
351 next-level-cache = <&L3_0>;
359 enable-method = "psci";
360 next-level-cache = <&L2_600>;
361 qcom,freq-domain = <&cpufreq_hw 1>;
363 L2_600: l2-cache {
364 compatible = "cache";
365 cache-unified;
366 cache-level = <2>;
367 next-level-cache = <&L3_0>;
375 enable-method = "psci";
376 next-level-cache = <&L2_700>;
377 qcom,freq-domain = <&cpufreq_hw 1>;
379 L2_700: l2-cache {
380 compatible = "cache";
381 cache-unified;
382 cache-level = <2>;
383 next-level-cache = <&L3_0>;
389 #address-cells = <1>;
390 #size-cells = <1>;
393 compatible = "qcom,sdm845-cpufreq-hw", "qcom,cpufreq-hw";
395 reg-names = "freq-domain0", "freq-domain1";
398 clock-names = "xo", "alternate";
400 #freq-domain-cells = <1>;
401 #clock-cells = <1>;