70 /* Tuning bits */
101 /* NOTE: the minimum valid tuning start tap for mx6sl is 1 */
147 /* The IP supports manual tuning process */
149 /* The IP supports standard tuning process */
567 				/* the std tuning bits is in ACMD12_ERR for imx6sl */  in esdhc_readw_le()
693 				 * tuning, when send tuning command, usdhc will  in esdhc_writew_le()
816 				 * the tuning bits should be kept during reset  in esdhc_writeb_le()
979 	 * DDR50, normally does not require tuning for DDR50 mode.  in usdhc_execute_tuning()
993 	/* FIXME: delay a bit for card to be ready for next tuning due to errors */  in esdhc_prepare_tuning()
996 	/* IC suggest to reset USDHC before every tuning command */  in esdhc_prepare_tuning()
1002 		"warning! RESET_ALL never complete before sending tuning command\n");  in esdhc_prepare_tuning()
1010 		"tuning with delay 0x%x ESDHC_TUNE_CTRL_STATUS 0x%x\n",  in esdhc_prepare_tuning()
1028 	/* find the mininum delay first which can pass tuning */  in esdhc_executing_tuning()
1037 	/* find the maxinum delay which can not pass tuning */  in esdhc_executing_tuning()
1054 	dev_dbg(mmc_dev(host->mmc), "tuning %s at 0x%x ret %d\n",  in esdhc_executing_tuning()
1161 	/* Reset the tuning circuit */  in esdhc_reset_tuning()
1370 			/* Disable the CMD CRC check for tuning, if not, need to  in sdhci_esdhc_imx_hwinit()
1371 			 * add some delay after every tuning command, because  in sdhci_esdhc_imx_hwinit()
1372 			 * hardware standard tuning logic will directly go to next  in sdhci_esdhc_imx_hwinit()
1374 			 * the card side to finally send out the tuning data, trigger  in sdhci_esdhc_imx_hwinit()
1376 			 * the next tuning command some eMMC card will stuck, can't  in sdhci_esdhc_imx_hwinit()
1377 			 * response, block the tuning procedure or the first command  in sdhci_esdhc_imx_hwinit()
1378 			 * after the whole tuning procedure always can't get any response.  in sdhci_esdhc_imx_hwinit()
1386 			 * the manual tuning can work.  in sdhci_esdhc_imx_hwinit()
1420 	 * the case after tuning, so ensure the buffer is drained.  in esdhc_cqe_enable()
1493 	of_property_read_u32(np, "fsl,tuning-step", &boarddata->tuning_step);  in sdhci_esdhc_imx_probe_dt()
1494 	of_property_read_u32(np, "fsl,tuning-start-tap",  in sdhci_esdhc_imx_probe_dt()
1669 		/* clear tuning bits in case ROM has set it already */  in sdhci_esdhc_imx_probe()