Lines Matching +full:cs +full:- +full:x
2 * Copyright © 2008-2010 Intel Corporation
43 * set-context and then emitting the batch.
53 if (engine->class == RENDER_CLASS) { in set_hwstam()
54 if (INTEL_GEN(engine->i915) >= 6) in set_hwstam()
68 if (INTEL_GEN(engine->i915) >= 4) in set_hws_pga()
71 intel_uncore_write(engine->uncore, HWS_PGA, addr); in set_hws_pga()
76 struct drm_i915_gem_object *obj = engine->status_page.vma->obj; in status_page()
79 return sg_page(obj->mm.pages->sgl); in status_page()
96 if (IS_GEN(engine->i915, 7)) { in set_hwsp()
97 switch (engine->id) { in set_hwsp()
103 GEM_BUG_ON(engine->id); in set_hwsp()
118 } else if (IS_GEN(engine->i915, 6)) { in set_hwsp()
119 hwsp = RING_HWS_PGA_GEN6(engine->mmio_base); in set_hwsp()
121 hwsp = RING_HWS_PGA(engine->mmio_base); in set_hwsp()
124 intel_uncore_write(engine->uncore, hwsp, offset); in set_hwsp()
125 intel_uncore_posting_read(engine->uncore, hwsp); in set_hwsp()
130 struct drm_i915_private *dev_priv = engine->i915; in flush_cs_tlb()
136 drm_WARN_ON(&dev_priv->drm, in flush_cs_tlb()
142 if (intel_wait_for_register(engine->uncore, in flush_cs_tlb()
143 RING_INSTPM(engine->mmio_base), in flush_cs_tlb()
146 drm_err(&dev_priv->drm, in flush_cs_tlb()
148 engine->name); in flush_cs_tlb()
153 set_hwsp(engine, i915_ggtt_offset(engine->status_page.vma)); in ring_setup_status_page()
161 struct drm_i915_private *dev_priv = engine->i915; in stop_ring()
166 if (intel_wait_for_register(engine->uncore, in stop_ring()
167 RING_MI_MODE(engine->mmio_base), in stop_ring()
171 drm_err(&dev_priv->drm, in stop_ring()
173 engine->name); in stop_ring()
200 vm = &i915_vm_to_ggtt(vm)->alias->vm; in vm_alias()
207 return to_gen6_ppgtt(i915_vm_to_ppgtt(vm))->pp_dir; in pp_dir()
212 struct i915_address_space *vm = vm_alias(engine->gt->vm); in set_pp_dir()
222 struct drm_i915_private *dev_priv = engine->i915; in xcs_resume()
223 struct intel_ring *ring = engine->legacy.ring; in xcs_resume()
226 ENGINE_TRACE(engine, "ring:{HEAD:%04x, TAIL:%04x}\n", in xcs_resume()
227 ring->head, ring->tail); in xcs_resume()
229 intel_uncore_forcewake_get(engine->uncore, FORCEWAKE_ALL); in xcs_resume()
234 drm_dbg(&dev_priv->drm, "%s head not reset to zero " in xcs_resume()
235 "ctl %08x head %08x tail %08x start %08x\n", in xcs_resume()
236 engine->name, in xcs_resume()
243 drm_err(&dev_priv->drm, in xcs_resume()
245 "ctl %08x head %08x tail %08x start %08x\n", in xcs_resume()
246 engine->name, in xcs_resume()
251 ret = -EIO; in xcs_resume()
261 intel_breadcrumbs_reset(engine->breadcrumbs); in xcs_resume()
272 ENGINE_WRITE(engine, RING_START, i915_ggtt_offset(ring->vma)); in xcs_resume()
275 GEM_BUG_ON(!intel_ring_offset_valid(ring, ring->head)); in xcs_resume()
276 GEM_BUG_ON(!intel_ring_offset_valid(ring, ring->tail)); in xcs_resume()
282 ENGINE_WRITE(engine, RING_HEAD, ring->head); in xcs_resume()
283 ENGINE_WRITE(engine, RING_TAIL, ring->head); in xcs_resume()
286 ENGINE_WRITE(engine, RING_CTL, RING_CTL_SIZE(ring->size) | RING_VALID); in xcs_resume()
289 if (intel_wait_for_register(engine->uncore, in xcs_resume()
290 RING_CTL(engine->mmio_base), in xcs_resume()
293 drm_err(&dev_priv->drm, "%s initialization failed " in xcs_resume()
294 "ctl %08x (valid? %d) head %08x [%08x] tail %08x [%08x] start %08x [expected %08x]\n", in xcs_resume()
295 engine->name, in xcs_resume()
298 ENGINE_READ(engine, RING_HEAD), ring->head, in xcs_resume()
299 ENGINE_READ(engine, RING_TAIL), ring->tail, in xcs_resume()
301 i915_ggtt_offset(ring->vma)); in xcs_resume()
302 ret = -EIO; in xcs_resume()
311 if (ring->tail != ring->head) { in xcs_resume()
312 ENGINE_WRITE(engine, RING_TAIL, ring->tail); in xcs_resume()
319 intel_uncore_forcewake_put(engine->uncore, FORCEWAKE_ALL); in xcs_resume()
326 struct intel_uncore *uncore = engine->uncore; in reset_prepare()
327 const u32 base = engine->mmio_base; in reset_prepare()
362 ENGINE_TRACE(engine, "ring head [%x] not parked\n", in reset_prepare()
373 spin_lock_irqsave(&engine->active.lock, flags); in reset_rewind()
374 list_for_each_entry(pos, &engine->active.requests, sched.link) { in reset_rewind()
421 GEM_BUG_ON(rq->ring != engine->legacy.ring); in reset_rewind()
422 head = rq->head; in reset_rewind()
424 head = engine->legacy.ring->tail; in reset_rewind()
426 engine->legacy.ring->head = intel_ring_wrap(engine->legacy.ring, head); in reset_rewind()
428 spin_unlock_irqrestore(&engine->active.lock, flags); in reset_rewind()
440 spin_lock_irqsave(&engine->active.lock, flags); in reset_cancel()
443 list_for_each_entry(request, &engine->active.requests, sched.link) { in reset_cancel()
444 i915_request_set_error_once(request, -EIO); in reset_cancel()
450 spin_unlock_irqrestore(&engine->active.lock, flags); in reset_cancel()
458 ENGINE_WRITE(request->engine, RING_TAIL, in i9xx_submit_request()
459 intel_ring_set_tail(request->ring, request->tail)); in i9xx_submit_request()
464 i915_vma_put(ce->state); in __ring_context_fini()
473 if (ce->state) in ring_context_destroy()
487 vm = vm_alias(ce->vm); in ring_context_pre_pin()
498 vm = vm_alias(ce->vm); in __context_unpin_ppgtt()
515 struct drm_i915_private *i915 = engine->i915; in alloc_context_vma()
520 obj = i915_gem_object_create_shmem(i915, engine->context_size); in alloc_context_vma()
532 * Snooping is required on non-llc platforms in execlist in alloc_context_vma()
542 if (engine->default_state) { in alloc_context_vma()
551 shmem_read(engine->default_state, 0, in alloc_context_vma()
552 vaddr, engine->context_size); in alloc_context_vma()
558 vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL); in alloc_context_vma()
573 struct intel_engine_cs *engine = ce->engine; in ring_context_alloc()
576 GEM_BUG_ON(!engine->legacy.ring); in ring_context_alloc()
577 ce->ring = engine->legacy.ring; in ring_context_alloc()
578 ce->timeline = intel_timeline_get(engine->legacy.timeline); in ring_context_alloc()
580 GEM_BUG_ON(ce->state); in ring_context_alloc()
581 if (engine->context_size) { in ring_context_alloc()
588 ce->state = vma; in ring_context_alloc()
589 if (engine->default_state) in ring_context_alloc()
590 __set_bit(CONTEXT_VALID_BIT, &ce->flags); in ring_context_alloc()
603 intel_ring_reset(ce->ring, ce->ring->emit); in ring_context_reset()
625 const struct intel_engine_cs * const engine = rq->engine; in load_pd_dir()
626 u32 *cs; in load_pd_dir() local
628 cs = intel_ring_begin(rq, 12); in load_pd_dir()
629 if (IS_ERR(cs)) in load_pd_dir()
630 return PTR_ERR(cs); in load_pd_dir()
632 *cs++ = MI_LOAD_REGISTER_IMM(1); in load_pd_dir()
633 *cs++ = i915_mmio_reg_offset(RING_PP_DIR_DCLV(engine->mmio_base)); in load_pd_dir()
634 *cs++ = valid; in load_pd_dir()
636 *cs++ = MI_LOAD_REGISTER_IMM(1); in load_pd_dir()
637 *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base)); in load_pd_dir()
638 *cs++ = pp_dir(vm); in load_pd_dir()
641 *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT; in load_pd_dir()
642 *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base)); in load_pd_dir()
643 *cs++ = intel_gt_scratch_offset(engine->gt, in load_pd_dir()
646 *cs++ = MI_LOAD_REGISTER_IMM(1); in load_pd_dir()
647 *cs++ = i915_mmio_reg_offset(RING_INSTPM(engine->mmio_base)); in load_pd_dir()
648 *cs++ = _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE); in load_pd_dir()
650 intel_ring_advance(rq, cs); in load_pd_dir()
652 return rq->engine->emit_flush(rq, EMIT_FLUSH); in load_pd_dir()
659 struct intel_engine_cs *engine = rq->engine; in mi_set_context()
660 struct drm_i915_private *i915 = engine->i915; in mi_set_context()
663 IS_HASWELL(i915) ? engine->gt->info.num_engines - 1 : 0; in mi_set_context()
666 u32 *cs; in mi_set_context() local
680 cs = intel_ring_begin(rq, len); in mi_set_context()
681 if (IS_ERR(cs)) in mi_set_context()
682 return PTR_ERR(cs); in mi_set_context()
686 *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE; in mi_set_context()
690 *cs++ = MI_LOAD_REGISTER_IMM(num_engines); in mi_set_context()
691 for_each_engine(signaller, engine->gt, id) { in mi_set_context()
695 *cs++ = i915_mmio_reg_offset( in mi_set_context()
696 RING_PSMI_CTL(signaller->mmio_base)); in mi_set_context()
697 *cs++ = _MASKED_BIT_ENABLE( in mi_set_context()
703 * This w/a is only listed for pre-production ilk a/b steppings, in mi_set_context()
706 * this should never take effect and so be a no-op! in mi_set_context()
708 *cs++ = MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN; in mi_set_context()
724 *cs++ = MI_SET_CONTEXT; in mi_set_context()
725 *cs++ = i915_ggtt_offset(engine->kernel_context->state) | in mi_set_context()
730 *cs++ = MI_NOOP; in mi_set_context()
731 *cs++ = MI_SET_CONTEXT; in mi_set_context()
732 *cs++ = i915_ggtt_offset(ce->state) | flags; in mi_set_context()
737 *cs++ = MI_NOOP; in mi_set_context()
744 *cs++ = MI_LOAD_REGISTER_IMM(num_engines); in mi_set_context()
745 for_each_engine(signaller, engine->gt, id) { in mi_set_context()
749 last_reg = RING_PSMI_CTL(signaller->mmio_base); in mi_set_context()
750 *cs++ = i915_mmio_reg_offset(last_reg); in mi_set_context()
751 *cs++ = _MASKED_BIT_DISABLE( in mi_set_context()
756 *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT; in mi_set_context()
757 *cs++ = i915_mmio_reg_offset(last_reg); in mi_set_context()
758 *cs++ = intel_gt_scratch_offset(engine->gt, in mi_set_context()
760 *cs++ = MI_NOOP; in mi_set_context()
762 *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE; in mi_set_context()
764 *cs++ = MI_SUSPEND_FLUSH; in mi_set_context()
767 intel_ring_advance(rq, cs); in mi_set_context()
774 u32 *cs, *remap_info = rq->engine->i915->l3_parity.remap_info[slice]; in remap_l3_slice() local
780 cs = intel_ring_begin(rq, GEN7_L3LOG_SIZE/4 * 2 + 2); in remap_l3_slice()
781 if (IS_ERR(cs)) in remap_l3_slice()
782 return PTR_ERR(cs); in remap_l3_slice()
789 *cs++ = MI_LOAD_REGISTER_IMM(GEN7_L3LOG_SIZE/4); in remap_l3_slice()
791 *cs++ = i915_mmio_reg_offset(GEN7_L3LOG(slice, i)); in remap_l3_slice()
792 *cs++ = remap_info[i]; in remap_l3_slice()
794 *cs++ = MI_NOOP; in remap_l3_slice()
795 intel_ring_advance(rq, cs); in remap_l3_slice()
805 if (!ctx || !ctx->remap_slice) in remap_l3()
809 if (!(ctx->remap_slice & BIT(i))) in remap_l3()
817 ctx->remap_slice = 0; in remap_l3()
828 ret = rq->engine->emit_flush(rq, EMIT_FLUSH); in switch_mm()
833 * Not only do we need a full barrier (post-sync write) after in switch_mm()
837 * post-sync op, this extra pass appears vital before a in switch_mm()
844 return rq->engine->emit_flush(rq, EMIT_INVALIDATE); in switch_mm()
849 struct intel_engine_cs *engine = rq->engine; in clear_residuals()
852 ret = switch_mm(rq, vm_alias(engine->kernel_context->vm)); in clear_residuals()
856 if (engine->kernel_context->state) { in clear_residuals()
858 engine->kernel_context, in clear_residuals()
864 ret = engine->emit_bb_start(rq, in clear_residuals()
865 engine->wa_ctx.vma->node.start, 0, in clear_residuals()
870 ret = engine->emit_flush(rq, EMIT_FLUSH); in clear_residuals()
875 return engine->emit_flush(rq, EMIT_INVALIDATE); in clear_residuals()
880 struct intel_engine_cs *engine = rq->engine; in switch_context()
881 struct intel_context *ce = rq->context; in switch_context()
885 GEM_BUG_ON(HAS_EXECLISTS(engine->i915)); in switch_context()
887 if (engine->wa_ctx.vma && ce != engine->kernel_context) { in switch_context()
888 if (engine->wa_ctx.vma->private != ce) { in switch_context()
893 residuals = &engine->wa_ctx.vma->private; in switch_context()
897 ret = switch_mm(rq, vm_alias(ce->vm)); in switch_context()
901 if (ce->state) { in switch_context()
904 GEM_BUG_ON(engine->id != RCS0); in switch_context()
911 if (test_bit(CONTEXT_VALID_BIT, &ce->flags)) in switch_context()
946 GEM_BUG_ON(!intel_context_is_pinned(request->context)); in ring_request_alloc()
947 GEM_BUG_ON(i915_request_timeline(request)->has_initial_breadcrumb); in ring_request_alloc()
951 * we start building the request - in which case we will just in ring_request_alloc()
954 request->reserved_space += LEGACY_REQUEST_SIZE; in ring_request_alloc()
957 ret = request->engine->emit_flush(request, EMIT_INVALIDATE); in ring_request_alloc()
965 request->reserved_space -= LEGACY_REQUEST_SIZE; in ring_request_alloc()
971 struct intel_uncore *uncore = request->engine->uncore; in gen6_bsd_submit_request()
992 drm_err(&uncore->i915->drm, in gen6_bsd_submit_request()
1009 engine->submit_request = i9xx_submit_request; in i9xx_set_default_submission()
1011 engine->park = NULL; in i9xx_set_default_submission()
1012 engine->unpark = NULL; in i9xx_set_default_submission()
1018 engine->submit_request = gen6_bsd_submit_request; in gen6_bsd_set_default_submission()
1023 struct drm_i915_private *dev_priv = engine->i915; in ring_release()
1025 drm_WARN_ON(&dev_priv->drm, INTEL_GEN(dev_priv) > 2 && in ring_release()
1030 if (engine->wa_ctx.vma) { in ring_release()
1031 intel_context_put(engine->wa_ctx.vma->private); in ring_release()
1032 i915_vma_unpin_and_release(&engine->wa_ctx.vma, 0); in ring_release()
1035 intel_ring_unpin(engine->legacy.ring); in ring_release()
1036 intel_ring_put(engine->legacy.ring); in ring_release()
1038 intel_timeline_unpin(engine->legacy.timeline); in ring_release()
1039 intel_timeline_put(engine->legacy.timeline); in ring_release()
1044 struct drm_i915_private *i915 = engine->i915; in setup_irq()
1047 engine->irq_enable = gen6_irq_enable; in setup_irq()
1048 engine->irq_disable = gen6_irq_disable; in setup_irq()
1050 engine->irq_enable = gen5_irq_enable; in setup_irq()
1051 engine->irq_disable = gen5_irq_disable; in setup_irq()
1053 engine->irq_enable = gen3_irq_enable; in setup_irq()
1054 engine->irq_disable = gen3_irq_disable; in setup_irq()
1056 engine->irq_enable = gen2_irq_enable; in setup_irq()
1057 engine->irq_disable = gen2_irq_disable; in setup_irq()
1063 struct drm_i915_private *i915 = engine->i915; in setup_common()
1070 engine->resume = xcs_resume; in setup_common()
1071 engine->reset.prepare = reset_prepare; in setup_common()
1072 engine->reset.rewind = reset_rewind; in setup_common()
1073 engine->reset.cancel = reset_cancel; in setup_common()
1074 engine->reset.finish = reset_finish; in setup_common()
1076 engine->cops = &ring_context_ops; in setup_common()
1077 engine->request_alloc = ring_request_alloc; in setup_common()
1082 * engine->emit_init_breadcrumb(). in setup_common()
1084 engine->emit_fini_breadcrumb = gen3_emit_breadcrumb; in setup_common()
1086 engine->emit_fini_breadcrumb = gen5_emit_breadcrumb; in setup_common()
1088 engine->set_default_submission = i9xx_set_default_submission; in setup_common()
1091 engine->emit_bb_start = gen6_emit_bb_start; in setup_common()
1093 engine->emit_bb_start = gen4_emit_bb_start; in setup_common()
1095 engine->emit_bb_start = i830_emit_bb_start; in setup_common()
1097 engine->emit_bb_start = gen3_emit_bb_start; in setup_common()
1102 struct drm_i915_private *i915 = engine->i915; in setup_rcs()
1105 engine->irq_keep_mask = GT_RENDER_L3_PARITY_ERROR_INTERRUPT; in setup_rcs()
1107 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT; in setup_rcs()
1110 engine->emit_flush = gen7_emit_flush_rcs; in setup_rcs()
1111 engine->emit_fini_breadcrumb = gen7_emit_breadcrumb_rcs; in setup_rcs()
1113 engine->emit_flush = gen6_emit_flush_rcs; in setup_rcs()
1114 engine->emit_fini_breadcrumb = gen6_emit_breadcrumb_rcs; in setup_rcs()
1116 engine->emit_flush = gen4_emit_flush_rcs; in setup_rcs()
1119 engine->emit_flush = gen2_emit_flush; in setup_rcs()
1121 engine->emit_flush = gen4_emit_flush_rcs; in setup_rcs()
1122 engine->irq_enable_mask = I915_USER_INTERRUPT; in setup_rcs()
1126 engine->emit_bb_start = hsw_emit_bb_start; in setup_rcs()
1131 struct drm_i915_private *i915 = engine->i915; in setup_vcs()
1136 engine->set_default_submission = gen6_bsd_set_default_submission; in setup_vcs()
1137 engine->emit_flush = gen6_emit_flush_vcs; in setup_vcs()
1138 engine->irq_enable_mask = GT_BSD_USER_INTERRUPT; in setup_vcs()
1141 engine->emit_fini_breadcrumb = gen6_emit_breadcrumb_xcs; in setup_vcs()
1143 engine->emit_fini_breadcrumb = gen7_emit_breadcrumb_xcs; in setup_vcs()
1145 engine->emit_flush = gen4_emit_flush_vcs; in setup_vcs()
1147 engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT; in setup_vcs()
1149 engine->irq_enable_mask = I915_BSD_USER_INTERRUPT; in setup_vcs()
1155 struct drm_i915_private *i915 = engine->i915; in setup_bcs()
1157 engine->emit_flush = gen6_emit_flush_xcs; in setup_bcs()
1158 engine->irq_enable_mask = GT_BLT_USER_INTERRUPT; in setup_bcs()
1161 engine->emit_fini_breadcrumb = gen6_emit_breadcrumb_xcs; in setup_bcs()
1163 engine->emit_fini_breadcrumb = gen7_emit_breadcrumb_xcs; in setup_bcs()
1168 struct drm_i915_private *i915 = engine->i915; in setup_vecs()
1172 engine->emit_flush = gen6_emit_flush_xcs; in setup_vecs()
1173 engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT; in setup_vecs()
1174 engine->irq_enable = hsw_irq_enable_vecs; in setup_vecs()
1175 engine->irq_disable = hsw_irq_disable_vecs; in setup_vecs()
1177 engine->emit_fini_breadcrumb = gen7_emit_breadcrumb_xcs; in setup_vecs()
1198 obj = i915_gem_object_create_internal(engine->i915, size); in gen7_ctx_switch_bb_init()
1202 vma = i915_vma_instance(obj, engine->gt->vm, NULL); in gen7_ctx_switch_bb_init()
1208 vma->private = intel_context_create(engine); /* dummy residuals */ in gen7_ctx_switch_bb_init()
1209 if (IS_ERR(vma->private)) { in gen7_ctx_switch_bb_init()
1210 err = PTR_ERR(vma->private); in gen7_ctx_switch_bb_init()
1226 engine->wa_ctx.vma = vma; in gen7_ctx_switch_bb_init()
1232 intel_context_put(vma->private); in gen7_ctx_switch_bb_init()
1246 switch (engine->class) { in intel_ring_submission_setup()
1260 MISSING_CASE(engine->class); in intel_ring_submission_setup()
1261 return -ENODEV; in intel_ring_submission_setup()
1270 GEM_BUG_ON(timeline->has_initial_breadcrumb); in intel_ring_submission_setup()
1286 GEM_BUG_ON(engine->legacy.ring); in intel_ring_submission_setup()
1287 engine->legacy.ring = ring; in intel_ring_submission_setup()
1288 engine->legacy.timeline = timeline; in intel_ring_submission_setup()
1290 GEM_BUG_ON(timeline->hwsp_ggtt != engine->status_page.vma); in intel_ring_submission_setup()
1292 if (IS_HASWELL(engine->i915) && engine->class == RENDER_CLASS) { in intel_ring_submission_setup()
1299 engine->release = ring_release; in intel_ring_submission_setup()