49 #define VP_CTRL_MSF(v)		FLD_VAL(v, 0, 0) /* Magic square in RGB666 */  argument
50 #define VP_CTRL_VTGEN(v)	FLD_VAL(v, 4, 4) /* Use chip clock for timing */  argument
51 #define VP_CTRL_EVTMODE(v)	FLD_VAL(v, 5, 5) /* Event mode */  argument
52 #define VP_CTRL_RGB888(v)	FLD_VAL(v, 8, 8) /* RGB888 mode */  argument
53 #define VP_CTRL_VSDELAY(v)	FLD_VAL(v, 31, 20) /* VSYNC delay */  argument
58 #define VP_HTIM1_HBP(v)		FLD_VAL(v, 24, 16)  argument
59 #define VP_HTIM1_HSYNC(v)	FLD_VAL(v, 8, 0)  argument
61 #define VP_HTIM2_HFP(v)		FLD_VAL(v, 24, 16)  argument
62 #define VP_HTIM2_HACT(v)	FLD_VAL(v, 10, 0)  argument
64 #define VP_VTIM1_VBP(v)		FLD_VAL(v, 23, 16)  argument
65 #define VP_VTIM1_VSYNC(v)	FLD_VAL(v, 7, 0)  argument
67 #define VP_VTIM2_VFP(v)		FLD_VAL(v, 23, 16)  argument
68 #define VP_VTIM2_VACT(v)	FLD_VAL(v, 10, 0)  argument
116 #define LV_PHY0_RST(v)		FLD_VAL(v, 22, 22) /* PHY reset */  argument
117 #define LV_PHY0_IS(v)		FLD_VAL(v, 15, 14)  argument
118 #define LV_PHY0_ND(v)		FLD_VAL(v, 4, 0) /* Frequency range select */  argument
119 #define LV_PHY0_PRBS_ON(v)	FLD_VAL(v, 20, 16) /* Clock/Data Flag pins */  argument
130 #define SYS_RST_REG		BIT(5) /* Reset Register module */
200 	data[5] = val >> 24;  in tc358764_write()
214 	u32 v = 0;  in tc358764_init()  local
216 	tc358764_read(ctx, SYS_ID, &v);  in tc358764_init()
219 	dev_info(ctx->dev, "ID: %#x\n", v);  in tc358764_init()
224 	tc358764_write(ctx, PPI_D0S_CLRSIPOCOUNT, 5);  in tc358764_init()
225 	tc358764_write(ctx, PPI_D1S_CLRSIPOCOUNT, 5);  in tc358764_init()
226 	tc358764_write(ctx, PPI_D2S_CLRSIPOCOUNT, 5);  in tc358764_init()
227 	tc358764_write(ctx, PPI_D3S_CLRSIPOCOUNT, 5);  in tc358764_init()