Lines Matching +full:0 +full:x5c000000
60 reg = <0x0 0x48211000 0x0 0x1000>,
61 <0x0 0x48212000 0x0 0x2000>,
62 <0x0 0x48214000 0x0 0x2000>,
63 <0x0 0x48216000 0x0 0x2000>;
72 reg = <0x0 0x48281000 0x0 0x1000>;
78 #size-cells = <0>;
80 cpu0: cpu@0 {
83 reg = <0>;
107 opp-supported-hw = <0xFF 0x01>;
116 opp-supported-hw = <0xFF 0x02>;
123 opp-supported-hw = <0xFF 0x04>;
150 ranges = <0x0 0x0 0x0 0xc0000000>;
151 dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>;
153 reg = <0x0 0x44000000 0x0 0x1000000>,
154 <0x0 0x45000000 0x0 0x1000>;
169 axi@0 {
173 ranges = <0x51000000 0x51000000 0x3000
174 0x0 0x20000000 0x10000000>;
181 reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
183 interrupts = <0 232 0x4>, <0 233 0x4>;
187 ranges = <0x81000000 0 0 0x03000 0 0x00010000
188 0x82000000 0 0x20013000 0x13000 0 0xffed000>;
189 bus-range = <0x00 0xff>;
192 linux,pci-domain = <0>;
196 ti,syscon-lane-sel = <&scm_conf_pcie 0x18>;
197 interrupt-map-mask = <0 0 0 7>;
198 interrupt-map = <0 0 0 1 &pcie1_intc 1>,
199 <0 0 0 2 &pcie1_intc 2>,
200 <0 0 0 3 &pcie1_intc 3>,
201 <0 0 0 4 &pcie1_intc 4>;
202 ti,syscon-unaligned-access = <&scm_conf1 0x14 1>;
206 #address-cells = <0>;
212 reg = <0x51000000 0x28>, <0x51002000 0x14c>, <0x51001000 0x28>, <0x1000 0x10000000>;
214 interrupts = <0 232 0x4>;
221 ti,syscon-unaligned-access = <&scm_conf1 0x14 1>;
222 ti,syscon-lane-sel = <&scm_conf_pcie 0x18>;
231 ranges = <0x51800000 0x51800000 0x3000
232 0x0 0x30000000 0x10000000>;
236 reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>;
238 interrupts = <0 355 0x4>, <0 356 0x4>;
242 ranges = <0x81000000 0 0 0x03000 0 0x00010000
243 0x82000000 0 0x30013000 0x13000 0 0xffed000>;
244 bus-range = <0x00 0xff>;
251 interrupt-map-mask = <0 0 0 7>;
252 interrupt-map = <0 0 0 1 &pcie2_intc 1>,
253 <0 0 0 2 &pcie2_intc 2>,
254 <0 0 0 3 &pcie2_intc 3>,
255 <0 0 0 4 &pcie2_intc 4>;
256 ti,syscon-unaligned-access = <&scm_conf1 0x14 2>;
259 #address-cells = <0>;
267 reg = <0x40300000 0x80000>;
268 ranges = <0x0 0x40300000 0x80000>;
282 sram-hs@0 {
284 reg = <0x0 0x0>;
297 reg = <0x40400000 0x100000>;
298 ranges = <0x0 0x40400000 0x100000>;
306 reg = <0x40500000 0x100000>;
307 ranges = <0x0 0x40500000 0x100000>;
313 reg = <0x4a0021e0 0xc
314 0x4a00232c 0xc
315 0x4a002380 0x2c
316 0x4a0023C0 0x3c
317 0x4a002564 0x8
318 0x4a002574 0x50>;
326 reg = <0x40d00000 0x100>;
331 reg = <0x4844a000 0x0d1c>;
333 #size-cells = <0>;
339 reg = <0x43300000 0x4>;
341 clocks = <&l3main1_clkctrl DRA7_L3MAIN1_TPCC_CLKCTRL 0>;
345 ranges = <0x0 0x43300000 0x100000>;
347 edma: dma@0 {
349 reg = <0 0x100000>;
359 ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 0>;
372 reg = <0x43400000 0x4>;
374 clocks = <&l3main1_clkctrl DRA7_L3MAIN1_TPTC0_CLKCTRL 0>;
378 ranges = <0x0 0x43400000 0x100000>;
380 edma_tptc0: dma@0 {
382 reg = <0 0x100000>;
390 reg = <0x43500000 0x4>;
392 clocks = <&l3main1_clkctrl DRA7_L3MAIN1_TPTC1_CLKCTRL 0>;
396 ranges = <0x0 0x43500000 0x100000>;
398 edma_tptc1: dma@0 {
400 reg = <0 0x100000>;
408 reg = <0x4e000000 0x800>;
415 reg = <0x58820000 0x10000>;
419 resets = <&prm_ipu 0>, <&prm_ipu 1>;
420 clocks = <&ipu1_clkctrl DRA7_IPU1_MMU_IPU1_CLKCTRL 0>;
426 reg = <0x55020000 0x10000>;
430 resets = <&prm_core 0>, <&prm_core 1>;
431 clocks = <&ipu2_clkctrl DRA7_IPU2_MMU_IPU2_CLKCTRL 0>;
437 reg = <0x40800000 0x48000>,
438 <0x40e00000 0x8000>,
439 <0x40f00000 0x8000>;
441 ti,bootreg = <&scm_conf 0x55c 10>;
444 resets = <&prm_dsp1 0>;
445 clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>;
451 reg = <0x40d01000 0x4>,
452 <0x40d01010 0x4>,
453 <0x40d01014 0x4>;
461 clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>;
465 ranges = <0x0 0x40d01000 0x1000>;
469 mmu0_dsp1: mmu@0 {
471 reg = <0x0 0x100>;
473 #iommu-cells = <0>;
474 ti,syscon-mmuconfig = <&dsp1_system 0x0>;
480 reg = <0x40d02000 0x4>,
481 <0x40d02010 0x4>,
482 <0x40d02014 0x4>;
490 clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>;
494 ranges = <0x0 0x40d02000 0x1000>;
498 mmu1_dsp1: mmu@0 {
500 reg = <0x0 0x100>;
502 #iommu-cells = <0>;
503 ti,syscon-mmuconfig = <&dsp1_system 0x1>;
509 reg = <0x58882000 0x4>,
510 <0x58882010 0x4>,
511 <0x58882014 0x4>;
519 clocks = <&ipu1_clkctrl DRA7_IPU1_MMU_IPU1_CLKCTRL 0>;
525 ranges = <0x0 0x58882000 0x100>;
527 mmu_ipu1: mmu@0 {
529 reg = <0x0 0x100>;
531 #iommu-cells = <0>;
538 reg = <0x55082000 0x4>,
539 <0x55082010 0x4>,
540 <0x55082014 0x4>;
548 clocks = <&ipu2_clkctrl DRA7_IPU2_MMU_IPU2_CLKCTRL 0>;
554 ranges = <0x0 0x55082000 0x100>;
556 mmu_ipu2: mmu@0 {
558 reg = <0x0 0x100>;
560 #iommu-cells = <0>;
568 #address-cells = <0>;
569 #size-cells = <0>;
574 reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>,
575 <0x4ae06014 0x4>, <0x4a003b20 0xc>,
576 <0x4ae0c158 0x4>;
580 ti,tranxdone-status-mask = <0x80>;
582 ti,ldovbb-override-mask = <0x400>;
584 ti,ldovbb-vset-mask = <0x1F>;
592 1060000 0 0x0 0 0x02000000 0x01F00000
593 1160000 0 0x4 0 0x02000000 0x01F00000
594 1210000 0 0x8 0 0x02000000 0x01F00000
601 #address-cells = <0>;
602 #size-cells = <0>;
607 reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>,
608 <0x4ae06010 0x4>, <0x4a0025cc 0xc>,
609 <0x4a002470 0x4>;
613 ti,tranxdone-status-mask = <0x40000000>;
615 ti,ldovbb-override-mask = <0x400>;
617 ti,ldovbb-vset-mask = <0x1F>;
625 1055000 0 0x0 0 0x02000000 0x01F00000
626 1150000 0 0x4 0 0x02000000 0x01F00000
627 1250000 0 0x8 0 0x02000000 0x01F00000
634 #address-cells = <0>;
635 #size-cells = <0>;
640 reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>,
641 <0x4ae06010 0x4>, <0x4a0025e0 0xc>,
642 <0x4a00246c 0x4>;
646 ti,tranxdone-status-mask = <0x20000000>;
648 ti,ldovbb-override-mask = <0x400>;
650 ti,ldovbb-vset-mask = <0x1F>;
658 1055000 0 0x0 0 0x02000000 0x01F00000
659 1150000 0 0x4 0 0x02000000 0x01F00000
660 1250000 0 0x8 0 0x02000000 0x01F00000
667 #address-cells = <0>;
668 #size-cells = <0>;
673 reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>,
674 <0x4ae06010 0x4>, <0x4a003b08 0xc>,
675 <0x4ae0c154 0x4>;
679 ti,tranxdone-status-mask = <0x10000000>;
681 ti,ldovbb-override-mask = <0x400>;
683 ti,ldovbb-vset-mask = <0x1F>;
691 1090000 0 0x0 0 0x02000000 0x01F00000
692 1210000 0 0x4 0 0x02000000 0x01F00000
693 1280000 0 0x8 0 0x02000000 0x01F00000
699 reg = <0x4b300000 0x100>,
700 <0x5c000000 0x4000000>;
702 syscon-chipselects = <&scm_conf 0x558>;
704 #size-cells = <0>;
716 reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
722 ports-implemented = <0x1>;
730 reg = <0x50000000 0x37c>; /* device IO registers */
732 dmas = <&edma_xbar 4 0>;
747 reg = <0x5600fe00 0x4>,
748 <0x5600fe10 0x4>;
756 clocks = <&gpu_clkctrl DRA7_GPU_CLKCTRL 0>;
760 ranges = <0 0x56000000 0x2000000>;
765 reg = <0x4a002a48 0x130>;
772 ti,irqs-reserved = <0 1 2 3 5 6 131 132>;
774 ti,irqs-safe-map = <0>;
779 reg = <0x58000000 4>,
780 <0x58000014 4>;
783 clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 0>,
790 ranges = <0 0x58000000 0x800000>;
792 dss: dss@0 {
798 syscon-pll-ctrl = <&scm_conf 0x538>;
801 ranges = <0 0 0x800000>;
805 reg = <0x1000 0x4>,
806 <0x1010 0x4>,
807 <0x1014 0x4>;
824 ranges = <0 0x1000 0x1000>;
826 dispc@0 {
828 reg = <0 0x1000>;
833 syscon-pol = <&scm_conf 0x534>;
839 reg = <0x40000 0x4>,
840 <0x40010 0x4>;
852 ranges = <0 0x40000 0x40000>;
854 hdmi: encoder@0 {
856 reg = <0 0x200>,
857 <0x200 0x80>,
858 <0x300 0x80>,
859 <0x20000 0x19000>;
875 reg = <0x4b500080 0x4>,
876 <0x4b500084 0x4>,
877 <0x4b500088 0x4>;
887 clocks = <&l4sec_clkctrl DRA7_L4SEC_AES1_CLKCTRL 0>;
891 ranges = <0x0 0x4b500000 0x1000>;
893 aes1: aes@0 {
895 reg = <0 0xa0>;
897 dmas = <&edma_xbar 111 0>, <&edma_xbar 110 0>;
906 reg = <0x4b700080 0x4>,
907 <0x4b700084 0x4>,
908 <0x4b700088 0x4>;
918 clocks = <&l4sec_clkctrl DRA7_L4SEC_AES2_CLKCTRL 0>;
922 ranges = <0x0 0x4b700000 0x1000>;
924 aes2: aes@0 {
926 reg = <0 0xa0>;
928 dmas = <&edma_xbar 114 0>, <&edma_xbar 113 0>;
937 reg = <0x4b101100 0x4>,
938 <0x4b101110 0x4>,
939 <0x4b101114 0x4>;
948 clocks = <&l4sec_clkctrl DRA7_L4SEC_SHAM_CLKCTRL 0>;
952 ranges = <0x0 0x4b101000 0x1000>;
954 sham: sham@0 {
956 reg = <0 0x300>;
958 dmas = <&edma_xbar 119 0>;
967 reg = <0x4a003b20 0xc>;
970 1060000 0x0
971 1160000 0x4
972 1210000 0x8
991 coefficients = <0 2000>;
995 coefficients = <0 2000>;
999 coefficients = <0 2000>;
1003 coefficients = <0 2000>;
1007 coefficients = <0 2000>;
1036 reg = <0x400 0x100>;
1042 reg = <0x500 0x100>;
1048 reg = <0x700 0x100>;
1054 reg = <0xf00 0x100>;
1059 reg = <0x1b00 0x40>;
1065 reg = <0x1b40 0x40>;
1070 reg = <0x1b80 0x40>;
1075 reg = <0x1bc0 0x40>;
1080 reg = <0x1c00 0x60>;
1088 timer@0 {