35 #define DRV_VERSION	"1.5.0"
42 static int debug = 0;
44         (0x0000)
130 module_param(debug, int, 0);
131 module_param(rx_copybreak, int, 0);
132 module_param(avoid_D3, bool, 0);
153 offset 0x78. For most of these settings, this driver assumes that they are
241 	VT86C100A	= 0x00,
242 	VTunknown0	= 0x20,
243 	VT6102		= 0x40,
244 	VT8231		= 0x50,	/* Integrated MAC */
245 	VT8233		= 0x60,	/* Integrated MAC */
246 	VT8235		= 0x74,	/* Integrated MAC */
247 	VT8237		= 0x78,	/* Integrated MAC */
248 	VTunknown1	= 0x7C,
249 	VT6105		= 0x80,
250 	VT6105_B0	= 0x83,
251 	VT6105L		= 0x8A,
252 	VT6107		= 0x8C,
253 	VTunknown2	= 0x8E,
254 	VT6105M		= 0x90,	/* Management adapter */
258 	rqWOL		= 0x0001,	/* Wake-On-LAN support */
259 	rqForceReset	= 0x0002,
260 	rq6patterns	= 0x0040,	/* 6 instead of 4 patterns for WOL */
261 	rqStatusWBRace	= 0x0080,	/* Tx Status Writeback Error possible */
262 	rqRhineI	= 0x0100,	/* See comment below */
271 #define IOSYNC	do { ioread8(ioaddr + StationAddr); } while (0)
274 	{ 0x1106, 0x3043, PCI_ANY_ID, PCI_ANY_ID, },	/* VT86C100A */
275 	{ 0x1106, 0x3065, PCI_ANY_ID, PCI_ANY_ID, },	/* VT6102 */
276 	{ 0x1106, 0x3106, PCI_ANY_ID, PCI_ANY_ID, },	/* 6105{,L,LOM} */
277 	{ 0x1106, 0x3053, PCI_ANY_ID, PCI_ANY_ID, },	/* VT6105M */
285 	StationAddr=0x00, RxConfig=0x06, TxConfig=0x07, ChipCmd=0x08,
286 	ChipCmd1=0x09, TQWake=0x0A,
287 	IntrStatus=0x0C, IntrEnable=0x0E,
288 	MulticastFilter0=0x10, MulticastFilter1=0x14,
289 	RxRingPtr=0x18, TxRingPtr=0x1C, GFIFOTest=0x54,
290 	MIIPhyAddr=0x6C, MIIStatus=0x6D, PCIBusConfig=0x6E, PCIBusConfig1=0x6F,
291 	MIICmd=0x70, MIIRegAddr=0x71, MIIData=0x72, MACRegEEcsr=0x74,
292 	ConfigA=0x78, ConfigB=0x79, ConfigC=0x7A, ConfigD=0x7B,
293 	RxMissed=0x7C, RxCRCErrs=0x7E, MiscCmd=0x81,
294 	StickyHW=0x83, IntrStatus2=0x84,
295 	CamMask=0x88, CamCon=0x92, CamAddr=0x93,
296 	WOLcrSet=0xA0, PwcfgSet=0xA1, WOLcgSet=0xA3, WOLcrClr=0xA4,
297 	WOLcrClr1=0xA6, WOLcgClr=0xA7,
298 	PwrcsrSet=0xA8, PwrcsrSet1=0xA9, PwrcsrClr=0xAC, PwrcsrClr1=0xAD,
303 	BackOptional=0x01, BackModify=0x02,
304 	BackCaptureEffect=0x04, BackRandom=0x08
309 	TCR_PQEN=0x01,
310 	TCR_LB0=0x02,		/* loopback[0] */
311 	TCR_LB1=0x04,		/* loopback[1] */
312 	TCR_OFSET=0x08,
313 	TCR_RTGOPT=0x10,
314 	TCR_RTFT0=0x20,
315 	TCR_RTFT1=0x40,
316 	TCR_RTSF=0x80,
321 	CAMC_CAMEN=0x01,
322 	CAMC_VCAMSL=0x02,
323 	CAMC_CAMWR=0x04,
324 	CAMC_CAMRD=0x08,
329 	BCR1_POT0=0x01,
330 	BCR1_POT1=0x02,
331 	BCR1_POT2=0x04,
332 	BCR1_CTFT0=0x08,
333 	BCR1_CTFT1=0x10,
334 	BCR1_CTSF=0x20,
335 	BCR1_TXQNOBK=0x40,	/* for VT6105 */
336 	BCR1_VIDFR=0x80,	/* for VT6105 */
337 	BCR1_MED0=0x40,		/* for VT6102 */
338 	BCR1_MED1=0x80,		/* for VT6102 */
345 	0
351 	IntrRxDone	= 0x0001,
352 	IntrTxDone	= 0x0002,
353 	IntrRxErr	= 0x0004,
354 	IntrTxError	= 0x0008,
355 	IntrRxEmpty	= 0x0020,
356 	IntrPCIErr	= 0x0040,
357 	IntrStatsMax	= 0x0080,
358 	IntrRxEarly	= 0x0100,
359 	IntrTxUnderrun	= 0x0210,
360 	IntrRxOverflow	= 0x0400,
361 	IntrRxDropped	= 0x0800,
362 	IntrRxNoBuf	= 0x1000,
363 	IntrTxAborted	= 0x2000,
364 	IntrLinkChange	= 0x4000,
365 	IntrRxWakeUp	= 0x8000,
366 	IntrTxDescRace		= 0x080000,	/* mapped from IntrStatus2 */
374 	WOLucast	= 0x10,
375 	WOLmagic	= 0x20,
376 	WOLbmcast	= 0x30,
377 	WOLlnkon	= 0x40,
378 	WOLlnkoff	= 0x80,
395 /* Initial value for tx_desc.desc_length, Buffer size goes to bits 0-10 */
396 #define TXDESC		0x00e08000
399 	RxOK=0x8000, RxWholePkt=0x0300, RxErr=0x008F
404 	DescOwn=0x80000000
409 	DescTag=0x00010000
414 	CmdInit=0x01, CmdStart=0x02, CmdStop=0x04, CmdRxOn=0x08,
415 	CmdTxOn=0x10, Cmd1TxDemand=0x20, CmdRxDemand=0x40,
416 	Cmd1EarlyRx=0x01, Cmd1EarlyTx=0x02, Cmd1FDuplex=0x04,
417 	Cmd1NoTxPoll=0x08, Cmd1Reset=0x80,
469 #define BYTE_REG_BITS_ON(x, p)      do { iowrite8((ioread8((p))|(x)), (p)); } while (0)
470 #define WORD_REG_BITS_ON(x, p)      do { iowrite16((ioread16((p))|(x)), (p)); } while (0)
471 #define DWORD_REG_BITS_ON(x, p)     do { iowrite32((ioread32((p))|(x)), (p)); } while (0)
477 #define BYTE_REG_BITS_OFF(x, p)     do { iowrite8(ioread8((p)) & (~(x)), (p)); } while (0)
478 #define WORD_REG_BITS_OFF(x, p)     do { iowrite16(ioread16((p)) & (~(x)), (p)); } while (0)
479 #define DWORD_REG_BITS_OFF(x, p)    do { iowrite32(ioread32((p)) & (~(x)), (p)); } while (0)
481 #define BYTE_REG_BITS_SET(x, m, p)   do { iowrite8((ioread8((p)) & (~(m)))|(x), (p)); } while (0)
482 #define WORD_REG_BITS_SET(x, m, p)   do { iowrite16((ioread16((p)) & (~(m)))|(x), (p)); } while (0)
483 #define DWORD_REG_BITS_SET(x, m, p)  do { iowrite32((ioread32((p)) & (~(m)))|(x), (p)); } while (0)
511 	for (i = 0; i < 1024; i++) {  in rhine_wait_bit()
566 		iowrite8(ioread8(ioaddr + StickyHW) & 0xFC, ioaddr + StickyHW);  in rhine_power_init()
569 		iowrite8(0x80, ioaddr + WOLcgClr);  in rhine_power_init()
572 		iowrite8(0xFF, ioaddr + WOLcrClr);  in rhine_power_init()
575 			iowrite8(0x03, ioaddr + WOLcrClr1);  in rhine_power_init()
580 			wolstat |= (ioread8(ioaddr + PwrcsrSet1) & 0x03) << 8;  in rhine_power_init()
583 		iowrite8(0xFF, ioaddr + PwrcsrClr);  in rhine_power_init()
585 			iowrite8(0x03, ioaddr + PwrcsrClr1);  in rhine_power_init()
628 			iowrite8(0x40, ioaddr + MiscCmd);  in rhine_chip_reset()
645 		n = inb(pioaddr + ConfigA) | 0x20;  in enable_mmio()
648 		n = inb(pioaddr + ConfigD) | 0x80;  in enable_mmio()
655  * Loads bytes 0x00-0x05, 0x6E-0x6F, 0x78-0x7B from EEPROM
656  * (plus 0x6C for Rhine-I/II)
664 	outb(0x20, pioaddr + MACRegEEcsr);  in rhine_reload_eeprom()
665 	for (i = 0; i < 1024; i++) {  in rhine_reload_eeprom()
666 		if (!(inb(pioaddr + MACRegEEcsr) & 0x20))  in rhine_reload_eeprom()
683 		iowrite8(ioread8(ioaddr + ConfigA) & 0xFC, ioaddr + ConfigA);  in rhine_reload_eeprom()
698 	if (rp->tx_thresh < 0xe0) {  in rhine_kick_tx_threshold()
701 		rp->tx_thresh += 0x20;  in rhine_kick_tx_threshold()
702 		BYTE_REG_BITS_SET(rp->tx_thresh, 0x80, ioaddr + TxConfig);  in rhine_kick_tx_threshold()
725 	    (status & (IntrTxAborted | IntrTxUnderrun | IntrTxDescRace)) == 0) {  in rhine_tx_err()
744 	 * It has been reported that some chips need a write of 0 to clear  in rhine_update_rx_crc_and_missed_errord()
748 	iowrite32(0, ioaddr + RxMissed);  in rhine_update_rx_crc_and_missed_errord()
778 	u16 enable_mask = RHINE_EVENT & 0xffff;  in rhine_napipoll()
779 	int work_done = 0;  in rhine_napipoll()
869 	int bar = 0;  in rhine_init_one()
878 	phy_id = 0;  in rhine_init_one()
879 	quirks = 0;  in rhine_init_one()
915 	if ((pci_resource_len(pdev, 0) < io_size) ||  in rhine_init_one()
922 	pioaddr = pci_resource_start(pdev, 0);  in rhine_init_one()
950 			"ioremap failed for device %s, region 0x%X @ 0x%lX\n",  in rhine_init_one()
959 	i = 0;  in rhine_init_one()
981 	for (i = 0; i < 6; i++)  in rhine_init_one()
995 		phy_id = ioread8(ioaddr + 0x6C);  in rhine_init_one()
1007 	rp->mii_if.phy_id_mask = 0x1f;  in rhine_init_one()
1008 	rp->mii_if.reg_num_mask = 0x1f;  in rhine_init_one()
1029 	netdev_info(dev, "VIA %s at 0x%lx, %pM, IRQ %d\n",  in rhine_init_one()
1045 		if (mii_status != 0xffff && mii_status != 0x0000) {  in rhine_init_one()
1048 				    "MII PHY found at address %d, status 0x%04x advertising %04x Link %04x\n",  in rhine_init_one()
1065 	return 0;  in rhine_init_one()
1109 	return 0;  in alloc_ring()
1136 	rp->dirty_rx = rp->cur_rx = 0;  in alloc_rbufs()
1139 	rp->rx_head_desc = &rp->rx_ring[0];  in alloc_rbufs()
1143 	for (i = 0; i < RX_RING_SIZE; i++) {  in alloc_rbufs()
1144 		rp->rx_ring[i].rx_status = 0;  in alloc_rbufs()
1154 	for (i = 0; i < RX_RING_SIZE; i++) {  in alloc_rbufs()
1177 	for (i = 0; i < RX_RING_SIZE; i++) {  in free_rbufs()
1178 		rp->rx_ring[i].rx_status = 0;  in free_rbufs()
1179 		rp->rx_ring[i].addr = cpu_to_le32(0xBADF00D0); /* An invalid address. */  in free_rbufs()
1196 	rp->dirty_tx = rp->cur_tx = 0;  in alloc_tbufs()
1198 	for (i = 0; i < TX_RING_SIZE; i++) {  in alloc_tbufs()
1200 		rp->tx_ring[i].tx_status = 0;  in alloc_tbufs()
1216 	for (i = 0; i < TX_RING_SIZE; i++) {  in free_tbufs()
1217 		rp->tx_ring[i].tx_status = 0;  in free_tbufs()
1219 		rp->tx_ring[i].addr = cpu_to_le32(0xBADF00D0); /* An invalid address. */  in free_tbufs()
1263 		rhine_check_media(dev, 0);  in rhine_set_carrier()
1272  * @idx: multicast CAM index [0..MCAM_SIZE-1]
1289 	for (i = 0; i < 6; i++, addr++)  in rhine_set_cam()
1297 	iowrite8(0, ioaddr + CamCon);  in rhine_set_cam()
1303  * @idx: VLAN CAM index [0..VCAM_SIZE-1]
1325 	iowrite8(0, ioaddr + CamCon);  in rhine_set_vlan_cam()
1344 	iowrite8(0, ioaddr + CamCon);  in rhine_set_cam_mask()
1363 	iowrite8(0, ioaddr + CamCon);  in rhine_set_vlan_cam_mask()
1379 	rhine_set_vlan_cam_mask(ioaddr, 0);  in rhine_init_cam_filter()
1380 	rhine_set_cam_mask(ioaddr, 0);  in rhine_init_cam_filter()
1398 	u32 vCAMmask = 0;	/* 32 vCAMs (6105M and better) */  in rhine_update_vcam()
1399 	unsigned int i = 0;  in rhine_update_vcam()
1418 	return 0;  in rhine_vlan_rx_add_vid()
1429 	return 0;  in rhine_vlan_rx_kill_vid()
1438 	for (i = 0; i < 6; i++)  in init_registers()
1442 	iowrite16(0x0006, ioaddr + PCIBusConfig);	/* Tune configuration??? */  in init_registers()
1444 	iowrite8(0x20, ioaddr + TxConfig);  in init_registers()
1445 	rp->tx_thresh = 0x20;  in init_registers()
1446 	rp->rx_thresh = 0x60;		/* Written in rhine_set_rx_mode(). */  in init_registers()
1458 	iowrite16(RHINE_EVENT & 0xffff, ioaddr + IntrEnable);  in init_registers()
1470 	iowrite8(0, ioaddr + MIICmd);  in rhine_enable_linkmon()
1472 	iowrite8(0x80, ioaddr + MIICmd);  in rhine_enable_linkmon()
1474 	rhine_wait_bit_high(rp, MIIRegAddr, 0x20);  in rhine_enable_linkmon()
1476 	iowrite8(MII_BMSR | 0x40, ioaddr + MIIRegAddr);  in rhine_enable_linkmon()
1484 	iowrite8(0, ioaddr + MIICmd);  in rhine_disable_linkmon()
1487 		iowrite8(0x01, ioaddr + MIIRegAddr);	// MII_BMSR  in rhine_disable_linkmon()
1492 		/* 0x80 must be set immediately before turning it off */  in rhine_disable_linkmon()
1493 		iowrite8(0x80, ioaddr + MIICmd);  in rhine_disable_linkmon()
1495 		rhine_wait_bit_high(rp, MIIRegAddr, 0x20);  in rhine_disable_linkmon()
1497 		/* Heh. Now clear 0x80 again. */  in rhine_disable_linkmon()
1498 		iowrite8(0, ioaddr + MIICmd);  in rhine_disable_linkmon()
1501 		rhine_wait_bit_high(rp, MIIRegAddr, 0x80);  in rhine_disable_linkmon()
1517 	iowrite8(0x40, ioaddr + MIICmd);		/* Trigger read */  in mdio_read()
1518 	rhine_wait_bit_low(rp, MIICmd, 0x40);  in mdio_read()
1536 	iowrite8(0x20, ioaddr + MIICmd);		/* Trigger write */  in mdio_write()
1537 	rhine_wait_bit_low(rp, MIICmd, 0x20);  in mdio_write()
1589 	return 0;  in rhine_open()
1657 …(((unsigned long)skb->data & 3) || skb_shinfo(skb)->nr_frags != 0 || skb->ip_summed == CHECKSUM_PA…  in rhine_start_tx()
1670 			memset(rp->tx_buf[entry] + skb->len, 0,  in rhine_start_tx()
1672 		rp->tx_skbuff_dma[entry] = 0;  in rhine_start_tx()
1689 		rp->tx_ring[entry].desc_length |= cpu_to_le32(0x020000);  in rhine_start_tx()
1692 		rp->tx_ring[entry].tx_status = 0;  in rhine_start_tx()
1704 		/* Tx queues are bits 7-0 (first Tx queue: bit 7) */  in rhine_start_tx()
1723 	iowrite16(0x0000, rp->base + IntrEnable);  in rhine_irq_disable()
1734 	int handled = 0;  in rhine_interrupt()
1760 	int txstatus = 0, entry = rp->dirty_tx % TX_RING_SIZE;  in rhine_tx()
1769 		if (txstatus & 0x8000) {  in rhine_tx()
1773 			if (txstatus & 0x0400)  in rhine_tx()
1775 			if (txstatus & 0x0200)  in rhine_tx()
1777 			if (txstatus & 0x0100)  in rhine_tx()
1779 			if (txstatus & 0x0080)  in rhine_tx()
1781 			if (((rp->quirks & rqRhineI) && txstatus & 0x0002) ||  in rhine_tx()
1782 			    (txstatus & 0x0800) || (txstatus & 0x1000)) {  in rhine_tx()
1790 				dev->stats.collisions += (txstatus >> 3) & 0x0F;  in rhine_tx()
1792 				dev->stats.collisions += txstatus & 0x0F;  in rhine_tx()
1794 				  (txstatus >> 3) & 0xF, txstatus & 0xF);  in rhine_tx()
1839 	for (count = 0; count < limit; ++count) {  in rhine_rx()
1869 				if (desc_status & 0x0030)  in rhine_rx()
1871 				if (desc_status & 0x0048)  in rhine_rx()
1873 				if (desc_status & 0x0004)  in rhine_rx()
1875 				if (desc_status & 0x0002) {  in rhine_rx()
1886 			u16 vlan_tci = 0;  in rhine_rx()
1936 	for (; rp->cur_rx - rp->dirty_rx > 0; rp->dirty_rx++) {  in rhine_rx()
1969 	if ((intr_status & IntrTxErrSummary) == 0) {  in rhine_restart_tx()
1978 		if (rp->tx_ring[entry].desc_length & cpu_to_le32(0x020000))  in rhine_restart_tx()
1979 			/* Tx queues are bits 7-0 (first Tx queue: bit 7) */  in rhine_restart_tx()
2010 		rhine_check_media(dev, 0);  in rhine_slow_event_task()
2041 	u8 rx_mode = 0x0C;	/* Note: 0x02=accept runt, 0x01=accept errs */  in rhine_set_rx_mode()
2045 		rx_mode = 0x1C;  in rhine_set_rx_mode()
2046 		iowrite32(0xffffffff, ioaddr + MulticastFilter0);  in rhine_set_rx_mode()
2047 		iowrite32(0xffffffff, ioaddr + MulticastFilter1);  in rhine_set_rx_mode()
2051 		iowrite32(0xffffffff, ioaddr + MulticastFilter0);  in rhine_set_rx_mode()
2052 		iowrite32(0xffffffff, ioaddr + MulticastFilter1);  in rhine_set_rx_mode()
2054 		int i = 0;  in rhine_set_rx_mode()
2055 		u32 mCAMmask = 0;	/* 32 mCAMs (6105M and better) */  in rhine_set_rx_mode()
2065 		memset(mc_filter, 0, sizeof(mc_filter));  in rhine_set_rx_mode()
2071 		iowrite32(mc_filter[0], ioaddr + MulticastFilter0);  in rhine_set_rx_mode()
2176 	return 0;  in rhine_set_wol()
2220 	iowrite8(rp->tx_thresh | 0x02, ioaddr + TxConfig);  in rhine_close()
2232 	return 0;  in rhine_close()
2262 	/* Make sure we use pattern 0, 1 and not 4, 5 */  in rhine_shutdown()
2264 		iowrite8(0x04, ioaddr + WOLcgClr);  in rhine_shutdown()
2274 		iowrite8(ioread8(ioaddr + ConfigA) | 0x03, ioaddr + ConfigA);  in rhine_shutdown()
2288 		iowrite8(0x01, ioaddr + PwcfgSet);  in rhine_shutdown()
2289 		iowrite8(ioread8(ioaddr + StickyHW) | 0x04, ioaddr + StickyHW);  in rhine_shutdown()
2295 		iowrite8(ioread8(ioaddr + StickyHW) | 0x03, ioaddr + StickyHW);  in rhine_shutdown()
2310 		return 0;  in rhine_suspend()
2320 	return 0;  in rhine_suspend()
2330 		return 0;  in rhine_resume()
2347 	return 0;  in rhine_resume()