2  * Support for Moorestown/Medfield I2C chip
28 #include <linux/i2c.h>
35 #define DRIVER_NAME	"i2c-intel-mid"
59  * @adap: core i2c layer adapter information
73  * i2c layer objects and the data we need to track privately.
109 #define IC_TAR_SPECIAL		(1 << 11)	/* Perform special I2C cmd */
273 #define IC_EN			(1 << 0)	/* I2C in an enabled state */
304 MODULE_PARM_DESC(speed_mode, "Set the speed of the i2c interface (0-2)");
307  * intel_mid_i2c_disable - Disable I2C controller
313  * -ETIMEDOUT	if i2c cannot be disabled within the given time
315  * I2C bus state should be checked prior to disabling the hardware. If bus is
317  * I2C controller.
321 	struct intel_mid_i2c_private *i2c = i2c_get_adapdata(adap);  in intel_mid_i2c_disable()  local
328 	writel(0, i2c->base + IC_ENABLE);  in intel_mid_i2c_disable()
331 	dev_dbg(&adap->dev, "mrst i2c disable\n");  in intel_mid_i2c_disable()
332 	while ((ret1 = readl(i2c->base + IC_ENABLE_STATUS) & 0x1)  in intel_mid_i2c_disable()
333 		|| (ret2 = readl(i2c->base + IC_STATUS) & 0x1)) {  in intel_mid_i2c_disable()
334 		udelay(delay[i2c->speed]);  in intel_mid_i2c_disable()
335 		writel(0, i2c->base + IC_ENABLE);  in intel_mid_i2c_disable()
336 		dev_dbg(&adap->dev, "i2c is busy, count is %d speed %d\n",  in intel_mid_i2c_disable()
337 			count, i2c->speed);  in intel_mid_i2c_disable()
345 	readl(i2c->base + IC_CLR_INTR);  in intel_mid_i2c_disable()
346 	readl(i2c->base + IC_CLR_STOP_DET);  in intel_mid_i2c_disable()
347 	readl(i2c->base + IC_CLR_START_DET);  in intel_mid_i2c_disable()
348 	readl(i2c->base + IC_CLR_ACTIVITY);  in intel_mid_i2c_disable()
349 	readl(i2c->base + IC_CLR_TX_ABRT);  in intel_mid_i2c_disable()
350 	readl(i2c->base + IC_CLR_RX_OVER);  in intel_mid_i2c_disable()
351 	readl(i2c->base + IC_CLR_RX_UNDER);  in intel_mid_i2c_disable()
352 	readl(i2c->base + IC_CLR_TX_OVER);  in intel_mid_i2c_disable()
353 	readl(i2c->base + IC_CLR_RX_DONE);  in intel_mid_i2c_disable()
354 	readl(i2c->base + IC_CLR_GEN_CALL);  in intel_mid_i2c_disable()
357 	writel(0x0000, i2c->base + IC_INTR_MASK);  in intel_mid_i2c_disable()
363  * intel_mid_i2c_hwinit - Initialize the I2C hardware registers
371  * -EBUSY	i2c cannot be disabled
372  * -ETIMEDOUT	i2c cannot be disabled
375  * I2C should be disabled prior to other register operation. If failed, an
381 static int intel_mid_i2c_hwinit(struct intel_mid_i2c_private *i2c)  in intel_mid_i2c_hwinit()  argument
394 	/* Disable i2c first */  in intel_mid_i2c_hwinit()
395 	err = intel_mid_i2c_disable(&i2c->adap);  in intel_mid_i2c_hwinit()
406 	writel((i2c->speed + 1) << 1 | SLV_DIS | RESTART | MASTER_EN,  in intel_mid_i2c_hwinit()
407 		i2c->base + IC_CON);  in intel_mid_i2c_hwinit()
408 	writel(hcnt[i2c->platform][i2c->speed],  in intel_mid_i2c_hwinit()
409 		i2c->base + (IC_SS_SCL_HCNT + (i2c->speed << 3)));  in intel_mid_i2c_hwinit()
410 	writel(lcnt[i2c->platform][i2c->speed],  in intel_mid_i2c_hwinit()
411 		i2c->base + (IC_SS_SCL_LCNT + (i2c->speed << 3)));  in intel_mid_i2c_hwinit()
414 	writel(0x0, i2c->base + IC_RX_TL);  in intel_mid_i2c_hwinit()
415 	writel(0x0, i2c->base + IC_TX_TL);  in intel_mid_i2c_hwinit()
421  * intel_mid_i2c_func - Return the supported three I2C operations.
430  * intel_mid_i2c_address_neq - To check if the addresses for different i2c messages
439  * Within a single transfer, the I2C client may need to send its address more
464 static void intel_mid_i2c_abort(struct intel_mid_i2c_private *i2c)  in intel_mid_i2c_abort()  argument
467 	int abort = i2c->abort;  in intel_mid_i2c_abort()
468 	struct i2c_adapter *adap = &i2c->adap;  in intel_mid_i2c_abort()
484 		writel(~ABRT_SBYTE_NORSTRT, i2c->base + IC_TX_ABRT_SOURCE);  in intel_mid_i2c_abort()
485 		writel(RESTART, i2c->base + IC_CON);  in intel_mid_i2c_abort()
486 		writel(~IC_TAR_SPECIAL, i2c->base + IC_TAR);  in intel_mid_i2c_abort()
503 			"I2C slave device not acknowledged.\n");  in intel_mid_i2c_abort()
506 	readl(i2c->base + IC_CLR_TX_ABRT);  in intel_mid_i2c_abort()
507 	i2c->status = STATUS_XFER_ABORT;  in intel_mid_i2c_abort()
530 	struct intel_mid_i2c_private *i2c = i2c_get_adapdata(adap);  in xfer_read()  local
536 			"I2C FIFO cannot support larger than 256 bytes\n");  in xfer_read()
540 	INIT_COMPLETION(i2c->complete);  in xfer_read()
542 	readl(i2c->base + IC_CLR_INTR);  in xfer_read()
543 	writel(0x0044, i2c->base + IC_INTR_MASK);  in xfer_read()
545 	i2c->status = STATUS_READ_START;  in xfer_read()
548 		writel(IC_RD, i2c->base + IC_DATA_CMD);  in xfer_read()
550 	i2c->status = STATUS_READ_START;  in xfer_read()
551 	err = wait_for_completion_interruptible_timeout(&i2c->complete, HZ);  in xfer_read()
553 		dev_err(&adap->dev, "Timeout for ACK from I2C slave device\n");  in xfer_read()
554 		intel_mid_i2c_hwinit(i2c);  in xfer_read()
557 	if (i2c->status == STATUS_READ_SUCCESS)  in xfer_read()
584 	struct intel_mid_i2c_private *i2c = i2c_get_adapdata(adap);  in xfer_write()  local
589 			"I2C FIFO cannot support larger than 256 bytes\n");  in xfer_write()
593 	INIT_COMPLETION(i2c->complete);  in xfer_write()
595 	readl(i2c->base + IC_CLR_INTR);  in xfer_write()
596 	writel(0x0050, i2c->base + IC_INTR_MASK);  in xfer_write()
598 	i2c->status = STATUS_WRITE_START;  in xfer_write()
600 		writel((u16)(*(buf + i)), i2c->base + IC_DATA_CMD);  in xfer_write()
602 	i2c->status = STATUS_WRITE_START;  in xfer_write()
603 	err = wait_for_completion_interruptible_timeout(&i2c->complete, HZ);  in xfer_write()
605 		dev_err(&adap->dev, "Timeout for ACK from I2C slave device\n");  in xfer_write()
606 		intel_mid_i2c_hwinit(i2c);  in xfer_write()
609 		if (i2c->status == STATUS_WRITE_SUCCESS)  in xfer_write()
618 	struct intel_mid_i2c_private *i2c = i2c_get_adapdata(adap);  in intel_mid_i2c_setup()  local
628 			"Cannot disable i2c controller, timeout\n");  in intel_mid_i2c_setup()
632 	mode = (1 + i2c->speed) << 1;  in intel_mid_i2c_setup()
634 	reg = readl(i2c->base + IC_CON);  in intel_mid_i2c_setup()
636 		dev_dbg(&adap->dev, "set mode %d\n", i2c->speed);  in intel_mid_i2c_setup()
637 		writel((reg & ~0x6) | mode, i2c->base + IC_CON);  in intel_mid_i2c_setup()
640 	reg = readl(i2c->base + IC_CON);  in intel_mid_i2c_setup()
644 			dev_dbg(&adap->dev, "set i2c 10 bit address mode\n");  in intel_mid_i2c_setup()
645 			writel(reg | ADDR_10BIT, i2c->base + IC_CON);  in intel_mid_i2c_setup()
649 			dev_dbg(&adap->dev, "set i2c 7 bit address mode\n");  in intel_mid_i2c_setup()
650 			writel(reg & ~ADDR_10BIT, i2c->base + IC_CON);  in intel_mid_i2c_setup()
654 	reg = readl(i2c->base + IC_CON);  in intel_mid_i2c_setup()
657 		writel(reg | RESTART, i2c->base + IC_CON);  in intel_mid_i2c_setup()
661 	reg = readl(i2c->base + IC_CON);  in intel_mid_i2c_setup()
663 	writel(reg | MASTER_EN, i2c->base + IC_CON);  in intel_mid_i2c_setup()
666 		writel(reg | SLV_DIS, i2c->base + IC_CON);  in intel_mid_i2c_setup()
671 	reg = readl(i2c->base + IC_TAR);  in intel_mid_i2c_setup()
677 		writel(reg & ~bit_mask, i2c->base + IC_TAR);  in intel_mid_i2c_setup()
680 	/* set target address to the I2C slave address */  in intel_mid_i2c_setup()
682 		"set target address to the I2C slave address, addr is %x\n",  in intel_mid_i2c_setup()
685 		i2c->base + IC_TAR);  in intel_mid_i2c_setup()
687 	/* Enable I2C controller */  in intel_mid_i2c_setup()
688 	writel(ENABLE, i2c->base + IC_ENABLE);  in intel_mid_i2c_setup()
701  * -ETIMEDOUT	If cannot disable I2C controller or read IC_STATUS
704  * This function will be registered in i2c-core and exposed to external
705  * I2C clients.
706  * 1. Disable I2C controller
709  * 4. Enable I2C controller
718 	struct intel_mid_i2c_private *i2c = i2c_get_adapdata(adap);  in intel_mid_i2c_xfer()  local
725 	pm_runtime_get(i2c->dev);  in intel_mid_i2c_xfer()
727 	mutex_lock(&i2c->lock);  in intel_mid_i2c_xfer()
732 	if (i2c->status != STATUS_IDLE) {  in intel_mid_i2c_xfer()
735 		mutex_unlock(&i2c->lock);  in intel_mid_i2c_xfer()
736 		pm_runtime_put(i2c->dev);  in intel_mid_i2c_xfer()
745 			mutex_unlock(&i2c->lock);  in intel_mid_i2c_xfer()
746 			pm_runtime_put(i2c->dev);  in intel_mid_i2c_xfer()
752 		mutex_unlock(&i2c->lock);  in intel_mid_i2c_xfer()
753 		pm_runtime_put(i2c->dev);  in intel_mid_i2c_xfer()
758 		i2c->msg = pmsg;  in intel_mid_i2c_xfer()
759 		i2c->status = STATUS_IDLE;  in intel_mid_i2c_xfer()
775 	writel(0x0000, i2c->base + IC_INTR_MASK);  in intel_mid_i2c_xfer()
777 	readl(i2c->base + IC_CLR_INTR);  in intel_mid_i2c_xfer()
779 	i2c->status = STATUS_IDLE;  in intel_mid_i2c_xfer()
780 	mutex_unlock(&i2c->lock);  in intel_mid_i2c_xfer()
781 	pm_runtime_put(i2c->dev);  in intel_mid_i2c_xfer()
789 	struct intel_mid_i2c_private *i2c = pci_get_drvdata(pdev);  in intel_mid_i2c_runtime_suspend()  local
793 	if (i2c->status != STATUS_IDLE)  in intel_mid_i2c_runtime_suspend()
809 	i2c->status = STATUS_STANDBY;  in intel_mid_i2c_runtime_suspend()
817 	struct intel_mid_i2c_private *i2c = pci_get_drvdata(pdev);  in intel_mid_i2c_runtime_resume()  local
820 	if (i2c->status != STATUS_STANDBY)  in intel_mid_i2c_runtime_resume()
831 	i2c->status = STATUS_IDLE;  in intel_mid_i2c_runtime_resume()
833 	intel_mid_i2c_hwinit(i2c);  in intel_mid_i2c_runtime_resume()
837 static void i2c_isr_read(struct intel_mid_i2c_private *i2c)  in i2c_isr_read()  argument
839 	struct i2c_msg *msg = i2c->msg;  in i2c_isr_read()
847 	if (i2c->status != STATUS_READ_IN_PROGRESS) {  in i2c_isr_read()
851 		len = i2c->rx_buf_len;  in i2c_isr_read()
852 		buf = i2c->rx_buf;  in i2c_isr_read()
855 	rx_num = readl(i2c->base + IC_RXFLR);  in i2c_isr_read()
858 		*buf++ = readl(i2c->base + IC_DATA_CMD);  in i2c_isr_read()
861 		i2c->status = STATUS_READ_IN_PROGRESS;  in i2c_isr_read()
862 		i2c->rx_buf_len = len;  in i2c_isr_read()
863 		i2c->rx_buf = buf;  in i2c_isr_read()
865 		i2c->status = STATUS_READ_SUCCESS;  in i2c_isr_read()
872 	struct intel_mid_i2c_private *i2c = dev;  in intel_mid_i2c_isr()  local
873 	u32 stat = readl(i2c->base + IC_INTR_STAT);  in intel_mid_i2c_isr()
878 	dev_dbg(&i2c->adap.dev, "%s, stat = 0x%x\n", __func__, stat);  in intel_mid_i2c_isr()
881 	if (i2c->status != STATUS_WRITE_START &&  in intel_mid_i2c_isr()
882 	    i2c->status != STATUS_READ_START &&  in intel_mid_i2c_isr()
883 	    i2c->status != STATUS_READ_IN_PROGRESS)  in intel_mid_i2c_isr()
887 		i2c->abort = readl(i2c->base + IC_TX_ABRT_SOURCE);  in intel_mid_i2c_isr()
889 	readl(i2c->base + IC_CLR_INTR);  in intel_mid_i2c_isr()
892 		intel_mid_i2c_abort(i2c);  in intel_mid_i2c_isr()
897 		i2c_isr_read(i2c);  in intel_mid_i2c_isr()
902 		if (readl(i2c->base + IC_STATUS) & 0x4)  in intel_mid_i2c_isr()
903 			i2c->status = STATUS_WRITE_SUCCESS;  in intel_mid_i2c_isr()
907 	if (i2c->status == STATUS_READ_SUCCESS ||  in intel_mid_i2c_isr()
908 	    i2c->status == STATUS_WRITE_SUCCESS ||  in intel_mid_i2c_isr()
909 	    i2c->status == STATUS_XFER_ABORT) {  in intel_mid_i2c_isr()
911 		readl(i2c->base + IC_CLR_INTR);  in intel_mid_i2c_isr()
913 		writel(0, i2c->base + IC_INTR_MASK);  in intel_mid_i2c_isr()
914 		complete(&i2c->complete);  in intel_mid_i2c_isr()
932  * intel_mid_i2c_probe - I2C controller initialization routine
948  * 6. Register I2C adapter in i2c-core
958 	dev_dbg(&dev->dev, "Get into probe function for I2C\n");  in intel_mid_i2c_probe()
961 		dev_err(&dev->dev, "Failed to enable I2C PCI device (%d)\n",  in intel_mid_i2c_probe()
966 	/* Determine the address of the I2C area */  in intel_mid_i2c_probe()
974 	dev_dbg(&dev->dev, "%s i2c resource start 0x%lx, len=%ld\n",  in intel_mid_i2c_probe()
979 		dev_err(&dev->dev, "failed to request I2C region "  in intel_mid_i2c_probe()
1002 		"Intel MID I2C at %lx", start);  in intel_mid_i2c_probe()
1022 	dev_dbg(&dev->dev, "I2C%d\n", busnum);  in intel_mid_i2c_probe()
1032 	/* Initialize i2c controller */  in intel_mid_i2c_probe()
1035 		dev_err(&dev->dev, "I2C interface initialization failed\n");  in intel_mid_i2c_probe()
1049 		dev_err(&dev->dev, "Failed to request IRQ for I2C controller: "  in intel_mid_i2c_probe()
1062 	dev_dbg(&dev->dev, "%s I2C bus %d driver bind success.\n",  in intel_mid_i2c_probe()
1087 		dev_err(&dev->dev, "Failed to delete i2c adapter");  in intel_mid_i2c_remove()
1133 MODULE_DESCRIPTION("I2C driver for Moorestown Platform");