platforms/iseries/lpardata.c

63 struct ItLpRegSave {  struct
64 	u32	xDesc;		// Eye catcher  "LpRS" ebcdic	000-003
65 	u16	xSize;		// Size of this class		004-005
66 	u8	xInUse;         // Area is live                 006-007
67 	u8	xRsvd1[9];	// Reserved			007-00F
69 	u8      xFixedRegSave[352]; // Fixed Register Save Area 010-16F
70 	u32	xCTRL;		// Control Register		170-173
71 	u32	xDEC;		// Decrementer			174-177
72 	u32	xFPSCR;		// FP Status and Control Reg	178-17B
73 	u32	xPVR;		// Processor Version Number	17C-17F
75 	u64	xMMCR0;		// Monitor Mode Control Reg 0	180-187
76 	u32	xPMC1;		// Perf Monitor Counter 1	188-18B
77 	u32	xPMC2;		// Perf Monitor Counter 2	18C-18F
78 	u32	xPMC3;		// Perf Monitor Counter 3	190-193
79 	u32	xPMC4;		// Perf Monitor Counter 4	194-197
80 	u32	xPIR;		// Processor ID Reg		198-19B
82 	u32	xMMCR1;		// Monitor Mode Control Reg 1	19C-19F
83 	u32	xMMCRA;		// Monitor Mode Control Reg A	1A0-1A3
84 	u32	xPMC5;		// Perf Monitor Counter 5	1A4-1A7
85 	u32	xPMC6;		// Perf Monitor Counter 6	1A8-1AB
86 	u32	xPMC7;		// Perf Monitor Counter 7	1AC-1AF
87 	u32	xPMC8;		// Perf Monitor Counter 8	1B0-1B3
88 	u32	xTSC;		// Thread Switch Control	1B4-1B7
89 	u32	xTST;		// Thread Switch Timeout	1B8-1BB
90 	u32	xRsvd;          // Reserved                     1BC-1BF
92 	u64	xACCR;		// Address Compare Control Reg	1C0-1C7
93 	u64	xIMR;		// Instruction Match Register	1C8-1CF
94 	u64	xSDR1;		// Storage Description Reg 1	1D0-1D7
95 	u64	xSPRG0;		// Special Purpose Reg General0	1D8-1DF
96 	u64	xSPRG1;		// Special Purpose Reg General1	1E0-1E7
97 	u64	xSPRG2;		// Special Purpose Reg General2	1E8-1EF
98 	u64	xSPRG3;		// Special Purpose Reg General3	1F0-1F7
99 	u64	xTB;		// Time Base Register		1F8-1FF
101 	u64	xFPR[32];	// Floating Point Registers	200-2FF
103 	u64	xMSR;		// Machine State Register	300-307
104 	u64	xNIA;		// Next Instruction Address	308-30F
106 	u64	xDABR;		// Data Address Breakpoint Reg	310-317
107 	u64	xIABR;		// Inst Address Breakpoint Reg	318-31F
109 	u64	xHID0;		// HW Implementation Dependent0	320-327
111 	u64	xHID4;		// HW Implementation Dependent4	328-32F
112 	u64	xSCOMd;		// SCON Data Reg (SPRG4)	330-337
113 	u64	xSCOMc;		// SCON Command Reg (SPRG5)	338-33F
114 	u64	xSDAR;		// Sample Data Address Register	340-347
115 	u64	xSIAR;		// Sample Inst Address Register	348-34F
117 	u8	xRsvd3[176];	// Reserved			350-3FF