17 	set_irq_line(line, 1);  in toggle_irq_line()
82 	report(g_isr_76 == 1, "edge triggered intr");  in test_ioapic_edge_intr()
98 	set_irq_line(0x0e, 1);  in test_ioapic_level_intr()
100 	report(g_isr_77 == 1, "level triggered intr");  in test_ioapic_level_intr()
136 static volatile int g_tmr_79 = -1;
166 	set_irq_line(0x0e, 1);  in test_ioapic_level_tmr()
186 	g_tmr_79 = -1;  in test_ioapic_edge_tmr_smp()
190 	on_cpu_async(1, toggle_irq_line_0x0e, 0);  in test_ioapic_edge_tmr_smp()
192 	while(g_tmr_79 == -1) i++;  in test_ioapic_edge_tmr_smp()
203 	set_irq_line(0x0e, 1);  in set_irq_line_0x0e()
211 	g_tmr_79 = -1;  in test_ioapic_level_tmr_smp()
215 	on_cpu_async(1, set_irq_line_0x0e, 0);  in test_ioapic_level_tmr_smp()
217 	while(g_tmr_79 == -1) i++;  in test_ioapic_level_tmr_smp()
230 	if (g_isr_98 == 1) {  in ioapic_isr_98()
232 		set_irq_line(0x0e, 1);  in ioapic_isr_98()
242 	set_irq_line(0x0e, 1);  in test_ioapic_level_coalesce()
244 	report(g_isr_98 == 1, "coalesce simultaneous level interrupts");  in test_ioapic_level_coalesce()
260 	set_irq_line(0x0e, 1);  in test_ioapic_level_sequential()
261 	set_irq_line(0x0e, 1);  in test_ioapic_level_sequential()
284 	set_irq_line(0x0e, 1);  in test_ioapic_level_retrigger()
313 	set_irq_line(0x0e, 1);  in test_ioapic_edge_mask()
320 	set_irq_line(0x0e, 1);  in test_ioapic_edge_mask()
323 	report(g_isr_81 == 1, "unmasked level interrupt");  in test_ioapic_edge_mask()
341 	set_irq_line(0x0e, 1);  in test_ioapic_level_mask()
349 	report(g_isr_82 == 1, "unmasked level interrupt");  in test_ioapic_level_mask()
366 	set_irq_line(0x0e, 1);  in test_ioapic_level_retrigger_mask()
385 	report(e.remote_irr == 1, "Reconfigure Remote IRR set");  in ioapic_reconfigure_dest()
387 	e.dest_id = 1;  in ioapic_reconfigure_dest()
391 	ioapic_write_reg(0x10 + line * 2 + 1, ((u32 *)&e)[1]);  in ioapic_reconfigure_dest()
402 	set_irq_line(0x0e, 1);  in ioapic_isr_64()
442 	set_irq_line(0x0d, 1);  in test_ioapic_self_reconfigure()
445 	report(g_isr_84 == 1 && e.remote_irr == 0, "Reconfigure self highest priority");  in test_ioapic_self_reconfigure()
448 	report(g_isr_64 == 1 && d.remote_irr == 0, "Reconfigure self lower priority");  in test_ioapic_self_reconfigure()
474 	set_irq_line(0x0e, 1);  in test_ioapic_physical_destination_mode()
477 	} while(g_isr_85 != 1);  in test_ioapic_physical_destination_mode()
478 	report(g_isr_85 == 1, "ioapic physical destination mode");  in test_ioapic_physical_destination_mode()
501 		.dest_mode = 1,  in test_ioapic_logical_destination_mode()
507 	set_irq_line(0x0e, 1);  in test_ioapic_logical_destination_mode()
550 	if (cpu_count() > 1)  in main()
555 	if (cpu_count() > 1) {  in main()