18 	set_irq_line(line, 0);  in toggle_irq_line()
26 	version_offset = 0x01;  in ioapic_reg_version()
28 	data_write = data_read ^ 0xffffffff;  in ioapic_reg_version()
40 	id_offset = 0x0;  in ioapic_reg_id()
42 	data_write = data_read ^ 0xffffffff;  in ioapic_reg_id()
47 	report(diff == 0x0f000000, "id register only bits [24:27] writable");  in ioapic_reg_id()
55 	id_offset = 0x0;  in ioapic_arbitration_id()
56 	arb_offset = 0x2;  in ioapic_arbitration_id()
57 	write = 0x0f000000;  in ioapic_arbitration_id()
63 	ioapic_write_reg(arb_offset, 0x0);  in ioapic_arbitration_id()
78 	handle_irq(0x76, ioapic_isr_76);  in test_ioapic_edge_intr()
79 	ioapic_set_redir(0x0e, 0x76, TRIGGER_EDGE);  in test_ioapic_edge_intr()
80 	toggle_irq_line(0x0e);  in test_ioapic_edge_intr()
90 	set_irq_line(0x0e, 0);  in ioapic_isr_77()
96 	handle_irq(0x77, ioapic_isr_77);  in test_ioapic_level_intr()
97 	ioapic_set_redir(0x0e, 0x77, TRIGGER_LEVEL);  in test_ioapic_level_intr()
98 	set_irq_line(0x0e, 1);  in test_ioapic_level_intr()
124 	handle_irq(0x78, ioapic_isr_78);  in test_ioapic_simultaneous()
125 	handle_irq(0x66, ioapic_isr_66);  in test_ioapic_simultaneous()
126 	ioapic_set_redir(0x0e, 0x78, TRIGGER_EDGE);  in test_ioapic_simultaneous()
127 	ioapic_set_redir(0x0f, 0x66, TRIGGER_EDGE);  in test_ioapic_simultaneous()
129 	toggle_irq_line(0x0f);  in test_ioapic_simultaneous()
130 	toggle_irq_line(0x0e);  in test_ioapic_simultaneous()
140 	g_tmr_79 = apic_read_bit(APIC_TMR, 0x79);  in ioapic_isr_79()
141 	set_irq_line(0x0e, 0);  in ioapic_isr_79()
149 	handle_irq(0x79, ioapic_isr_79);  in test_ioapic_edge_tmr()
150 	ioapic_set_redir(0x0e, 0x79, TRIGGER_EDGE);  in test_ioapic_edge_tmr()
151 	tmr_before = apic_read_bit(APIC_TMR, 0x79);  in test_ioapic_edge_tmr()
152 	toggle_irq_line(0x0e);  in test_ioapic_edge_tmr()
163 	handle_irq(0x79, ioapic_isr_79);  in test_ioapic_level_tmr()
164 	ioapic_set_redir(0x0e, 0x79, TRIGGER_LEVEL);  in test_ioapic_level_tmr()
165 	tmr_before = apic_read_bit(APIC_TMR, 0x79);  in test_ioapic_level_tmr()
166 	set_irq_line(0x0e, 1);  in test_ioapic_level_tmr()
177 	toggle_irq_line(0x0e);  in toggle_irq_line_0x0e()
187 	handle_irq(0x79, ioapic_isr_79);  in test_ioapic_edge_tmr_smp()
188 	ioapic_set_redir(0x0e, 0x79, TRIGGER_EDGE);  in test_ioapic_edge_tmr_smp()
189 	tmr_before = apic_read_bit(APIC_TMR, 0x79);  in test_ioapic_edge_tmr_smp()
190 	on_cpu_async(1, toggle_irq_line_0x0e, 0);  in test_ioapic_edge_tmr_smp()
191 	i = 0;  in test_ioapic_edge_tmr_smp()
203 	set_irq_line(0x0e, 1);  in set_irq_line_0x0e()
212 	handle_irq(0x79, ioapic_isr_79);  in test_ioapic_level_tmr_smp()
213 	ioapic_set_redir(0x0e, 0x79, TRIGGER_LEVEL);  in test_ioapic_level_tmr_smp()
214 	tmr_before = apic_read_bit(APIC_TMR, 0x79);  in test_ioapic_level_tmr_smp()
215 	on_cpu_async(1, set_irq_line_0x0e, 0);  in test_ioapic_level_tmr_smp()
216 	i = 0;  in test_ioapic_level_tmr_smp()
222 	poll_remote_irr(0xe);  in test_ioapic_level_tmr_smp()
231 		set_irq_line(0x0e, 0);  in ioapic_isr_98()
232 		set_irq_line(0x0e, 1);  in ioapic_isr_98()
234 	set_irq_line(0x0e, 0);  in ioapic_isr_98()
240 	handle_irq(0x98, ioapic_isr_98);  in test_ioapic_level_coalesce()
241 	ioapic_set_redir(0x0e, 0x98, TRIGGER_LEVEL);  in test_ioapic_level_coalesce()
242 	set_irq_line(0x0e, 1);  in test_ioapic_level_coalesce()
252 	set_irq_line(0x0e, 0);  in ioapic_isr_99()
258 	handle_irq(0x99, ioapic_isr_99);  in test_ioapic_level_sequential()
259 	ioapic_set_redir(0x0e, 0x99, TRIGGER_LEVEL);  in test_ioapic_level_sequential()
260 	set_irq_line(0x0e, 1);  in test_ioapic_level_sequential()
261 	set_irq_line(0x0e, 1);  in test_ioapic_level_sequential()
272 		set_irq_line(0x0e, 0);  in ioapic_isr_9a()
280 	handle_irq(0x9a, ioapic_isr_9a);  in test_ioapic_level_retrigger()
281 	ioapic_set_redir(0x0e, 0x9a, TRIGGER_LEVEL);  in test_ioapic_level_retrigger()
284 	set_irq_line(0x0e, 1);  in test_ioapic_level_retrigger()
286 	for (i = 0; i < 10; i++) {  in test_ioapic_level_retrigger()
303 	set_irq_line(0x0e, 0);  in ioapic_isr_81()
309 	handle_irq(0x81, ioapic_isr_81);  in test_ioapic_edge_mask()
310 	ioapic_set_redir(0x0e, 0x81, TRIGGER_EDGE);  in test_ioapic_edge_mask()
312 	set_mask(0x0e, true);  in test_ioapic_edge_mask()
313 	set_irq_line(0x0e, 1);  in test_ioapic_edge_mask()
314 	set_irq_line(0x0e, 0);  in test_ioapic_edge_mask()
317 	report(g_isr_81 == 0, "masked level interrupt");  in test_ioapic_edge_mask()
319 	set_mask(0x0e, false);  in test_ioapic_edge_mask()
320 	set_irq_line(0x0e, 1);  in test_ioapic_edge_mask()
331 	set_irq_line(0x0e, 0);  in ioapic_isr_82()
337 	handle_irq(0x82, ioapic_isr_82);  in test_ioapic_level_mask()
338 	ioapic_set_redir(0x0e, 0x82, TRIGGER_LEVEL);  in test_ioapic_level_mask()
340 	set_mask(0x0e, true);  in test_ioapic_level_mask()
341 	set_irq_line(0x0e, 1);  in test_ioapic_level_mask()
344 	report(g_isr_82 == 0, "masked level interrupt");  in test_ioapic_level_mask()
346 	set_mask(0x0e, false);  in test_ioapic_level_mask()
357 	set_mask(0x0e, true);  in ioapic_isr_83()
363 	handle_irq(0x83, ioapic_isr_83);  in test_ioapic_level_retrigger_mask()
364 	ioapic_set_redir(0x0e, 0x83, TRIGGER_LEVEL);  in test_ioapic_level_retrigger_mask()
366 	set_irq_line(0x0e, 1);  in test_ioapic_level_retrigger_mask()
368 	set_mask(0x0e, false);  in test_ioapic_level_retrigger_mask()
372 	set_irq_line(0x0e, 0);  in test_ioapic_level_retrigger_mask()
373 	set_mask(0x0e, false);  in test_ioapic_level_retrigger_mask()
380 	int line = 0xe;  in ioapic_isr_84()
384 	set_irq_line(line, 0);  in ioapic_isr_84()
391 	ioapic_write_reg(0x10 + line * 2 + 1, ((u32 *)&e)[1]);  in ioapic_isr_84()
399 		.vector = 0x84,  in test_ioapic_self_reconfigure()
400 		.delivery_mode = 0,  in test_ioapic_self_reconfigure()
401 		.dest_mode = 0,  in test_ioapic_self_reconfigure()
402 		.dest_id = 0,  in test_ioapic_self_reconfigure()
406 	handle_irq(0x84, ioapic_isr_84);  in test_ioapic_self_reconfigure()
407 	ioapic_write_redir(0xe, e);  in test_ioapic_self_reconfigure()
408 	set_irq_line(0x0e, 1);  in test_ioapic_self_reconfigure()
409 	e = ioapic_read_redir(0xe);  in test_ioapic_self_reconfigure()
410 	report(g_isr_84 == 1 && e.remote_irr == 0, "Reconfigure self");  in test_ioapic_self_reconfigure()
411 	poll_remote_irr(0xe);  in test_ioapic_self_reconfigure()
419 	set_irq_line(0x0e, 0);  in ioapic_isr_85()
426 		.vector = 0x85,  in test_ioapic_physical_destination_mode()
427 		.delivery_mode = 0,  in test_ioapic_physical_destination_mode()
428 		.dest_mode = 0,  in test_ioapic_physical_destination_mode()
429 		.dest_id = 0x1,  in test_ioapic_physical_destination_mode()
432 	handle_irq(0x85, ioapic_isr_85);  in test_ioapic_physical_destination_mode()
433 	ioapic_write_redir(0xe, e);  in test_ioapic_physical_destination_mode()
434 	set_irq_line(0x0e, 1);  in test_ioapic_physical_destination_mode()
439 	poll_remote_irr(0xe);  in test_ioapic_physical_destination_mode()
450 	set_irq_line(0x0e, 0);  in ioapic_isr_86()
459 		.vector = 0x86,  in test_ioapic_logical_destination_mode()
460 		.delivery_mode = 0,  in test_ioapic_logical_destination_mode()
462 		.dest_id = 0xd,  in test_ioapic_logical_destination_mode()
465 	handle_irq(0x86, ioapic_isr_86);  in test_ioapic_logical_destination_mode()
466 	ioapic_write_redir(0xe, e);  in test_ioapic_logical_destination_mode()
467 	set_irq_line(0x0e, 1);  in test_ioapic_logical_destination_mode()
472 	poll_remote_irr(0xe);  in test_ioapic_logical_destination_mode()