riscv/vmm: Initial import.

Add kernel code for 'H' — Hypervisor Extension[1] to support
virtualization on RISC-V ISA.

This comes with a separate userspace patch allowing us to boot
unmodified freeb

riscv/vmm: Initial import.

Add kernel code for 'H' — Hypervisor Extension[1] to support
virtualization on RISC-V ISA.

This comes with a separate userspace patch allowing us to boot
unmodified freebsd/riscv guest. Other operating systems are untested.

This also comes with a U-Boot port that is configured to run in bhyve
guest environment — in RISC-V virtual supervisor mode.
The vmm SBI code emulates RISC-V machine-mode for the guest, handling
SBI calls partly in vmm kernel and partly in bhyve userspace.

Developed in Spike simulator during short period of time, the support
is considered experimental. The first real hardware with hypervisor
spec included should have just reached the market, so this was tested
in Spike and QEMU only. Note that this depends on Sstc extension
presence in the hardware (both Spike and QEMU have it).

Note that booting multiple guests at the same time is not tested and
may require additional work. Some TODOs are indicated within the
code, and some listed in the project's home page[2].

Many thanks to Jessica Clarke, Mitchell Horne and Mark Johnston
for help with parts, test and review.

1. https://riscv.org/technical/specifications/
2. https://wiki.freebsd.org/riscv/bhyve

Sponsored by: UK Research and Innovation
Differential Revision: https://reviews.freebsd.org/D45553

show more ...

riscv: Recognise B extension for AT_HWCAP

This was ratified earlier this year as an alias for Zba_Zbb_Zbs. Whilst
we don't currently export multi-letter extensions, we can still export
this alias in

riscv: Recognise B extension for AT_HWCAP

This was ratified earlier this year as an alias for Zba_Zbb_Zbs. Whilst
we don't currently export multi-letter extensions, we can still export
this alias in AT_HWCAP.

Reviewed by: mhorne
MFC after: 1 month
Differential Revision: https://reviews.freebsd.org/D46277

show more ...

sys: Remove $FreeBSD$: two-line .h pattern

Remove /^\s*\*\n \*\s+\$FreeBSD\$$\n/

riscv: improve parsing of riscv,isa property strings

This code was originally written under the assumption that the ISA
string would only contain single-letter extensions. The RISC-V
specification h

riscv: improve parsing of riscv,isa property strings

This code was originally written under the assumption that the ISA
string would only contain single-letter extensions. The RISC-V
specification has extended its description of the format quite a bit,
allowing for much longer ISA strings containing multi-letter extension
names.

Newer versions of QEMU (7.1.0) will append to the riscv,isa property
indicating the presence of multi-letter standard extensions such as
Zfencei. This triggers a KASSERT about the expected length of the
string, preventing boot.

Increase the size of the isa array significantly, and teach the code
to parse (skip over) multi-letter extensions, and optional extension
version numbers. We currently ignore them completely, but this will
change in the future as we start supporting supervisor-level extensions.

MFC after: 2 weeks
Sponsored by: The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D36601

show more ...

MFHead @349234

Sponsored by: The FreeBSD Foundation

RISC-V: expose extension bits in AT_HWCAP

AT_HWCAP is a field in the elf auxiliary vector meant to describe
cpu-specific hardware features. For RISC-V we want to use this to
indicate the presence of

RISC-V: expose extension bits in AT_HWCAP

AT_HWCAP is a field in the elf auxiliary vector meant to describe
cpu-specific hardware features. For RISC-V we want to use this to
indicate the presence of any standard extensions supported by the CPU.
This allows userland applications to query the system for supported
extensions using elf_aux_info(3).

Support for an extension is indicated by the presence of its
corresponding bit in AT_HWCAP -- e.g. systems supporting the 'c'
extension (compressed instructions) will have the second bit set.

Extensions advertised through AT_HWCAP are only those that are supported
by all harts in the system.

Reviewed by: jhb, markj
Approved by: markj (mentor)
MFC after: 2 weeks
Differential Revision: https://reviews.freebsd.org/D20493

show more ...

Merge ^/head r339015 through r339669.

Consolidate identical ELF auxargs type defintions.

All platforms except powerpc use the same values and powerpc shares a
majority of them.

Go ahead and declare AT_NOTELF, AT_UID, and AT_EUID in fav

Consolidate identical ELF auxargs type defintions.

All platforms except powerpc use the same values and powerpc shares a
majority of them.

Go ahead and declare AT_NOTELF, AT_UID, and AT_EUID in favor of the
unused AT_DCACHEBSIZE, AT_ICACHEBSIZE, and AT_UCACHEBSIZE for powerpc.

Reviewed by: jhb, imp
Sponsored by: DARPA, AFRL
Differential Revision: https://reviews.freebsd.org/D17397

show more ...

riscv/vmm: Initial import.

Add kernel code for 'H' — Hypervisor Extension[1] to support
virtualization on RISC-V ISA.

This comes with a separate userspace patch allowing us to boot
unmodified freeb

riscv/vmm: Initial import.

Add kernel code for 'H' — Hypervisor Extension[1] to support
virtualization on RISC-V ISA.

This comes with a separate userspace patch allowing us to boot
unmodified freebsd/riscv guest. Other operating systems are untested.

This also comes with a U-Boot port that is configured to run in bhyve
guest environment — in RISC-V virtual supervisor mode.
The vmm SBI code emulates RISC-V machine-mode for the guest, handling
SBI calls partly in vmm kernel and partly in bhyve userspace.

Developed in Spike simulator during short period of time, the support
is considered experimental. The first real hardware with hypervisor
spec included should have just reached the market, so this was tested
in Spike and QEMU only. Note that this depends on Sstc extension
presence in the hardware (both Spike and QEMU have it).

Note that booting multiple guests at the same time is not tested and
may require additional work. Some TODOs are indicated within the
code, and some listed in the project's home page[2].

Many thanks to Jessica Clarke, Mitchell Horne and Mark Johnston
for help with parts, test and review.

1. https://riscv.org/technical/specifications/
2. https://wiki.freebsd.org/riscv/bhyve

Sponsored by: UK Research and Innovation
Differential Revision: https://reviews.freebsd.org/D45553

show more ...

riscv: Recognise B extension for AT_HWCAP

This was ratified earlier this year as an alias for Zba_Zbb_Zbs. Whilst
we don't currently export multi-letter extensions, we can still export
this alias in

riscv: Recognise B extension for AT_HWCAP

This was ratified earlier this year as an alias for Zba_Zbb_Zbs. Whilst
we don't currently export multi-letter extensions, we can still export
this alias in AT_HWCAP.

Reviewed by: mhorne
MFC after: 1 month
Differential Revision: https://reviews.freebsd.org/D46277

show more ...

sys: Remove $FreeBSD$: two-line .h pattern

Remove /^\s*\*\n \*\s+\$FreeBSD\$$\n/

riscv: improve parsing of riscv,isa property strings

This code was originally written under the assumption that the ISA
string would only contain single-letter extensions. The RISC-V
specification h

riscv: improve parsing of riscv,isa property strings

This code was originally written under the assumption that the ISA
string would only contain single-letter extensions. The RISC-V
specification has extended its description of the format quite a bit,
allowing for much longer ISA strings containing multi-letter extension
names.

Newer versions of QEMU (7.1.0) will append to the riscv,isa property
indicating the presence of multi-letter standard extensions such as
Zfencei. This triggers a KASSERT about the expected length of the
string, preventing boot.

Increase the size of the isa array significantly, and teach the code
to parse (skip over) multi-letter extensions, and optional extension
version numbers. We currently ignore them completely, but this will
change in the future as we start supporting supervisor-level extensions.

MFC after: 2 weeks
Sponsored by: The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D36601

show more ...

MFHead @349234

Sponsored by: The FreeBSD Foundation

RISC-V: expose extension bits in AT_HWCAP

AT_HWCAP is a field in the elf auxiliary vector meant to describe
cpu-specific hardware features. For RISC-V we want to use this to
indicate the presence of

RISC-V: expose extension bits in AT_HWCAP

AT_HWCAP is a field in the elf auxiliary vector meant to describe
cpu-specific hardware features. For RISC-V we want to use this to
indicate the presence of any standard extensions supported by the CPU.
This allows userland applications to query the system for supported
extensions using elf_aux_info(3).

Support for an extension is indicated by the presence of its
corresponding bit in AT_HWCAP -- e.g. systems supporting the 'c'
extension (compressed instructions) will have the second bit set.

Extensions advertised through AT_HWCAP are only those that are supported
by all harts in the system.

Reviewed by: jhb, markj
Approved by: markj (mentor)
MFC after: 2 weeks
Differential Revision: https://reviews.freebsd.org/D20493

show more ...

Merge ^/head r339015 through r339669.

Consolidate identical ELF auxargs type defintions.

All platforms except powerpc use the same values and powerpc shares a
majority of them.

Go ahead and declare AT_NOTELF, AT_UID, and AT_EUID in fav

Consolidate identical ELF auxargs type defintions.

All platforms except powerpc use the same values and powerpc shares a
majority of them.

Go ahead and declare AT_NOTELF, AT_UID, and AT_EUID in favor of the
unused AT_DCACHEBSIZE, AT_ICACHEBSIZE, and AT_UCACHEBSIZE for powerpc.

Reviewed by: jhb, imp
Sponsored by: DARPA, AFRL
Differential Revision: https://reviews.freebsd.org/D17397

show more ...

Merge ^/head r323559 through r325504.

MFhead@r324837

While here, diff reduce some of the changes in sys/boot by moving
MK_COVERAGE=no to sys/boot/Makefile.inc .

Add AT_HWCAP2 ELF auxiliary vector.
- allocate value for new AT_HWCAP2 auxiliary vector on all platforms.
- expand 'struct sysentvec' by new 'u_long *sv_hwcap2', in exactly
same way as for AT_HW

Add AT_HWCAP2 ELF auxiliary vector.
- allocate value for new AT_HWCAP2 auxiliary vector on all platforms.
- expand 'struct sysentvec' by new 'u_long *sv_hwcap2', in exactly
same way as for AT_HWCAP.

MFC after: 1 month
Reviewed by: kib
Differential Revision: https://reviews.freebsd.org/D12699

show more ...

MFhead@r323635

Add AT_HWCAP and AT_EHDRFLAGS on all platforms.

A new 'u_long *sv_hwcap' field is added to 'struct sysentvec'. A
process ABI can set this field to point to a value holding a mask of
architecture-sp

Add AT_HWCAP and AT_EHDRFLAGS on all platforms.

A new 'u_long *sv_hwcap' field is added to 'struct sysentvec'. A
process ABI can set this field to point to a value holding a mask of
architecture-specific CPU feature flags. If an ABI does not wish to
supply AT_HWCAP to processes the field can be left as NULL.

The support code for AT_EHDRFLAGS was already present on all systems,
just the #define was not present. This is a step towards unifying the
AT_* constants across platforms.

Reviewed by: kib
MFC after: 1 month
Differential Revision: https://reviews.freebsd.org/D12290

show more ...

MFH r289384-r293170

Sponsored by: The FreeBSD Foundation

MFH @r292599

This includes the pluggable TCP framework and other chnages to the
netstack to track for VNET stability.

Security: The FreeBSD Foundation

Import RISC-V machine headers. This is a minimal set required to compile
kernel and userland.

Reviewed by: andrew, imp, kib
Sponsored by: DARPA, AFRL
Sponsored by: HEIF5
Differential Revision: https

Import RISC-V machine headers. This is a minimal set required to compile
kernel and userland.

Reviewed by: andrew, imp, kib
Sponsored by: DARPA, AFRL
Sponsored by: HEIF5
Differential Revision: https://reviews.freebsd.org/D4554

show more ...

Merge ^/head r323559 through r325504.