| #
44423107 |
| 24-Aug-2020 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/xtensa/tags/20200821-xtensa' into staging
target/xtensa updates for 5.2:
- add NMI support;
- add DFPU option implementation;
- update FPU tests to support bot
Merge remote-tracking branch 'remotes/xtensa/tags/20200821-xtensa' into staging
target/xtensa updates for 5.2:
- add NMI support;
- add DFPU option implementation;
- update FPU tests to support both FPU2000 and DFPU;
- add example cores with FPU2000 and DFPU.
# gpg: Signature made Fri 21 Aug 2020 21:09:37 BST
# gpg: using RSA key 2B67854B98E5327DCDEB17D851F9CC91F83FA044
# gpg: issuer "jcmvbkbc@gmail.com"
# gpg: Good signature from "Max Filippov <filippov@cadence.com>" [unknown]
# gpg: aka "Max Filippov <max.filippov@cogentembedded.com>" [full]
# gpg: aka "Max Filippov <jcmvbkbc@gmail.com>" [full]
# Primary key fingerprint: 2B67 854B 98E5 327D CDEB 17D8 51F9 CC91 F83F A044
* remotes/xtensa/tags/20200821-xtensa: (24 commits)
target/xtensa: import DSP3400 core
target/xtensa: import de233_fpu core
tests/tcg/xtensa: add DFP0 arithmetic tests
tests/tcg/xtensa: test double precision load/store
tests/tcg/xtensa: add fp0 div and sqrt tests
tests/tcg/xtensa: update test_lsc for DFPU
tests/tcg/xtensa: update test_fp1 for DFPU
tests/tcg/xtensa: update test_fp0_conv for DFPU
tests/tcg/xtensa: expand madd tests
tests/tcg/xtensa: update test_fp0_arith for DFPU
tests/tcg/xtensa: fix test execution on ISS
target/xtensa: implement FPU division and square root
target/xtensa: add DFPU registers and opcodes
target/xtensa: add DFPU option
target/xtensa: don't access BR regfile directly
target/xtensa: move FSR/FCR register accessors
target/xtensa: rename FPU2000 translators and helpers
target/xtensa: support copying registers up to 64 bits wide
target/xtensa: add geometry to xtensa_get_regfile_by_name
softfloat: add xtensa specialization for pickNaNMulAdd
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
show more ...
|
| #
7f4faa21 |
| 04-Jul-2020 |
Max Filippov <jcmvbkbc@gmail.com> |
tests/tcg/xtensa: update test_fp1 for DFPU
DFPU sets Invalid flag in FSR when at least one argument of FP
comparison opcodes is NaN, SNaN for most opcodes, any NaN for olt/ole.
Add checks for FSR an
tests/tcg/xtensa: update test_fp1 for DFPU
DFPU sets Invalid flag in FSR when at least one argument of FP
comparison opcodes is NaN, SNaN for most opcodes, any NaN for olt/ole.
Add checks for FSR and expected FSR values.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
show more ...
|
| #
41795758 |
| 28-Feb-2019 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/xtensa/tags/20190228-xtensa' into staging
target/xtensa: FLIX support, various fixes and test improvements
- add FLIX (flexible length instructions extension)
Merge remote-tracking branch 'remotes/xtensa/tags/20190228-xtensa' into staging
target/xtensa: FLIX support, various fixes and test improvements
- add FLIX (flexible length instructions extension) support;
- make testsuite runnable on wider range of xtensa cores;
- add floating point opcode tests;
- don't add duplicate 'static' in import_core.sh script;
- fix undefined opcodes detection in test_mmuhifi_c3 overlay.
# gpg: Signature made Thu 28 Feb 2019 12:53:23 GMT
# gpg: using RSA key 2B67854B98E5327DCDEB17D851F9CC91F83FA044
# gpg: issuer "jcmvbkbc@gmail.com"
# gpg: Good signature from "Max Filippov <filippov@cadence.com>" [unknown]
# gpg: aka "Max Filippov <max.filippov@cogentembedded.com>" [full]
# gpg: aka "Max Filippov <jcmvbkbc@gmail.com>" [full]
# Primary key fingerprint: 2B67 854B 98E5 327D CDEB 17D8 51F9 CC91 F83F A044
* remotes/xtensa/tags/20190228-xtensa: (40 commits)
tests/tcg/xtensa: add FPU2000 coprocessor tests
tests/tcg/xtensa: add FP1 group tests
tests/tcg/xtensa: add FP0 group conversion tests
tests/tcg/xtensa: add FP0 group arithmetic tests
tests/tcg/xtensa: add LSCI/LSCX group tests
tests/tcg/xtensa: add test for FLIX
tests/tcg/xtensa: conditionalize MMU-related tests
tests/tcg/xtensa: conditionalize windowed register tests
tests/tcg/xtensa: conditionalize and fix s32c1i tests
tests/tcg/xtensa: fix SR tests for big endian configs
tests/tcg/xtensa: conditionalize and expand SR tests
tests/tcg/xtensa: conditionalize timer/CCOUNT tests
tests/tcg/xtensa: conditionalize interrupt tests
tests/tcg/xtensa: add straightforward conditionals
tests/tcg/xtensa: conditionalize cache option tests
tests/tcg/xtensa: conditionalize debug option tests
tests/tcg/xtensa: enable boolean tests
tests/tcg/xtensa: fix endianness issues in test_b
tests/tcg/xtensa: don't use optional opcodes in generic code
tests/tcg/xtensa: support configs with LITBASE
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
show more ...
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