Merge remote-tracking branch 'remotes/xtensa/tags/20190228-xtensa' into staging

target/xtensa: FLIX support, various fixes and test improvements

- add FLIX (flexible length instructions extension)

Merge remote-tracking branch 'remotes/xtensa/tags/20190228-xtensa' into staging

target/xtensa: FLIX support, various fixes and test improvements

- add FLIX (flexible length instructions extension) support;
- make testsuite runnable on wider range of xtensa cores;
- add floating point opcode tests;
- don't add duplicate 'static' in import_core.sh script;
- fix undefined opcodes detection in test_mmuhifi_c3 overlay.

# gpg: Signature made Thu 28 Feb 2019 12:53:23 GMT
# gpg: using RSA key 2B67854B98E5327DCDEB17D851F9CC91F83FA044
# gpg: issuer "jcmvbkbc@gmail.com"
# gpg: Good signature from "Max Filippov <filippov@cadence.com>" [unknown]
# gpg: aka "Max Filippov <max.filippov@cogentembedded.com>" [full]
# gpg: aka "Max Filippov <jcmvbkbc@gmail.com>" [full]
# Primary key fingerprint: 2B67 854B 98E5 327D CDEB 17D8 51F9 CC91 F83F A044

* remotes/xtensa/tags/20190228-xtensa: (40 commits)
tests/tcg/xtensa: add FPU2000 coprocessor tests
tests/tcg/xtensa: add FP1 group tests
tests/tcg/xtensa: add FP0 group conversion tests
tests/tcg/xtensa: add FP0 group arithmetic tests
tests/tcg/xtensa: add LSCI/LSCX group tests
tests/tcg/xtensa: add test for FLIX
tests/tcg/xtensa: conditionalize MMU-related tests
tests/tcg/xtensa: conditionalize windowed register tests
tests/tcg/xtensa: conditionalize and fix s32c1i tests
tests/tcg/xtensa: fix SR tests for big endian configs
tests/tcg/xtensa: conditionalize and expand SR tests
tests/tcg/xtensa: conditionalize timer/CCOUNT tests
tests/tcg/xtensa: conditionalize interrupt tests
tests/tcg/xtensa: add straightforward conditionals
tests/tcg/xtensa: conditionalize cache option tests
tests/tcg/xtensa: conditionalize debug option tests
tests/tcg/xtensa: enable boolean tests
tests/tcg/xtensa: fix endianness issues in test_b
tests/tcg/xtensa: don't use optional opcodes in generic code
tests/tcg/xtensa: support configs with LITBASE
...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...

tests/tcg/xtensa: support configurations w/o vecbase

Configurations w/o vecbase may have vectors not grouped together and not
in fixed order. They may not always be grouped into single output
sectio

tests/tcg/xtensa: support configurations w/o vecbase

Configurations w/o vecbase may have vectors not grouped together and not
in fixed order. They may not always be grouped into single output
sections by assigning next offset to dot, as it may sometimes move dot
backwards and sometimes they may even belong to different memory region.
Don't group vectors into single output section. Instead put each vector
into its own section ant put it at its default virtual address.
Reserve 4KBytes from the default vectors base and put rest of the code
and data starting from there. Mark vectors sections as executable,
otherwise their contents is discarded. There may be as little as 16
bytes reserved for some vectors, load handler address into a0 and use
ret.n to jump there to make vector code fit into this 16 byte space.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>

show more ...

Merge remote-tracking branch 'remotes/xtensa/tags/20180918-xtensa' into staging

target/xtensa updates:

- fix gdbstub register counts;
- add big-endian core test_kc705_be;
- convert to do_transactio

Merge remote-tracking branch 'remotes/xtensa/tags/20180918-xtensa' into staging

target/xtensa updates:

- fix gdbstub register counts;
- add big-endian core test_kc705_be;
- convert to do_transaction_failed and add test for failed memory
transactions;
- fix couple FPU2000 bugs;
- fix s32c1i implementation;
- clean up exception handlers generation in xtensa tests;
- add support for semihosting console input through a chardev.

# gpg: Signature made Tue 18 Sep 2018 18:35:50 BST
# gpg: using RSA key 51F9CC91F83FA044
# gpg: Good signature from "Max Filippov <filippov@cadence.com>"
# gpg: aka "Max Filippov <max.filippov@cogentembedded.com>"
# gpg: aka "Max Filippov <jcmvbkbc@gmail.com>"
# Primary key fingerprint: 2B67 854B 98E5 327D CDEB 17D8 51F9 CC91 F83F A044

* remotes/xtensa/tags/20180918-xtensa:
target/xtensa: support input from chardev console
target/xtensa: fix s32c1i TCGMemOp flags
tests/tcg/xtensa: only generate defined exception handlers
tests/tcg/xtensa: move exception handlers to separate section
target/xtensa: fix FPU2000 bugs
tests/tcg/xtensa: add test for failed memory transactions
target/xtensa: convert to do_transaction_failed
target/xtensa: add test_kc705_be core
target/xtensa: clean up gdbstub register handling
target/xtensa: fix gdbstub register counts

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

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tests/tcg/xtensa: move exception handlers to separate section

Not all CPU configurations may have enough space for handler code
between exception/interrupt vectors. Leave jumps to the handlers at th

tests/tcg/xtensa: move exception handlers to separate section

Not all CPU configurations may have enough space for handler code
between exception/interrupt vectors. Leave jumps to the handlers at the
vectors, but move all handlers past the vectors area.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>

show more ...

Merge remote-tracking branch 'remotes/armbru/tags/pull-include-2016-07-12' into staging

Clean up #include "..." vs <...> and header guards

# gpg: Signature made Tue 12 Jul 2016 15:23:43 BST
# gpg:

Merge remote-tracking branch 'remotes/armbru/tags/pull-include-2016-07-12' into staging

Clean up #include "..." vs <...> and header guards

# gpg: Signature made Tue 12 Jul 2016 15:23:43 BST
# gpg: using RSA key 0x3870B400EB918653
# gpg: Good signature from "Markus Armbruster <armbru@redhat.com>"
# gpg: aka "Markus Armbruster <armbru@pond.sub.org>"
# Primary key fingerprint: 354B C8B3 D7EB 2A6B 6867 4E5F 3870 B400 EB91 8653

* remotes/armbru/tags/pull-include-2016-07-12:
cris: Fix broken header guard in hw/cris/boot.h
Clean up decorations and whitespace around header guards
Clean up ill-advised or unusual header guards
libdecnumber: Don't error out on decNumberLocal.h re-inclusion
libdecnumber: Don't fool around with guards to avoid #include
Clean up header guards that don't match their file name
Drop Emacs local variables lists redundant with .dir-locals.el
spapr_pci: Include spapr.h instead of playing games with #error
tcg: Clean up tcg-target.h header guards
linux-user: Fix broken header guard in syscall_defs.h
linux-user: Clean up hostdep.h header guards
linux-user: Clean up target_structs.h header guards
linux-user: Clean up target_signal.h header guards
linux-user: Clean up target_cpu.h header guards
linux-user: Clean up target_syscall.h header guards
target-*: Clean up cpu.h header guards
scripts: New clean-header-guards.pl
Use #include "..." for our own headers, <...> for others

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

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Use #include "..." for our own headers, <...> for others

Tracked down with an ugly, brittle and probably buggy Perl script.

Also move includes converted to <...> up so they get included before
ours

Use #include "..." for our own headers, <...> for others

Tracked down with an ugly, brittle and probably buggy Perl script.

Also move includes converted to <...> up so they get included before
ours where that's obviously okay.

Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Tested-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>

show more ...

Merge remote-tracking branch 'remotes/xtensa/tags/20141103-xtensa' into staging

Xtensa fixes and improvements 2014-11-03:
- build fixes for cores w/o windowed registers and with profiling
interrup

Merge remote-tracking branch 'remotes/xtensa/tags/20141103-xtensa' into staging

Xtensa fixes and improvements 2014-11-03:
- build fixes for cores w/o windowed registers and with profiling
interrupts;
- fix uImage load address for MMUv2 cores;
- add script for automatic core import from xtensa configuration overlay.

# gpg: Signature made Sun 02 Nov 2014 22:04:44 GMT using RSA key ID F83FA044
# gpg: Good signature from "Max Filippov <max.filippov@cogentembedded.com>"
# gpg: aka "Max Filippov <jcmvbkbc@gmail.com>"

* remotes/xtensa/tags/20141103-xtensa:
MAINTAINERS: update xtensa boards
target-xtensa: fix build for cores w/o windowed registers
target-xtensa: add core importing script
hw/xtensa/xtfpga: treat uImage load address as virtual
hw/core/loader: implement address translation in uimage loader
target-xtensa: avoid duplicate timer interrupt delivery
target-xtensa: tests: pre-process tests linker script
target-xtensa: add definition for XTHAL_INTTYPE_PROFILING

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

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target-xtensa: tests: pre-process tests linker script

Xtensa cores have configurable interrupt vectors and endiannes. This
information is needed to link executable images correctly for a specific
co

target-xtensa: tests: pre-process tests linker script

Xtensa cores have configurable interrupt vectors and endiannes. This
information is needed to link executable images correctly for a specific
core configuration. Instead of hard-coding dc232 defaults pull endianness,
number of high-priority interrupts and location of vectors from the core
configuration and pass it through the C preprocessor.

While at it clean up tabs and align the initial stack on 16 bytes.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>

show more ...