History log of /qemu/tests/tcg/openrisc/test_addc.c (Results 1 – 3 of 3)
Revision Date Author Comments
# ffb62da7 21-Nov-2013 Anthony Liguori <aliguori@amazon.com>

Merge remote-tracking branch 'jliu/or32' into staging

# By Sebastian Macke
# Via Jia Liu
* jliu/or32:
target-openrisc: Correct carry flag check of l.addc and l.addic test cases
target-openrisc:

Merge remote-tracking branch 'jliu/or32' into staging

# By Sebastian Macke
# Via Jia Liu
* jliu/or32:
target-openrisc: Correct carry flag check of l.addc and l.addic test cases
target-openrisc: Correct memory bounds checking for the tlb buffers
openrisc-timer: Reduce overhead, Separate clock update functions
target-openrisc: Correct wrong epcr register in interrupt handler
target-openrisc: Remove executable flag for every page
target-openrisc: Remove unnecessary code generated by jump instructions
target-openrisc: Speed up move instruction

Message-id: 1384958318-9145-1-git-send-email-proljc@gmail.com
Signed-off-by: Anthony Liguori <aliguori@amazon.com>

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# 14a650ec 22-Oct-2013 Sebastian Macke <sebastian@macke.de>

target-openrisc: Correct carry flag check of l.addc and l.addic test cases

The test cases did not correctly test for the carry flag.

Signed-off-by: Sebastian Macke <sebastian@macke.de>
Reviewed-by:

target-openrisc: Correct carry flag check of l.addc and l.addic test cases

The test cases did not correctly test for the carry flag.

Signed-off-by: Sebastian Macke <sebastian@macke.de>
Reviewed-by: Jia Liu <proljc@gmail.com>
Signed-off-by: Jia Liu <proljc@gmail.com>

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# d901eff3 20-Jul-2012 Jia Liu <proljc@gmail.com>

target-or32: Add testcases

Add testcases for OpenRISC.

Signed-off-by: Jia Liu <proljc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>