#
3e82ddaa |
| 30-May-2025 |
Stefan Hajnoczi <stefanha@redhat.com> |
Merge tag 'pull-target-arm-20250530-2' of https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue: * hw/arm: Add GMAC devices to NPCM8XX SoC * hw/arm: Add missing psci_condui
Merge tag 'pull-target-arm-20250530-2' of https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue: * hw/arm: Add GMAC devices to NPCM8XX SoC * hw/arm: Add missing psci_conduit to NPCM8XX SoC boot info * docs/interop: convert text files to restructuredText * target/arm: Some minor refactorings * tests/functional: Add a test for the Stellaris arm machines * hw/block: Drop unused nand.c
# -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmg5qPYZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3tXUD/9tKWMUEYl23gd9IB5Ee3xK # dcgG4Fzv0Ae8HLTd1agyhrg5S2LiXmFi37IO65d8Wxf7Y2TBU+kj1m3aB/C3w9Bx # VdHGfNsHAMuYdYCOEm9OvmuSMYSxDRd43pNWdBxbc9/MgLM24rImJ05YHoZFVGrY # S5olcZOl3/ttFHtigO4AYAbxkHMAJ5gDyNJiuk88IPx9WGYdmmM4mzJ/m17/Re01 # hdOUi0DKQO7kl+646knSU0dicu8NeO5rBAyJzu3vFBnvYXznjd9XaxF+A0Opl54P # aBUZz27nDLvnGQrN8B5CjevjUysko+KL/L4NRqebeQKhSe4C8tKFIDocRTGyOEoR # SAI0UpZbcX/mXt52aksSwMNG8oRvHOqpJRnNaaCZQoMjK7SlFwi6WctDpwiGt/Hu # WaVlXaC77YRiKf1RAgH2CxV04ts342v+bndjfi4vy8D4zbTvwgqKxg+qk3N+JBMR # ZUI5Gz3OcGXbw5awJAYbJmyo6qxBysmdHpPY8I1eW0ohzRx1rZ3Vka4yIje5mgO+ # 5yFpSy4GDRqNYKgGwlXRaseB38qKL4bEz0+uGzXYqdG7ACBz0xhT5H10npXkX/au # LumtwW1sohsv3Xf9oBHQ1WQel7LDcWGVEZHZn6q67mazjvivLjREvA74dq1e8bqD # zovTStIpBYRChXTRK1ShUQ== # =Xts4 # -----END PGP SIGNATURE----- # gpg: Signature made Fri 30 May 2025 08:47:50 EDT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* tag 'pull-target-arm-20250530-2' of https://git.linaro.org/people/pmaydell/qemu-arm: hw/block: Drop unused nand.c tests/functional: Add a test for the Stellaris arm machines target/arm/hvf: Include missing 'cpu-qom.h' header target/arm/kvm: Include missing 'cpu-qom.h' header target/arm/qmp: Include missing 'cpu.h' header target/arm/cpu-features: Include missing 'cpu.h' header hw/arm/boot: Include missing 'system/memory.h' header target/arm/cpregs: Include missing 'target/arm/cpu.h' header target/arm: Only link with zlib when TCG is enabled target/arm/hvf_arm: Avoid using poisoned CONFIG_HVF definition target/arm/tcg-stubs: compile file once (system) docs/interop: convert text files to restructuredText hw/arm: Add missing psci_conduit to NPCM8XX SoC boot info tests/qtest: Migrate GMAC test from 7xx to 8xx hw/arm: Add GMAC devices to NPCM8XX SoC
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
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#
e7083b02 |
| 29-May-2025 |
Nabih Estefan <nabihestefan@google.com> |
tests/qtest: Migrate GMAC test from 7xx to 8xx
For upstreaming we migrated this test to 7xx (since that was already upstream) move it back to 8xx where it can check the 4 GMACs since that is the boa
tests/qtest: Migrate GMAC test from 7xx to 8xx
For upstreaming we migrated this test to 7xx (since that was already upstream) move it back to 8xx where it can check the 4 GMACs since that is the board this test was originally created for.
Signed-off-by: Nabih Estefan <nabihestefan@google.com> Message-id: 20250508220718.735415-3-nabihestefan@google.com Reviewed-by: Tyrone Ting <kfting@nuvoton.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
80db93b2 |
| 26-May-2025 |
Stefan Hajnoczi <stefanha@redhat.com> |
Merge tag 'pull-aspeed-20250526' of https://github.com/legoater/qemu into staging
aspeed queue:
* Fixed memory leaks in qtest tests * Reworked and fixed HACE (crypto) model for AST2700 SoC * Extend
Merge tag 'pull-aspeed-20250526' of https://github.com/legoater/qemu into staging
aspeed queue:
* Fixed memory leaks in qtest tests * Reworked and fixed HACE (crypto) model for AST2700 SoC * Extended HACE qtest tests * Fixed RAM size detection on BE hosts * Added network backends to ast2700fc machine * Mapped main SoC memory into system memory on multi SoC machines
# -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEEoPZlSPBIlev+awtgUaNDx8/77KEFAmg0IJYACgkQUaNDx8/7 # 7KFWkBAAqzVVJVH+XxVsKimljyI5hpkl1h7EiH2XS4hYyXQyGarwLjfYQs8tDSL0 # tD3+nfDAgbob4vIMSHy8KNs05paB6jYFisHIgalszQh5YqPyxQGhvXNfOCoIApVh # pcAmdaSmW+hfDMklOk1zDgLzxHuQX74EWBMRkCQycFrJzGE5Z4EFvQ6uavOGdrxP # 2m5ytGyuXEwtE4MYnX/5mK6CkCOFh6TC7/z8QOXJoBvXjXmjO3Iu1l216jZdnxtB # GBmavqpoDgm+884nWpf28jNKGos60QMMC2JAdBtdcW4RUxIGzZ8VYTpgS3bfuR+y # vvElGa3c67Ie6mu1VUlyNJ58rSqkMb5FaEz+U+V3apdJXtiHhqTwvnAyVMVnD3S8 # ajnMVw+BGJVgQWT5/w3TV3B+09IkfxJ+sh0BEVsRtvH0gKbE040o6tBoNHNANnHO # j33aMzVpAdqQFeRmxb1ysfSwzQV+q3Dw/rz9CNn8myAxqpixUq4AqWDasnWhSRVY # Mqou6qlTCwjFmyeuq7YCC2Y0wOm2lgIkfggG+vkIoBPEU0g/yLcnYeb5pIV0w33m # YqBB6UcxjGEN+hC4fkbkvXrIADNdkcs639al2xsRUYPz8+uTgUxO8poZvE4G+eNR # Jj2CrJn7a6ThjD4mG8ezEuknQ5pZ9SnX8DAL11XvDUGHRG0+CtI= # =00WM # -----END PGP SIGNATURE----- # gpg: Signature made Mon 26 May 2025 04:04:38 EDT # gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1 # gpg: Good signature from "Cédric Le Goater <clg@redhat.com>" [full] # gpg: aka "Cédric Le Goater <clg@kaod.org>" [full] # Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1
* tag 'pull-aspeed-20250526' of https://github.com/legoater/qemu: (39 commits) docs: Remove ast2700fc from Aspeed family boards hw/arm/fby35: Map BMC memory into system memory hw/arm/aspeed_ast27x0-fc: Map ca35 memory into system memory hw/arm/aspeed_ast27x0: Fix unimplemented region overlap with vbootrom hw/arm/aspeed_ast2700-fc: Reduce ca35 ram size to align with ast2700a1 hw/arm/aspeed_ast2700-fc: Add network support hw/arm/aspeed_ast27x0: Fix RAM size detection failure on BE hosts hw/intc/aspeed Fix coding style hw/intc/aspeed: Set impl.min_access_size to 4 test/qtest/hace: Add tests for AST2700 test/qtest/hace: Support to validate 64-bit hmac key buffer addresses test/qtest/hace: Support to test upper 32 bits of digest and source addresses test/qtest/hace: Support 64-bit source and digest addresses for AST2700 test/qtest/hace: Update source data and digest data type to 64-bit test/qtest/hace: Add tests for AST1030 test/qtest/hace: Add SHA-384 tests for AST2600 test/qtest/hace: Add SHA-384 test cases for ASPEED HACE model test/qtest/hace: Adjust test address range for AST1030 due to SRAM limitations test/qtest/hace: Specify explicit array sizes for test vectors and hash results test/qtest: Introduce a new aspeed-hace-utils.c to place common testcases ...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
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#
5071c229 |
| 15-May-2025 |
Jamin Lin <jamin_lin@aspeedtech.com> |
test/qtest/hace: Add tests for AST2700
The HACE models in AST2600 and AST2700 are nearly identical. Based on the AST2600 test cases, new tests have been added for AST2700.
Implemented test function
test/qtest/hace: Add tests for AST2700
The HACE models in AST2600 and AST2700 are nearly identical. Based on the AST2600 test cases, new tests have been added for AST2700.
Implemented test functions for SHA-256, SHA-384, SHA-512, and MD5. Added scatter-gather and accumulation test variants. For AST2700, the HACE controller base address starts at "0x12070000", and the DRAM start address is "0x4_00000000".
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Acked-by: Fabiano Rosas <farosas@suse.de> Link: https://lore.kernel.org/qemu-devel/20250515081008.583578-29-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
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#
70985b0e |
| 15-May-2025 |
Jamin Lin <jamin_lin@aspeedtech.com> |
test/qtest: Introduce a new aspeed-hace-utils.c to place common testcases
The test cases for the ASPEED HACE model were originally placed in aspeed_hace-test.c. However, this test file only supports
test/qtest: Introduce a new aspeed-hace-utils.c to place common testcases
The test cases for the ASPEED HACE model were originally placed in aspeed_hace-test.c. However, this test file only supports ARM32. To enable compatibility with all ASPEED SoCs, including the AST2700, which uses the AArch64 architecture, this update introduces a new source file, aspeed-hace-utils.c.
All common APIs and test cases have been moved from aspeed_hace-test.c to aspeed-hace-utils.c to facilitate reuse across different ASPEED SoCs. As a result, these test cases can now be reused for AST2700 and future ASPEED SoC testing.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Acked-by: Fabiano Rosas <farosas@suse.de> Link: https://lore.kernel.org/qemu-devel/20250515081008.583578-19-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
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#
408326af |
| 15-May-2025 |
Jamin Lin <jamin_lin@aspeedtech.com> |
tests/qtest: Reorder aspeed test list
Reordered the aspeed test list to keep the alphabetical order. No functional changes in test behavior.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Revi
tests/qtest: Reorder aspeed test list
Reordered the aspeed test list to keep the alphabetical order. No functional changes in test behavior.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Acked-by: Fabiano Rosas <farosas@suse.de> Link: https://lore.kernel.org/qemu-devel/20250515081008.583578-18-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
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#
69ee0189 |
| 12-May-2025 |
Stefan Hajnoczi <stefanha@redhat.com> |
Merge tag 'qtest-20250509-pull-request' of https://gitlab.com/farosas/qemu into staging
Qtest pull request
- Fix migration-test invocation of qtest_init - Simplify byte-swapping for virtio in libqo
Merge tag 'qtest-20250509-pull-request' of https://gitlab.com/farosas/qemu into staging
Qtest pull request
- Fix migration-test invocation of qtest_init - Simplify byte-swapping for virtio in libqos - New cpu hotplug test for loongarch64
# -----BEGIN PGP SIGNATURE----- # # iQJEBAABCAAuFiEEqhtIsKIjJqWkw2TPx5jcdBvsMZ0FAmgecLgQHGZhcm9zYXNA # c3VzZS5kZQAKCRDHmNx0G+wxnaiLD/9pW1eU9we/KDm3wJg9zRS37h5OmSF+ogIN # ziXG1XmyXKK+QAybInZ1d3oaGqZoR+hhJ6RWmf6+E57ZyJ2EPtasJhekOulAZYZI # yWXtbWzKnaCc+AhohM+xJGC1XObAvvfz+8wjMFHnuJn0BBiBBWXkiHljG02KdkT6 # Ca+83+NSn/6OJYENTgaXiXkviNELbzDBTFgtWKkW0+bniCsbfrnuGqWbf43/cDbr # vnfiIt4o6jgjvEaBMid3cAtFUzI9gRtB7tk/sGvdPWGPkyjxTt5rnVxe6CBqh1SA # j5CbrcgPt7HxgdBEZC38o2tj5YxAjUZ5TXziouoxom0vzHSTep/NJih+XIhtXM8f # ABL9YZCBGvb3ja8NvXZwsLkcbSDbfTG8CNtHCTx3S3qagENxd6mUj4GMaOQxNQ1y # DUPGQetOzBIsYQOjt9fITN2S7oprXjpHwgV6TD/VOkJ+YVML1mRNsDi2sUkzH8jF # IUmjHWqJvyTvPY8dfVyYWLLhPUgJJdEfjgyT2qG6nbEcgd5seuB/3Rm/+VbqST+e # JUjbBOJStPdCQLtvlcDv+r/u2VwRta6f8ZU+DTlUnBboRSoHBrD3vzAa4uDLTufC # K01SC/xxzIMXR0Ji9qB9uKA6FJmbDdJhzBOzCFm7q7UCrRCNcgfhWO/OXuOqTg7j # bPDmCKA+dw== # =MZlp # -----END PGP SIGNATURE----- # gpg: Signature made Fri 09 May 2025 17:16:40 EDT # gpg: using RSA key AA1B48B0A22326A5A4C364CFC798DC741BEC319D # gpg: issuer "farosas@suse.de" # gpg: Good signature from "Fabiano Rosas <farosas@suse.de>" [unknown] # gpg: aka "Fabiano Almeida Rosas <fabiano.rosas@suse.com>" [unknown] # gpg: WARNING: The key's User ID is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: AA1B 48B0 A223 26A5 A4C3 64CF C798 DC74 1BEC 319D
* tag 'qtest-20250509-pull-request' of https://gitlab.com/farosas/qemu: tests/qtest/cpu-plug-test: Add cpu hotplug support for LoongArch tests/qtest/libqos: Avoid double swapping when using modern virtio qtest: introduce qtest_init_ext
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
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#
98008aa4 |
| 14-Mar-2025 |
Bibo Mao <maobibo@loongson.cn> |
tests/qtest/cpu-plug-test: Add cpu hotplug support for LoongArch
Add cpu hotplug testcase support for LoongArch system, it passes to run with command "make check-qtest-loongarch64" as following: q
tests/qtest/cpu-plug-test: Add cpu hotplug support for LoongArch
Add cpu hotplug testcase support for LoongArch system, it passes to run with command "make check-qtest-loongarch64" as following: qemu:qtest+qtest-loongarch64 / qtest-loongarch64/cpu-plug-test OK 0.38s 1 subtests passed
Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-ID: <20250314085130.4184272-1-maobibo@loongson.cn> Signed-off-by: Fabiano Rosas <farosas@suse.de>
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#
71119ed3 |
| 23-Mar-2025 |
Stefan Hajnoczi <stefanha@redhat.com> |
Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
* exec/cpu-all: remove BSWAP_NEEDED * pl011: pad C PL011State struct to same size as Rust struct * rust: hpet: fix type of "t
Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
* exec/cpu-all: remove BSWAP_NEEDED * pl011: pad C PL011State struct to same size as Rust struct * rust: hpet: fix type of "timers" property * rust: hpet: fix functional tests (and really everything that uses it) * rust: Kconfig: Factor out whether devices are Rust or C * rust: vmstate: Fixes and tests
# -----BEGIN PGP SIGNATURE----- # # iQFIBAABCgAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAmfdsUsUHHBib256aW5p # QHJlZGhhdC5jb20ACgkQv/vSX3jHroOGpwf/Qk4bAcLX7A1/nOmYT+DtWzZ9V/VS # hSOe6BruzW8rzwMyn/d7oR+aUpk3sL+v2iPBWqoZ/wh0w8kcABcUfWsqqGI8ln/K # pnTdiC+hra5z0AFH1tmjjtOI50WDOeSjh5SFvoPJtGzhEbo89QvsUWgy98HiHOMm # YFPDuhg3Pfd1XDcdoaa85sOHO1vDsj45fCEJhx6Ktib4vOlEm2I4Z9YR/JxNMT33 # vy/y09HG4cpc6bWKLPL3nqR9RchUSI+YRDZ8rlaXUowiZzH2K/wi0qJOsvG6oJF5 # awni0YWuwyFi16jmUub8NFnWk6NKjbACqw74AwoVPbNbDoCrrogXzIF2Lw== # =NzCN # -----END PGP SIGNATURE----- # gpg: Signature made Fri 21 Mar 2025 14:34:51 EDT # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83
* tag 'for-upstream' of https://gitlab.com/bonzini/qemu: (24 commits) rust: hpet: fix decoding of timer registers rust/vmstate: Include complete crate path of VMStateFlags in vmstate_clock rust/vmstate: Add unit test for vmstate_validate rust/vmstate: Add unit test for pointer case rust/vmstate: Add unit test for vmstate_{of|struct} macro rust/vmstate: Add unit test for vmstate_of macro rust/vmstate: Support vmstate_validate rust/vmstate: Re-implement VMState trait for timer binding rust/vmstate: Relax array check when build varray in vmstate_struct rust/vmstate: Fix unnecessary VMState bound of with_varray_flag() rust/vmstate: Fix "cannot infer type" error in vmstate_struct rust/vmstate: Fix type check for varray in vmstate_struct rust/vmstate: Fix size field of VMStateField with VMS_ARRAY_OF_POINTER flag rust/vmstate: Fix num field when varray flags are set rust/vmstate: Fix num_offset in vmstate macros rust/vmstate: Remove unnecessary unsafe exec/cpu-all: remove BSWAP_NEEDED load_aout: replace bswap_needed with big_endian rust: pl011: Check size of state struct at compile time hw/char/pl011: Pad PL011State struct to same size as Rust impl ...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
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d1368344 |
| 19-Mar-2025 |
Peter Maydell <peter.maydell@linaro.org> |
rust: Kconfig: Factor out whether HPET is Rust or C
Currently we require everywhere that wants to know if there is an HPET device to check for "CONFIG_HPET || CONFIG_X_HPET_RUST". Factor out whether
rust: Kconfig: Factor out whether HPET is Rust or C
Currently we require everywhere that wants to know if there is an HPET device to check for "CONFIG_HPET || CONFIG_X_HPET_RUST". Factor out whether the HPET device is Rust or C into a separate Kconfig stanza, so that CONFIG_HPET means "there is an HPET", and whether this has pulled in CONFIG_X_HPET_RUST or CONFIG_HPET_C is something the rest of QEMU can ignore.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Link: https://lore.kernel.org/r/20250319193110.1565578-3-peter.maydell@linaro.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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4c33c097 |
| 13-Mar-2025 |
Stefan Hajnoczi <stefanha@redhat.com> |
Merge tag 'hw-misc-20250312' of https://github.com/philmd/qemu into staging
Misc HW patches
- Set correct values for MPC8569E's eSDHC (Zoltan) - Emulate Ricoh RS5C372 RTC device (Bernhard) - Array
Merge tag 'hw-misc-20250312' of https://github.com/philmd/qemu into staging
Misc HW patches
- Set correct values for MPC8569E's eSDHC (Zoltan) - Emulate Ricoh RS5C372 RTC device (Bernhard) - Array overflow fixes in SMSC91C111 netdev (Peter) - Fix typo in Xen HVM (Philippe) - Move graphic height/width/depth globals to their own file (Philippe) - Introduce qemu_arch_available() helper (Philippe) - Check fw_cfg's ACPI availability at runtime (Philippe) - Remove virtio-mem dependency on CONFIG_DEVICES (Philippe) - Sort HyperV SYNDBG API definitions (Pierrick) - Remove need for SDHCI_VENDOR_FSL definition (Philippe)
# -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmfRXiMACgkQ4+MsLN6t # wN5zFhAAzSW/hZneD8hycKtr9nBlvZSD72cEt+b656OCbTyyucUi1sG4rMPMvHeW # h6HP6xt2SfQxXbec6Y0pWxWUkBOQzk72s0zpttOED3oEspkrId2D+VSsSH1E+QLh # WoG7/hVgz0bDHexWYIDdGufO4no/icwewAKmC5Kp2HbaNxIIHyWlK1+RO69/lCLN # s3qkNesMsQyEWN28ogEMRqyCIG3oJVP76U4TVcdxIiE51WI8sP8/7V2um0AXN68m # IV3INrfVJjGDp501elrUbD3qsYopRdxoMAvwiVojrLXin6xtS+SQjEe/hcNxzM70 # 0IQPp9WWwLjNkeFlAJF4wpwGJttFNHj+5gtH7/YRrP75jt9kAxPXkFw/OFfpVd30 # NYbeFlWDhRL1QPBs+WPBZTrfD7fRmpfMJRLF3/w61+WvnVrshlyDaoCWbR+L329F # uOQFsBdAD7m/lkZ0mHtskS2vkZx7Itn1av4gql7T7/6cE1R7ItKy1HY9UUCtY6Gp # 7V6XrsAE3khg2HY8IcJ73+sPLQn/GxqZFE7PqmAhgcl6RZEFQv8PNrEgFxCEYyuK # KJjx0hRMLoigp0CEclLfOqz2d3knsI8SJbgD4iTYQc02E69lx8a4XS4N8JXoLEdh # 3i/ndwKEFmzwNuqbU0nYsSJDiAO9ejra8O2BXZS/a4pkxC2jtdw= # =VVr6 # -----END PGP SIGNATURE----- # gpg: Signature made Wed 12 Mar 2025 18:12:51 HKT # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE
* tag 'hw-misc-20250312' of https://github.com/philmd/qemu: hw/sd/sdhci: Remove need for SDHCI_VENDOR_IMX definition hw/hyperv/hyperv-proto: Move SYNDBG definitions from target/i386 hw/virtio/virtio-mem: Remove CONFIG_DEVICES include hw/i386/fw_cfg: Check ACPI availability with acpi_builtin() hw/acpi: Introduce acpi_builtin() helper system: Replace arch_type global by qemu_arch_available() helper system: Extract target-specific globals to their own compilation unit hw/xen/hvm: Fix Aarch64 typo hw/net/smc91c111: Don't allow data register access to overrun buffer hw/net/smc91c111: Use MAX_PACKET_SIZE instead of magic numbers hw/net/smc91c111: Sanitize packet length on tx hw/net/smc91c111: Sanitize packet numbers hw/rtc: Add Ricoh RS5C372 RTC emulation hw/sd/sdhci: Set reset value of interrupt registers
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
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#
71569cd8 |
| 11-Mar-2025 |
Stefan Hajnoczi <stefanha@redhat.com> |
Merge tag 'pull-ppc-for-10.0-1-20250311' of https://gitlab.com/npiggin/qemu into staging
* Next round of XIVE patches...
* tag 'pull-ppc-for-10.0-1-20250311' of https://gitlab.com/npiggin/qemu: (72
Merge tag 'pull-ppc-for-10.0-1-20250311' of https://gitlab.com/npiggin/qemu into staging
* Next round of XIVE patches...
* tag 'pull-ppc-for-10.0-1-20250311' of https://gitlab.com/npiggin/qemu: (72 commits) docs/system/ppc/amigang.rst: Update for NVRAM emulation ppc/amigaone: Add #defines for memory map constants ppc/amigaone: Add kernel and initrd support ppc/amigaone: Add default environment ppc/amigaone: Implement NVRAM emulation ppc/amigaone: Simplify replacement dummy_fw spapr: Generate random HASHPKEYR for spapr machines target/ppc: Avoid warning message for zero process table entries target/ppc: Wire up BookE ATB registers for e500 family target/ppc: fix timebase register reset state spapr: nested: Add support for reporting Hostwide state counter ppc: spapr: Enable 2nd DAWR on Power10 pSeries machine ppc: Enable 2nd DAWR support on Power10 PowerNV machine hw/ppc/epapr: Do not swap ePAPR magic value hw/ppc/spapr: Convert DIRTY_HPTE() macro as hpte_set_dirty() method hw/ppc/spapr: Convert CLEAN_HPTE() macro as hpte_set_clean() method hw/ppc/spapr: Convert HPTE_DIRTY() macro as hpte_is_dirty() method hw/ppc/spapr: Convert HPTE_VALID() macro as hpte_is_valid() method hw/ppc/spapr: Convert HPTE() macro as hpte_get_ptr() method target/ppc: Restrict ATTN / SCV / PMINSN helpers to TCG ...
[Fix __packed macro redefinition on FreeBSD 14 hosts: ../hw/ppc/pnv_occ.c:397:9: error: '__packed' macro redefined [-Werror,-Wmacro-redefined] 397 | #define __packed QEMU_PACKED | ^ /usr/include/sys/cdefs.h:217:9: note: previous definition is here 217 | #define __packed __attribute__((__packed__)) | ^ --Stefan]
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
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#
822405b1 |
| 23-Feb-2025 |
Bernhard Beschow <shentey@gmail.com> |
hw/rtc: Add Ricoh RS5C372 RTC emulation
The implementation just allows Linux to determine date and time.
Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <phi
hw/rtc: Add Ricoh RS5C372 RTC emulation
The implementation just allows Linux to determine date and time.
Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Acked-by: Fabiano Rosas <farosas@suse.de> Message-ID: <20250223114708.1780-19-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
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#
96a2132c |
| 11-Mar-2025 |
Frederic Barrat <fbarrat@linux.ibm.com> |
ppc/xive2: Add support for MMIO operations on the NVPG/NVC BAR
Add support for the NVPG and NVC BARs. Access to the BAR pages will cause backlog counter operations to either increment or decriment
ppc/xive2: Add support for MMIO operations on the NVPG/NVC BAR
Add support for the NVPG and NVC BARs. Access to the BAR pages will cause backlog counter operations to either increment or decriment the counter.
Also added qtests for the same.
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Michael Kowal <kowal@linux.ibm.com> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
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#
e5029e28 |
| 04-Feb-2025 |
Cédric Le Goater <clg@redhat.com> |
ppc/ppc405: Remove tests
Since we are about to remove all support for PPC 405, start by removing the tests referring to the ref405ep machine.
Link: https://lore.kernel.org/qemu-devel/20250110141800
ppc/ppc405: Remove tests
Since we are about to remove all support for PPC 405, start by removing the tests referring to the ref405ep machine.
Link: https://lore.kernel.org/qemu-devel/20250110141800.1587589-2-clg@redhat.com Signed-off-by: Cédric Le Goater <clg@redhat.com> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Message-ID: <20250204080649.836155-2-clg@redhat.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
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#
b4b0880c |
| 14-Feb-2025 |
Stefan Hajnoczi <stefanha@redhat.com> |
Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
* rust: more qdev bindings * rust: HPET device model with timer and GPIO bindings * rust: small cleanups and fixes; run docte
Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
* rust: more qdev bindings * rust: HPET device model with timer and GPIO bindings * rust: small cleanups and fixes; run doctests during CI * ui/sdl2: reenable the SDL2 Windows keyboard hook procedure
# -----BEGIN PGP SIGNATURE----- # # iQFIBAABCAAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAmet6qkUHHBib256aW5p # QHJlZGhhdC5jb20ACgkQv/vSX3jHroO4yQgAjSpJ8DChoEVrm6xgCUGPkC7VlI0A # 3WimcgiTUCUVqiywvLmObHRv9ld/b9mJ+2v/actDy39qioN3i3+RGpyeSRcysITd # 2AWQVOe6JuVfEyN+ihYq3yS3v1meDhzZbOzRNHgbTX20rMy/HWJFIvQbK4abQaVI # j8zaPYIjcfcH/ScEmmha88l6PJDMPy7fCEzQWx41oHKkQ8w4rhmarn9f3WcXB/SN # bCvm2NmkJFPsU/TCynWz7YSjrLWCsWjiDgxoDD1295QoeEvfcuD8Z6vPIA9BttGx # MUgcrXi4KnJI8W9gm5jAiKq+DSxFX6f7AwUDfb2l+Vrkq84s7bu9UVNQqA== # =/vpW # -----END PGP SIGNATURE----- # gpg: Signature made Thu 13 Feb 2025 07:50:49 EST # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83
* tag 'for-upstream' of https://gitlab.com/bonzini/qemu: (27 commits) ui/sdl2: reenable the SDL2 Windows keyboard hook procedure rust: fix doctests rust: vmstate: remove redundant link targets rust: qemu_api: add a documentation header for all modules i386: enable rust hpet for pc when rust is enabled rust/timer/hpet: add qom and qdev APIs support rust/timer/hpet: add basic HPET timer and HPETState rust/timer/hpet: define hpet_fw_cfg rust: add bindings for timer rust: add bindings for memattrs rust: add bindings for gpio_{in|out} initialization rust/irq: Add a helper to convert [InterruptSource] to pointer rust/qdev: add the macro to define bit property i386/fw_cfg: move hpet_cfg definition to hpet.c rust: pl011: convert pl011_create to safe Rust rust: chardev, qdev: add bindings to qdev_prop_set_chr rust: irq: define ObjectType for IRQState rust: bindings for MemoryRegionOps rust: bindings: add Send and Sync markers for types that have bindings rust: qdev: switch from legacy reset to Resettable ...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
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d128c341 |
| 10-Feb-2025 |
Zhao Liu <zhao1.liu@intel.com> |
i386: enable rust hpet for pc when rust is enabled
Add HPET configuration in PC's Kconfig options, and select HPET device (Rust version) if Rust is supported.
Signed-off-by: Zhao Liu <zhao1.liu@int
i386: enable rust hpet for pc when rust is enabled
Add HPET configuration in PC's Kconfig options, and select HPET device (Rust version) if Rust is supported.
Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Link: https://lore.kernel.org/r/20250210030051.2562726-11-zhao1.liu@intel.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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#
ffaf7f03 |
| 10-Feb-2025 |
Stefan Hajnoczi <stefanha@redhat.com> |
Merge tag 'pull-10.0-testing-and-gdstub-updates-100225-1' of https://gitlab.com/stsquad/qemu into staging
testing and gdbstub updates:
- add a check-rust test to docker builds - re-factor the q
Merge tag 'pull-10.0-testing-and-gdstub-updates-100225-1' of https://gitlab.com/stsquad/qemu into staging
testing and gdbstub updates:
- add a check-rust test to docker builds - re-factor the qtest logic to be cleaner - fix tests to not clock_step when no timers enabled - roll-up log prefix into qtest_send - cleaner error reporting when qtest_clock_set fails - revert old deadlock fix now tests are updated - only run full set of migration tests under HW acceleration - support late attachment to user-mode gdbstubs
# -----BEGIN PGP SIGNATURE----- # # iQEzBAABCgAdFiEEZoWumedRZ7yvyN81+9DbCVqeKkQFAmeqBSsACgkQ+9DbCVqe # KkQS/Af+K0hpdGc1msiuMsqmuESBvhoQniYZFLN1/pwe2KpG8i/+fq2fsCuxJhJ1 # 2TzPH7aj54p9MGCZf2k9JLhO22XldN+oezZMc1crhoWK0AtrWhnLs58I2oEPIsUo # NmGO6Zfm98ge89o2y8GCvd0QXAtUf+jduDKnW0mfnOnw+w/mky5KzWS7/1091VGW # 42LSY4KnqgdLSqLyuLBOrgADEjB1ChWS4/bSC+kEYSGrmNQB+n1KeIzzlJBGpOr0 # Z9yzmhMCm7TWdkFNPmnVfYH/7ZUNcpv6PtQSpkku4f6b/gybyvJBknHpM4i+Gpb5 # 87wSjljrCpdNm/9KFRjiJuUWdS/jCg== # =UF0n # -----END PGP SIGNATURE----- # gpg: Signature made Mon 10 Feb 2025 08:54:51 EST # gpg: using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44 # gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 6685 AE99 E751 67BC AFC8 DF35 FBD0 DB09 5A9E 2A44
* tag 'pull-10.0-testing-and-gdstub-updates-100225-1' of https://gitlab.com/stsquad/qemu: tests/tcg: Add late gdbstub attach test docs/user: Document the %d placeholder and suspend=n QEMU_GDB features gdbstub: Allow late attachment osdep: Introduce qemu_kill_thread() user: Introduce host_interrupt_signal user: Introduce user/signal.h gdbstub: Try unlinking the unix socket before binding gdbstub: Allow the %d placeholder in the socket path tests/qtest/migration: Pick smoke tests tests/qtest/migration: Add --full option Revert "util/timer: avoid deadlock when shutting down" tests/qtest: tighten up the checks on clock_step tests/qtest: rename qtest_send_prefix and roll-up into qtest_send tests/qtest: simplify qtest_process_inbuf tests/qtest: don't step clock at start of npcm7xx periodic IRQ test tests/qtest: don't attempt to clock_step while waiting for virtio ISR tests/docker: replicate the check-rust-tools-nightly CI job
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
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#
bc2a1f1a |
| 07-Feb-2025 |
Fabiano Rosas <farosas@suse.de> |
tests/qtest/migration: Add --full option
Add a new command line option to allow selecting between running the full set of tests or a smaller set of tests. The default will be to run the small set (i
tests/qtest/migration: Add --full option
Add a new command line option to allow selecting between running the full set of tests or a smaller set of tests. The default will be to run the small set (i.e. no comand line option provided) so we can reduce the amount of tests run by default. Only hosts which support KVM for the target architecture being tested will run the complete set of tests.
Adjust the meson.build file to pass in the --full option when appropriate.
(for now, set the option unconditionally until the next patch actually creates the small set)
Use cases:
configure --target-list=aarch64-softmmu,ppc64-softmmu,s390x-softmmu,x86_64-softmmu
| before - 615s/244 tests | after - 244s/100 tests ------------------------+--------------------------+----------------------------- make check | full set for all archs | full set for the KVM arch, make check-qtest | | small set for the rest | | qemu-system-$ARCH | full set for $ARCH | small set for $ARCH, KVM or ./migration-test | | TCG automatically chosen | | qemu-system-$ARCH | N/A | full set for $ARCH, KVM or ./migration-test --full | | TCG automatically chosen | | migration-compat-x86_64 | full set for x86_64 | small set for x86_64 CI job | | ------------------------+--------------------------+-----------------------------
Signed-off-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Peter Xu <peterx@redhat.com> Message-Id: <20250130184012.5711-2-farosas@suse.de> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20250207153112.3939799-9-alex.bennee@linaro.org>
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#
f58eb46a |
| 03-Feb-2025 |
Stefan Hajnoczi <stefanha@redhat.com> |
Merge tag 'qtest-20250203-pull-request' of https://gitlab.com/farosas/qemu into staging
Qtest pull request
- fw-cfg: DMA support and new vmcoreinfo test - accel detection via QOM for non-KVM accels
Merge tag 'qtest-20250203-pull-request' of https://gitlab.com/farosas/qemu into staging
Qtest pull request
- fw-cfg: DMA support and new vmcoreinfo test - accel detection via QOM for non-KVM accels - use virtio modern for vhost-user
# -----BEGIN PGP SIGNATURE----- # # iQJEBAABCAAuFiEEqhtIsKIjJqWkw2TPx5jcdBvsMZ0FAmeg8+cQHGZhcm9zYXNA # c3VzZS5kZQAKCRDHmNx0G+wxnS1jD/9/xx8i9fQgA9znEZmzMvQ0xXrlUz8jQkA8 # yd/iCZT1ue4ff39XA/Z01J/lUaHFV5x4xV4/YL+I0IcMddwIuI3xXexAEyO76rRC # dRxjKrq20s2W6VPnOT0NHBnvpNnYoQDunIZxY+16QMWajTRbA45G8R7W4dWWOhLQ # 2sWNuQHsj1lQ4lZMYlaMuFZC31PgFgPiEwIfS2NHST3WfxJVPpsLU5/Pc8UGs6fd # Sq58jXPS1Akhov7IuC8VG/icjnDpMe3f7OFWQ8u8MC5OhwFNnD7aNnf6V7LmM4f+ # vhwLPewKxS3KQ2j1Vt2iWGebxlJHDbvifaBpIiVIibaHvtzcOdwK/bK0i+ji3oTk # NgDB80+UKEUGzj0A+BNMcI+ZMonRT2wmBucWdGCosEG1FUlDONdX2a8Zs5Cfxipe # N2a30OmIfbHo905JLYbTw5SXFSyWdYTSgXOEyNlXjq/B+v3qtpdrHXtMOJaXfk/V # Ln0pKT/mDKx/haiooJdMheJpvRDYxFUHub1MrqnVWWeoiTS2wRwu9QAbFusNwyrk # cEYQRPwuX0AnGk6swRUVLdd7HHeeNDZtVBr30Gi1hzQUZRsfW/YmKunoXJ38XAoG # ZD/7VdTgmpQcoXNBJFnyi9Ie6NSWZwgNmZmZn3yWQtV5ACWIt0cqwF8POh8TOY25 # 5mVQly/UAA== # =FJP7 # -----END PGP SIGNATURE----- # gpg: Signature made Mon 03 Feb 2025 11:50:47 EST # gpg: using RSA key AA1B48B0A22326A5A4C364CFC798DC741BEC319D # gpg: issuer "farosas@suse.de" # gpg: Good signature from "Fabiano Rosas <farosas@suse.de>" [unknown] # gpg: aka "Fabiano Almeida Rosas <fabiano.rosas@suse.com>" [unknown] # gpg: WARNING: The key's User ID is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: AA1B 48B0 A223 26A5 A4C3 64CF C798 DC74 1BEC 319D
* tag 'qtest-20250203-pull-request' of https://gitlab.com/farosas/qemu: tests/qtest/vhost-user-test: Use modern virtio for vhost-user tests tests/qtest: Make qtest_has_accel() generic tests/qtest: Extract qtest_qom_has_concrete_type() helper tests/qtest/vmcoreinfo: add a unit test to exercize basic vmcoreinfo function tests/qtest/libqos: add DMA support for writing and reading fw_cfg files libqos/fw_cfg: refactor file directory iteraton to make it more reusable
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
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#
5fddf0c0 |
| 20-Jan-2025 |
Ani Sinha <anisinha@redhat.com> |
tests/qtest/vmcoreinfo: add a unit test to exercize basic vmcoreinfo function
A new qtest is written that exercizes the fw-cfg DMA based read and write ops to write values into vmcoreinfo fw-cfg fil
tests/qtest/vmcoreinfo: add a unit test to exercize basic vmcoreinfo function
A new qtest is written that exercizes the fw-cfg DMA based read and write ops to write values into vmcoreinfo fw-cfg file and read them back and verify that they are the same.
Signed-off-by: Ani Sinha <anisinha@redhat.com> Message-ID: <20250120043847.954881-4-anisinha@redhat.com> Signed-off-by: Fabiano Rosas <farosas@suse.de>
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#
f65f3261 |
| 02-Feb-2025 |
Stefan Hajnoczi <stefanha@redhat.com> |
Merge tag 'hw-misc-20250131' of https://github.com/philmd/qemu into staging
Misc HW patches
- Remove uses of &first_cpu in rx-gdbsim and loongson3_virt machines (Philippe) - Convert few legacy qemu
Merge tag 'hw-misc-20250131' of https://github.com/philmd/qemu into staging
Misc HW patches
- Remove uses of &first_cpu in rx-gdbsim and loongson3_virt machines (Philippe) - Convert few legacy qemu_allocate_irqs to qemu_init_irqs (Philippe) - Add tracing events in i2c-echo device (Titus) - Fix debug format string in USB EHCI (Zoltan) - Rework loader API to remove its target_words_bigendian() call (Philippe) - QOMify OMAP MMC device (Peter) - Remove legacy SD Card APIs (Peter)
# -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmedOmkACgkQ4+MsLN6t # wN4qHhAAtL3vmk6hQgKD76bSaB3CDEdHsnS7qqeRVVmbr7pQL9D6yyXzkjJBzZtk # nG7ubhoS5WFeKswzD8tY/mgP25hntnq38TNrRxDrpRNdFYF+a2cncpRGfgzk0z/9 # nme/BuUx6fNowV8MVGLNOLvaDCeDHl9biTLJmcQyqwlHy9l9Wi6DSa6Xi9ZQWlHi # fxYVeuQ7HYlKwhiu3mqpfNeauIgMSWz8V48ETCrFnjMWmiF1k1L0GccWDS8zpPDk # QkdOxHC4eVMxk0d2458eUXeqo/izfzoc7Z9hW6W8cyI69y4m011xqANd/udTS03E # HMcG9Ks0E+Yw8NGoErOP7zu8yFVEzCn2BKhH/wrUHBC2UfP99vNR/b8LNkg25y19 # IItOkMban0Oyr9KaNb1Ga+3pZIsyyil+shSYNHpWkfqk+TUpZkMUSaVHA9r1oB3V # u/dOO/lPLaWMvftKVXRl3K/Lfz4WF5cWjza5RratnzbBqqwr03CwjjBEuZIX/5ww # ATj/fV10OSHScxCqauYp8uuNSgEOKaJCJe2uEMaLvxn/O9ka0FQZ5CLUJ0yIKs/t # Tg4sS0QLgmpaXwSnscKoVE7aHWNFT1WomHI4SjWbwUQhmm0DmPizBZ2yX8dnSR24 # ubtzmxNYFWScrUTGQvbMhkU6I+Sc0Ca8APmPxErNV2mzF4p3CPE= # =Jvwi # -----END PGP SIGNATURE----- # gpg: Signature made Fri 31 Jan 2025 16:02:33 EST # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE
* tag 'hw-misc-20250131' of https://github.com/philmd/qemu: (36 commits) hw/sd: Remove unused SDState::enable hw/sd: Remove unused legacy functions, stop killing mammoths hw/sd: Remove unused 'enable' method from SDCardClass hw/sd/omap_mmc: Untabify hw/sd/omap_mmc: Remove unused coverswitch qemu_irq hw/arm/omap1: Inline creation of MMC hw/sd/omap_mmc: Use similar API for "wire up omap_clk" to other OMAP devices hw/sd/omap_mmc: Convert to SDBus API hw/sd/omap_mmc: Convert output qemu_irqs to gpio and sysbus IRQ APIs hw/sd/omap_mmc: Convert remaining 'struct omap_mmc_s' uses to OMAPMMCState hw/sd/omap_mmc: Do a minimal conversion to QDev hw/loader: Pass ELFDATA endian order argument to load_elf() hw/loader: Pass ELFDATA endian order argument to load_elf_as() hw/loader: Pass ELFDATA endian order argument to load_elf_ram_sym() hw/loader: Clarify local variable name in load_elf_ram_sym() hw/loader: Remove unused load_elf_ram() hw/avr/boot: Replace load_elf_ram_sym() -> load_elf_as() hw/usb/hcd-ehci: Fix debug printf format string hw/misc/i2c-echo: add tracing hw/char/pci-multi: Convert legacy qemu_allocate_irqs to qemu_init_irq ...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
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29df9104 |
| 21-Jan-2025 |
Philippe Mathieu-Daudé <philmd@linaro.org> |
hw/ipack: Clarify KConfig symbols
Split IPACK Kconfig key as {IPACK, TPCI200, IP_OCTAL_232}
- IPack is a bus - TPCI200 is a PCI device providing an IPack bus - IP-Octal232 is an IPack device
hw/ipack: Clarify KConfig symbols
Split IPACK Kconfig key as {IPACK, TPCI200, IP_OCTAL_232}
- IPack is a bus - TPCI200 is a PCI device providing an IPack bus - IP-Octal232 is an IPack device plugged on an IPack bus
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Acked-by: Fabiano Rosas <farosas@suse.de> Message-Id: <20250121155526.29982-3-philmd@linaro.org>
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20fac491 |
| 18-Jan-2025 |
Stefan Hajnoczi <stefanha@redhat.com> |
Merge tag 'qtest-20250117-pull-request' of https://gitlab.com/farosas/qemu into staging
Qtest pull request
- RISCV CSR test - migration recover changed to OOB - removal of dead code in test-x86-cpu
Merge tag 'qtest-20250117-pull-request' of https://gitlab.com/farosas/qemu into staging
Qtest pull request
- RISCV CSR test - migration recover changed to OOB - removal of dead code in test-x86-cpuid-compat
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* tag 'qtest-20250117-pull-request' of https://gitlab.com/farosas/qemu: tests/qtest/test-x86-cpuid-compat: Remove tests related to pc-i440fx-2.3 tests/qtest/migration: Use out-of-band execution for migrate-recover tests/qtest: Introduce qtest_init_with_env_and_capabilities() tests/qtest: QTest example for RISC-V CSR register target/riscv: Add RISC-V CSR qtest support
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
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b4a91c5e |
| 09-Jan-2025 |
Ivan Klokov <ivan.klokov@syntacore.com> |
tests/qtest: QTest example for RISC-V CSR register
Added demo for reading CSR register from qtest environment.
Signed-off-by: Ivan Klokov <ivan.klokov@syntacore.com> Reviewed-by: Fabiano Rosas <far
tests/qtest: QTest example for RISC-V CSR register
Added demo for reading CSR register from qtest environment.
Signed-off-by: Ivan Klokov <ivan.klokov@syntacore.com> Reviewed-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Fabiano Rosas <farosas@suse.de>
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