Merge tag 'pull-target-arm-20250211' of https://git.linaro.org/people/pmaydell/qemu-arm into staging

target-arm queue:
* target/alpha: Don't corrupt error_code with unknown softfloat flags
* targe

Merge tag 'pull-target-arm-20250211' of https://git.linaro.org/people/pmaydell/qemu-arm into staging

target-arm queue:
* target/alpha: Don't corrupt error_code with unknown softfloat flags
* target/arm: Implement FEAT_AFP and FEAT_RPRES

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# gpg: Signature made Tue 11 Feb 2025 11:24:04 EST
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full]
# gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE

* tag 'pull-target-arm-20250211' of https://git.linaro.org/people/pmaydell/qemu-arm: (68 commits)
target/arm: Sink fp_status and fpcr access into do_fmlal*
target/arm: Read fz16 from env->vfp.fpcr
target/arm: Simplify DO_VFP_cmp in vfp_helper.c
target/arm: Simplify fp_status indexing in mve_helper.c
target/arm: Remove fp_status_a32
target/arm: Remove fp_status_a64
target/arm: Remove fp_status_f16_a32
target/arm: Remove fp_status_f16_a64
target/arm: Remove ah_fp_status
target/arm: Remove ah_fp_status_f16
target/arm: Remove standard_fp_status
target/arm: Remove standard_fp_status_f16
target/arm: Introduce CPUARMState.vfp.fp_status[]
target/arm: Enable FEAT_RPRES for -cpu max
target/arm: Implement increased precision FRSQRTE
target/arm: Implement increased precision FRECPE
target/arm: Plumb FEAT_RPRES frecpe and frsqrte through to new helper
target/arm: Enable FEAT_AFP for '-cpu max'
target/arm: Handle FPCR.AH in SVE FMLSLB, FMLSLT (vectors)
target/arm: Handle FPCR.AH in SVE FMLSL (indexed)
...

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>

show more ...

fpu: allow flushing of output denormals to be after rounding

Currently we handle flushing of output denormals in uncanon_normal
always before we deal with rounding. This works for architectures
tha

fpu: allow flushing of output denormals to be after rounding

Currently we handle flushing of output denormals in uncanon_normal
always before we deal with rounding. This works for architectures
that detect tininess before rounding, but is usually not the right
place when the architecture detects tininess after rounding. For
example, for x86 the SDM states that the MXCSR FTZ control bit causes
outputs to be flushed to zero "when it detects a floating-point
underflow condition". This means that we mustn't flush to zero if
the input is such that after rounding it is no longer tiny.

At least one of our guest architectures does underflow detection
after rounding but flushing of denormals before rounding (MIPS MSA);
this means we need to have a config knob for this that is separate
from our existing tininess_before_rounding setting.

Add an ftz_detection flag. For consistency with
tininess_before_rounding, we make it default to "detect ftz after
rounding"; this means that we need to explicitly set the flag to
"detect ftz before rounding" on every existing architecture that sets
flush_to_zero, so that this commit has no behaviour change.
(This means more code change here but for the long term a less
confusing API.)

For several architectures the current behaviour is either
definitely or possibly wrong; annotate those with TODO comments.
These architectures are definitely wrong (and should detect
ftz after rounding):
* x86
* Alpha

For these architectures the spec is unclear:
* MIPS (for non-MSA)
* RX
* SH4

PA-RISC makes ftz detection IMPDEF, but we aren't setting the
"tininess before rounding" setting that we ought to.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

Merge tag 'pull-target-arm-20241211' of https://git.linaro.org/people/pmaydell/qemu-arm into staging

target-arm queue:
* hw/net/lan9118: Extract PHY model, reuse with imx_fec, fix bugs
* fpu: Make

Merge tag 'pull-target-arm-20241211' of https://git.linaro.org/people/pmaydell/qemu-arm into staging

target-arm queue:
* hw/net/lan9118: Extract PHY model, reuse with imx_fec, fix bugs
* fpu: Make muladd NaN handling runtime-selected, not compile-time
* fpu: Make default NaN pattern runtime-selected, not compile-time
* fpu: Minor NaN-related cleanups
* MAINTAINERS: email address updates

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# gpg: Signature made Wed 11 Dec 2024 11:18:38 EST
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full]
# gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE

* tag 'pull-target-arm-20241211' of https://git.linaro.org/people/pmaydell/qemu-arm: (72 commits)
MAINTAINERS: Add correct email address for Vikram Garhwal
MAINTAINERS: update email address for Leif Lindholm
softfloat: Replace WHICH with RET in parts_pick_nan
softfloat: Sink frac_cmp in parts_pick_nan until needed
softfloat: Share code between parts_pick_nan cases
softfloat: Inline pickNaN
softfloat: Use parts_pick_nan in propagateFloatx80NaN
softfloat: Move propagateFloatx80NaN to softfloat.c
softfloat: Pad array size in pick_nan_muladd
softfloat: Remove which from parts_pick_nan_muladd
softfloat: Use goto for default nan case in pick_nan_muladd
softfloat: Inline pickNaNMulAdd
fpu: Remove default handling for dnan_pattern
target/tricore: Set default NaN pattern explicitly
target/riscv: Set default NaN pattern explicitly
target/hexagon: Set default NaN pattern explicitly
target/xtensa: Set default NaN pattern explicitly
target/sparc: Set default NaN pattern explicitly
target/s390x: Set default NaN pattern explicitly
target/rx: Set default NaN pattern explicitly
...

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>

show more ...

tests/fp: Set default NaN pattern explicitly

Set the default NaN pattern explicitly for the tests/fp code.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <ri

tests/fp: Set default NaN pattern explicitly

Set the default NaN pattern explicitly for the tests/fp code.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241202131347.498124-36-peter.maydell@linaro.org

show more ...

tests/fp: Explicitly set 3-NaN propagation rule

Explicitly set a rule in the softfloat tests for propagating NaNs in
the muladd case. In meson.build we put -DTARGET_ARM in fpcflags, and
so we shoul

tests/fp: Explicitly set 3-NaN propagation rule

Explicitly set a rule in the softfloat tests for propagating NaNs in
the muladd case. In meson.build we put -DTARGET_ARM in fpcflags, and
so we should select here the Arm rule of float_3nan_prop_s_cab.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241202131347.498124-17-peter.maydell@linaro.org

show more ...

tests/fp: Explicitly set inf-zero-nan rule

Explicitly set a rule in the softfloat tests for the inf-zero-nan
muladd special case. In meson.build we put -DTARGET_ARM in fpcflags,
and so we should se

tests/fp: Explicitly set inf-zero-nan rule

Explicitly set a rule in the softfloat tests for the inf-zero-nan
muladd special case. In meson.build we put -DTARGET_ARM in fpcflags,
and so we should select here the Arm rule of
float_infzeronan_dnan_if_qnan.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20241202131347.498124-5-peter.maydell@linaro.org

show more ...

Merge tag 'pull-target-arm-20241105' of https://git.linaro.org/people/pmaydell/qemu-arm into staging

target-arm queue:
* Fix MMU indexes for AArch32 Secure PL1&0 in a less complex and buggy way
*

Merge tag 'pull-target-arm-20241105' of https://git.linaro.org/people/pmaydell/qemu-arm into staging

target-arm queue:
* Fix MMU indexes for AArch32 Secure PL1&0 in a less complex and buggy way
* Fix SVE SDOT/UDOT/USDOT (4-way, indexed)
* softfloat: set 2-operand NaN propagation rule at runtime
* disas: Fix build against Capstone v6 (again)
* hw/rtc/ds1338: Trace send and receive operations
* hw/timer/imx_gpt: Convert DPRINTF to trace events
* hw/watchdog/wdt_imx2: Remove redundant assignment
* hw/sensor/tmp105: Convert printf() to trace event, add tracing for read/write access
* hw/net/npcm_gmac: Change error log to trace event
* target/arm: Enable FEAT_CMOW for -cpu max

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# gpg: Signature made Tue 05 Nov 2024 11:19:06 GMT
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# gpg: aka "Peter Maydell <peter@archaic.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE

* tag 'pull-target-arm-20241105' of https://git.linaro.org/people/pmaydell/qemu-arm: (31 commits)
target/arm: Enable FEAT_CMOW for -cpu max
hw/net/npcm_gmac: Change error log to trace event
hw/sensor/tmp105: Convert printf() to trace event, add tracing for read/write access
hw/watchdog/wdt_imx2: Remove redundant assignment
hw/timer/imx_gpt: Convert DPRINTF to trace events
hw/rtc/ds1338: Trace send and receive operations
disas: Fix build against Capstone v6 (again)
target/arm: Fix SVE SDOT/UDOT/USDOT (4-way, indexed)
target/arm: Add new MMU indexes for AArch32 Secure PL1&0
Revert "target/arm: Fix usage of MMU indexes when EL3 is AArch32"
softfloat: Remove fallback rule from pickNaN()
target/rx: Explicitly set 2-NaN propagation rule
target/openrisc: Explicitly set 2-NaN propagation rule
target/microblaze: Explicitly set 2-NaN propagation rule
target/microblaze: Move setting of float rounding mode to reset
target/alpha: Explicitly set 2-NaN propagation rule
target/i386: Set 2-NaN propagation rule explicitly
target/xtensa: Explicitly set 2-NaN propagation rule
target/xtensa: Factor out calls to set_use_first_nan()
target/sparc: Explicitly set 2-NaN propagation rule
...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...

tests/fp: Explicitly set 2-NaN propagation rule

Explicitly set a 2-NaN propagation rule in the softfloat tests. In
meson.build we put -DTARGET_ARM in fpcflags, and so we should select
here the Arm

tests/fp: Explicitly set 2-NaN propagation rule

Explicitly set a 2-NaN propagation rule in the softfloat tests. In
meson.build we put -DTARGET_ARM in fpcflags, and so we should select
here the Arm propagation rule of float_2nan_prop_s_ab.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241025141254.2141506-3-peter.maydell@linaro.org

show more ...

Merge tag 'misc-pull-request' of gitlab.com:marcandre.lureau/qemu into staging

Misc cleanups

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Merge tag 'misc-pull-request' of gitlab.com:marcandre.lureau/qemu into staging

Misc cleanups

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# -----END PGP SIGNATURE-----
# gpg: Signature made Thu 21 Apr 2022 06:47:55 AM PDT
# gpg: using RSA key 87A9BD933F87C606D276F62DDAE8E10975969CE5
# gpg: issuer "marcandre.lureau@redhat.com"
# gpg: Good signature from "Marc-André Lureau <marcandre.lureau@redhat.com>" [full]
# gpg: aka "Marc-André Lureau <marcandre.lureau@gmail.com>" [full]

* tag 'misc-pull-request' of gitlab.com:marcandre.lureau/qemu: (30 commits)
qga: use fixed-length and GDateTime for log timestamp
tests/fuzz: fix warning
qga: remove need for QEMU atomic.h
util: replace qemu_get_local_state_pathname()
util: use qemu_create() in qemu_write_pidfile()
util: use qemu_write_full() in qemu_write_pidfile()
util: simplify write in signal handler
qtest: simplify socket_send()
qga: move qga_get_host_name()
Move error_printf_unless_qmp() with monitor unit
tests: run-time skip test-qga if TSAN is enabled
compiler.h: add QEMU_SANITIZE_{ADDRESS,THREAD}
tests: remove block/qdict checks from check-qobject.c
include: move qdict_{crumple,flatten} declarations
include: add qemu/keyval.h
include: move qemu_fdatasync() to osdep
include: move qemu_msync() to osdep
compiler.h: replace QEMU_NORETURN with G_NORETURN
osdep.h: move qemu_build_not_reached()
doc/style: CLang -> Clang
...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

compiler.h: replace QEMU_NORETURN with G_NORETURN

G_NORETURN was introduced in glib 2.68, fallback to G_GNUC_NORETURN in
glib-compat.

Note that this attribute must be placed before the function dec

compiler.h: replace QEMU_NORETURN with G_NORETURN

G_NORETURN was introduced in glib 2.68, fallback to G_GNUC_NORETURN in
glib-compat.

Note that this attribute must be placed before the function declaration
(bringing a bit of consistency in qemu codebase usage).

Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Warner Losh <imp@bsdimp.com>
Message-Id: <20220420132624.2439741-20-marcandre.lureau@redhat.com>

show more ...

Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-fp-20210516' into staging

Reorg FloatParts to use QEMU_GENERIC.
Begin replacing the Berkeley float128 routines with FloatParts128.
- incl

Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-fp-20210516' into staging

Reorg FloatParts to use QEMU_GENERIC.
Begin replacing the Berkeley float128 routines with FloatParts128.
- includes a new implementation of float128_muladd
- includes the snan silencing that was missing from
float{32,64}_to_float128 and float128_to_float{32,64}.
- does not include float128_min/max* (written but not yet reviewed).

# gpg: Signature made Sun 16 May 2021 13:27:10 BST
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F

* remotes/rth-gitlab/tags/pull-fp-20210516: (46 commits)
softfloat: Move round_to_int_and_pack to softfloat-parts.c.inc
softfloat: Move round_to_int to softfloat-parts.c.inc
softfloat: Convert float-to-float conversions with float128
softfloat: Split float_to_float
softfloat: Move div_floats to softfloat-parts.c.inc
softfloat: Introduce sh[lr]_double primitives
softfloat: Tidy mul128By64To192
softfloat: Use add192 in mul128To256
softfloat: Use mulu64 for mul64To128
softfloat: Move muladd_floats to softfloat-parts.c.inc
softfloat: Move mul_floats to softfloat-parts.c.inc
softfloat: Implement float128_add/sub via parts
softfloat: Move addsub_floats to softfloat-parts.c.inc
softfloat: Use uadd64_carry, usub64_borrow in softfloat-macros.h
softfloat: Move round_canonical to softfloat-parts.c.inc
softfloat: Move sf_canonicalize to softfloat-parts.c.inc
softfloat: Move pick_nan_muladd to softfloat-parts.c.inc
softfloat: Move pick_nan to softfloat-parts.c.inc
softfloat: Move return_nan to softfloat-parts.c.inc
softfloat: Convert float128_default_nan to parts
...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

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softfloat: Move muladd_floats to softfloat-parts.c.inc

Rename to parts$N_muladd.
Implement float128_muladd with FloatParts128.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richa

softfloat: Move muladd_floats to softfloat-parts.c.inc

Rename to parts$N_muladd.
Implement float128_muladd with FloatParts128.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

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tests/fp: add quad support to the benchmark utility

Currently this only support softfloat calculations because working out
if the hardware supports 128 bit floats needs configure magic. The 3
op mul

tests/fp: add quad support to the benchmark utility

Currently this only support softfloat calculations because working out
if the hardware supports 128 bit floats needs configure magic. The 3
op muladd operation is currently unimplemented so commented out for
now.

Reviewed-by: David Hildenbrand <david@redhat.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20201020163738.27700-8-alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

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Merge remote-tracking branch 'remotes/stsquad/tags/pull-fpu-next-230119-2' into staging

Some more softfloat/fpu fixes

- make check-softfloat
- fixes for fp-bench
- workaround broken host f

Merge remote-tracking branch 'remotes/stsquad/tags/pull-fpu-next-230119-2' into staging

Some more softfloat/fpu fixes

- make check-softfloat
- fixes for fp-bench
- workaround broken host fma
- compile fix for s390x/clang
- fixed for bigendian (v2)
- minor makefile tweaks (v2)

# gpg: Signature made Wed 23 Jan 2019 11:37:53 GMT
# gpg: using RSA key FBD0DB095A9E2A44
# gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>"
# Primary key fingerprint: 6685 AE99 E751 67BC AFC8 DF35 FBD0 DB09 5A9E 2A44

* remotes/stsquad/tags/pull-fpu-next-230119-2:
tests/Makefile: add check-softfloat rule
scripts/archive-source: include softfloat tests
tests/Makefile: add floating point tests
include/fpu/softfloat: Fix compilation with Clang on s390x
softfloat: enforce softfloat if the host's FMA is broken
tests/fp/platform.h: include config-host.h
fp-test: fix signature of slow_clear_flags and qemu_clear_flags
tests/fp/Makefile: do not use gcc-only -W flags
berkeley-testfloat-3: pull changes
fp-bench: remove wrong exponent raise in fill_random
fp-bench: fix update_random_ops

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

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fp-bench: remove wrong exponent raise in fill_random

At this point random_ops[] only contains normals, so there's
no need to do anything to them. In fact, raising the exponent
here can make the outp

fp-bench: remove wrong exponent raise in fill_random

At this point random_ops[] only contains normals, so there's
no need to do anything to them. In fact, raising the exponent
here can make the output !normal, which is precisely
what the comment says we want to avoid.

Signed-off-by: Emilio G. Cota <cota@braap.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>

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fp-bench: fix update_random_ops

The second test in the branches is wrong; fix while converting
to a switch statement, which is easier to get right.

Signed-off-by: Emilio G. Cota <cota@braap.org>
Re

fp-bench: fix update_random_ops

The second test in the branches is wrong; fix while converting
to a switch statement, which is easier to get right.

Signed-off-by: Emilio G. Cota <cota@braap.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>

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Merge remote-tracking branch 'remotes/stsquad/tags/pull-hardfloat-and-gitdm-171218-3' into staging

Hardfloat + maintainers and gitdm

# gpg: Signature made Mon 17 Dec 2018 10:55:19 GMT
# gpg:

Merge remote-tracking branch 'remotes/stsquad/tags/pull-hardfloat-and-gitdm-171218-3' into staging

Hardfloat + maintainers and gitdm

# gpg: Signature made Mon 17 Dec 2018 10:55:19 GMT
# gpg: using RSA key FBD0DB095A9E2A44
# gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>"
# Primary key fingerprint: 6685 AE99 E751 67BC AFC8 DF35 FBD0 DB09 5A9E 2A44

* remotes/stsquad/tags/pull-hardfloat-and-gitdm-171218-3:
hardfloat: implement float32/64 comparison
hardfloat: implement float32/64 square root
hardfloat: implement float32/64 fused multiply-add
hardfloat: implement float32/64 division
hardfloat: implement float32/64 multiplication
hardfloat: implement float32/64 addition and subtraction
fpu: introduce hardfloat
tests/fp: add fp-bench
softfloat: add float{32,64}_is_zero_or_normal
softfloat: rename canonicalize to sf_canonicalize
target/tricore: use float32_is_denormal
softfloat: add float{32,64}_is_{de,}normal
fp-test: pick TARGET_ARM to get its specialization
MAINTAINERS: update status of FPU emulation
contrib: add a basic gitdm config

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

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tests/fp: add fp-bench

These microbenchmarks will allow us to measure the performance impact of
FP emulation optimizations. Note that we can measure both directly the impact
on the softfloat functio

tests/fp: add fp-bench

These microbenchmarks will allow us to measure the performance impact of
FP emulation optimizations. Note that we can measure both directly the impact
on the softfloat functions (with "-t soft"), or the impact on an
emulated workload (call with "-t host" and run under qemu user-mode).

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>

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