Merge tag 'pull-tcg-20250429' of https://gitlab.com/rth7680/qemu into staging

Convert TCG backend code generators to TCGOutOp structures,
decomposing the monolithic tcg_out_op functions.

# -----BEG

Merge tag 'pull-tcg-20250429' of https://gitlab.com/rth7680/qemu into staging

Convert TCG backend code generators to TCGOutOp structures,
decomposing the monolithic tcg_out_op functions.

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# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F

* tag 'pull-tcg-20250429' of https://gitlab.com/rth7680/qemu: (161 commits)
tcg/sparc64: Implement CTPOP
tcg/sparc64: Unexport use_vis3_instructions
tcg: Remove tcg_out_op
tcg: Convert qemu_st{2} to TCGOutOpLdSt{2}
tcg: Convert qemu_ld{2} to TCGOutOpLoad{2}
tcg: Merge INDEX_op_{ld,st}_{i32,i64,i128}
tcg: Remove INDEX_op_qemu_st8_*
tcg: Stash MemOp size in TCGOP_FLAGS
tcg: Merge INDEX_op_st*_{i32,i64}
tcg: Convert st to TCGOutOpStore
tcg: Merge INDEX_op_ld*_{i32,i64}
tcg: Convert ld to TCGOutOpLoad
tcg: Formalize tcg_out_goto_ptr
tcg: Formalize tcg_out_br
tcg: Formalize tcg_out_mb
tcg: Remove add2/sub2 opcodes
tcg/tci: Implement add/sub carry opcodes
tcg/sparc64: Implement add/sub carry opcodes
tcg/sparc64: Hoist tcg_cond_to_bcond lookup out of tcg_out_movcc
tcg/s390x: Use ADD LOGICAL WITH SIGNED IMMEDIATE
...

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>

show more ...

tcg: Add TCGType to tcg_op_insert_{after,before}

We cannot rely on the value copied from TCGOP_TYPE(op), because
the relevant op could be typeless, such as INDEX_op_call.

Fixes: fb744ece3a78 ("tcg:

tcg: Add TCGType to tcg_op_insert_{after,before}

We cannot rely on the value copied from TCGOP_TYPE(op), because
the relevant op could be typeless, such as INDEX_op_call.

Fixes: fb744ece3a78 ("tcg: Copy TCGOP_TYPE in tcg_op_insert_{after,before}")
Suggested-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

Merge tag 'pull-tcg-20250423' of https://gitlab.com/rth7680/qemu into staging

meson: Introduce top-level libuser_ss and libsystem_ss
meson: Add hw_common_arch dictionary
accel/tcg: Lots of cleanups

Merge tag 'pull-tcg-20250423' of https://gitlab.com/rth7680/qemu into staging

meson: Introduce top-level libuser_ss and libsystem_ss
meson: Add hw_common_arch dictionary
accel/tcg: Lots of cleanups to enable build once for:
user-exec-stub.c,
plugin-gen.c,
translator.c
page-vary: Restrict scope of TARGET_PAGE_BITS_MIN
tcg: Always define TARGET_INSN_START_EXTRA_WORDS
tcg: Convert TARGET_GUEST_DEFAULT_MO to TCGCPUOps::guest_default_memory_order
tcg: Convert TARGET_SUPPORTS_MTTCG to TCGCPUOps::mttcg_supported field
target/riscv: Do not expose rv128 CPU on user mode emulation

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* tag 'pull-tcg-20250423' of https://gitlab.com/rth7680/qemu: (148 commits)
tcg: Convert TARGET_SUPPORTS_MTTCG to TCGCPUOps::mttcg_supported field
target/i386: Remove AccelCPUClass::cpu_class_init need
target/riscv: Remove AccelCPUClass::cpu_class_init need
accel/tcg: Move mttcg warning to tcg_init_machine
tcg: Convert TCGState::mttcg_enabled to TriState
accel/tcg: Remove mttcg_enabled
tcg: Move qemu_tcg_mttcg_enabled() to 'system/tcg.h'
tcg: Pass max_threads not max_cpus to tcg_init
tcg: Move cpu_req_mo() macro to target-agnostic 'backend-ldst.h'
tcg: Remove the TCG_GUEST_DEFAULT_MO definition globally
tcg: Have tcg_req_mo() use TCGCPUOps::guest_default_memory_order
tcg: Propagate CPUState argument to cpu_req_mo()
tcg: Remove use of TCG_GUEST_DEFAULT_MO in tb_gen_code()
tcg: Define guest_default_memory_order in TCGCPUOps
tcg: Simplify tcg_req_mo() macro
tcg: Always define TCG_GUEST_DEFAULT_MO
exec: Do not include 'accel/tcg/cpu-ldst.h' in 'exec-all.h'
exec: Restrict 'cpu_ldst.h' to accel/tcg/
exec: Restrict 'cpu-ldst-common.h' to accel/tcg/
tcg: Always define TARGET_INSN_START_EXTRA_WORDS
...

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>

show more ...

tcg: Pass max_threads not max_cpus to tcg_init

In effect, hoist the check for mttcg from tcg_n_regions()
to tcg_init_machine().

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by:

tcg: Pass max_threads not max_cpus to tcg_init

In effect, hoist the check for mttcg from tcg_n_regions()
to tcg_init_machine().

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

Merge tag 'pull-tcg-20250117' of https://gitlab.com/rth7680/qemu into staging

tcg:
- Add TCGOP_TYPE, TCGOP_FLAGS.
- Pass type and flags to tcg_op_supported, tcg_target_op_def.
- Split out tcg-

Merge tag 'pull-tcg-20250117' of https://gitlab.com/rth7680/qemu into staging

tcg:
- Add TCGOP_TYPE, TCGOP_FLAGS.
- Pass type and flags to tcg_op_supported, tcg_target_op_def.
- Split out tcg-target-has.h and unexport from tcg.h.
- Reorg constraint processing; constify TCGOpDef.
- Make extract, sextract, deposit opcodes mandatory.
- Merge ext{8,16,32}{s,u} opcodes into {s}extract.
tcg/mips: Expand bswap unconditionally
tcg/riscv: Use SRAIW, SRLIW for {s}extract_i64
tcg/riscv: Use BEXTI for single-bit extractions
tcg/sparc64: Use SRA, SRL for {s}extract_i64

disas/riscv: Guard dec->cfg dereference for host disassemble
util/cpuinfo-riscv: Detect Zbs
accel/tcg: Call tcg_tb_insert() for one-insn TBs
linux-user: Add missing /proc/cpuinfo fields for sparc

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* tag 'pull-tcg-20250117' of https://gitlab.com/rth7680/qemu: (68 commits)
softfloat: Constify helpers returning float_status field
accel/tcg: Call tcg_tb_insert() for one-insn TBs
tcg: Document tb_lookup() and tcg_tb_lookup()
linux-user: Add missing /proc/cpuinfo fields for sparc
tcg/riscv: Use BEXTI for single-bit extractions
util/cpuinfo-riscv: Detect Zbs
tcg: Remove TCG_TARGET_HAS_deposit_{i32,i64}
tcg: Remove TCG_TARGET_HAS_{s}extract_{i32,i64}
tcg/tci: Remove assertions for deposit and extract
tcg/tci: Provide TCG_TARGET_{s}extract_valid
tcg/sparc64: Use SRA, SRL for {s}extract_i64
tcg/s390x: Fold the ext{8,16,32}[us] cases into {s}extract
tcg/riscv: Use SRAIW, SRLIW for {s}extract_i64
tcg/riscv64: Fold the ext{8,16,32}[us] cases into {s}extract
tcg/ppc: Fold the ext{8,16,32}[us] cases into {s}extract
tcg/mips: Fold the ext{8,16,32}[us] cases into {s}extract
tcg/loongarch64: Fold the ext{8,16,32}[us] cases into {s}extract
tcg/arm: Add full [US]XT[BH] into {s}extract
tcg/aarch64: Expand extract with offset 0 with andi
tcg/aarch64: Provide TCG_TARGET_{s}extract_valid
...

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>

show more ...

tcg: Move tcg_op_insert_{after,before} decls to tcg-internal.h

These are not particularly useful outside of optimization passes.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-b

tcg: Move tcg_op_insert_{after,before} decls to tcg-internal.h

These are not particularly useful outside of optimization passes.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

tcg: Replace TCGOP_VECL with TCGOP_TYPE

In the replacement, drop the TCGType - TCG_TYPE_V64 adjustment,
except for the call to tcg_out_vec_op. Pass type to tcg_gen_op[1-6],
so that all integer opco

tcg: Replace TCGOP_VECL with TCGOP_TYPE

In the replacement, drop the TCGType - TCG_TYPE_V64 adjustment,
except for the call to tcg_out_vec_op. Pass type to tcg_gen_op[1-6],
so that all integer opcodes gain the type.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

Merge tag 'pull-tcg-20240922' of https://gitlab.com/rth7680/qemu into staging

target/ppc: Fix lxvx/stxvx facility check
linux-user: update syscall_nr.h to Linux v6.10
linux-user: update syscall.tbl

Merge tag 'pull-tcg-20240922' of https://gitlab.com/rth7680/qemu into staging

target/ppc: Fix lxvx/stxvx facility check
linux-user: update syscall_nr.h to Linux v6.10
linux-user: update syscall.tbl to Linux v6.11
tcg: Fix iteration step in 32-bit gvec operation
tcg: Propagate new TCGOp to add_as_label_use
tcg/*: Do not expand cmp_vec, cmpsel_vec early
tcg/optimize: Fold movcond with true and false values identical
tcg/optimize: Optimize cmp_vec and cmpsel_vec
tcg/optimize: Optimize bitsel_vec
tcg/i386: Optimize cmpsel with constant 0 operand 3.
tcg/i386: Implement cmp_vec with avx512 insns
tcg/i386: Implement cmpsel_vec with avx512 insns
tcg/i386: Implement vector TST{EQ,NE} for avx512
tcg/ppc: Implement cmpsel_vec and optimize with constant 0/-1 arguments
tcg/s390x: Implement cmpsel_vec and optimize with constant 0/-1 arguments

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# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F

* tag 'pull-tcg-20240922' of https://gitlab.com/rth7680/qemu: (31 commits)
linux-user: update syscall.tbl to Linux v6.11
linux-user,loongarch: move to syscalltbl file
linux-user,hexagon: move to syscalltbl file
linux-user,riscv: move to syscalltbl file
linux-user,openrisc: move to syscalltbl file
linux-user,aarch64: move to syscalltbl file
linux-user: update syscall.tbl to Linux v6.10
linux-user, mips: update syscall-args-o32.c.inc to Linux v6.10
linux-user: update syscall_nr.h to Linux v6.10
target/ppc: Fix lxvx/stxvx facility check
tcg/s390x: Optimize cmpsel with constant 0/-1 arguments
tcg/s390x: Implement cmpsel_vec
tcg/ppc: Optimize cmpsel with constant 0/-1 arguments
tcg/ppc: Implement cmpsel_vec
tcg/i386: Implement vector TST{EQ,NE} for avx512
tcg/i386: Implement cmpsel_vec with avx512 insns
tcg/i386: Add predicate parameters to tcg_out_evex_opc
tcg/i386: Implement cmp_vec with avx512 insns
tcg/i386: Optimize cmpsel with constant 0 operand 3.
tcg/optimize: Optimize bitsel_vec
...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...

tcg: Export vec_gen_6

Add declaration to tcg-internal.h, making it available for
use from tcg backend vector expanders.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richar

tcg: Export vec_gen_6

Add declaration to tcg-internal.h, making it available for
use from tcg backend vector expanders.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

tcg: Return TCGOp from tcg_gen_op[1-6]

TCGOp to be propagated further in the next patch.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org

tcg: Return TCGOp from tcg_gen_op[1-6]

TCGOp to be propagated further in the next patch.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

Merge tag 'pull-tcg-20240205-2' of https://gitlab.com/rth7680/qemu into staging

tcg: Introduce TCG_COND_TST{EQ,NE}
target/alpha: Use TCG_COND_TST{EQ,NE}
target/m68k: Use TCG_COND_TST{EQ,NE} in gen_f

Merge tag 'pull-tcg-20240205-2' of https://gitlab.com/rth7680/qemu into staging

tcg: Introduce TCG_COND_TST{EQ,NE}
target/alpha: Use TCG_COND_TST{EQ,NE}
target/m68k: Use TCG_COND_TST{EQ,NE} in gen_fcc_cond
target/sparc: Use TCG_COND_TSTEQ in gen_op_mulscc
target/s390x: Use TCG_COND_TSTNE for CC_OP_{TM,ICM}
target/s390x: Improve general case of disas_jcc

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* tag 'pull-tcg-20240205-2' of https://gitlab.com/rth7680/qemu: (39 commits)
tcg/tci: Support TCG_COND_TST{EQ,NE}
tcg/s390x: Support TCG_COND_TST{EQ,NE}
tcg/s390x: Add TCG_CT_CONST_CMP
tcg/s390x: Split constraint A into J+U
tcg/ppc: Support TCG_COND_TST{EQ,NE}
tcg/ppc: Add TCG_CT_CONST_CMP
tcg/ppc: Tidy up tcg_target_const_match
tcg/ppc: Use cr0 in tcg_to_bc and tcg_to_isel
tcg/ppc: Sink tcg_to_bc usage into tcg_out_bc
tcg/sparc64: Support TCG_COND_TST{EQ,NE}
tcg/sparc64: Pass TCGCond to tcg_out_cmp
tcg/sparc64: Hoist read of tcg_cond_to_rcond
tcg/i386: Use TEST r,r to test 8/16/32 bits
tcg/i386: Improve TSTNE/TESTEQ vs powers of two
tcg/i386: Support TCG_COND_TST{EQ,NE}
tcg/i386: Move tcg_cond_to_jcc[] into tcg_out_cmp
tcg/i386: Pass x86 condition codes to tcg_out_cmov
tcg/arm: Support TCG_COND_TST{EQ,NE}
tcg/arm: Split out tcg_out_cmp()
tcg/aarch64: Generate CBNZ for TSTNE of UINT32_MAX
...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...

tcg/optimize: Lower TCG_COND_TST{EQ,NE} if unsupported

After having performed other simplifications, lower any
remaining test comparisons with AND.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linar

tcg/optimize: Lower TCG_COND_TST{EQ,NE} if unsupported

After having performed other simplifications, lower any
remaining test comparisons with AND.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

Merge tag 'pull-tcg-20231106' of https://gitlab.com/rth7680/qemu into staging

util: Add cpuinfo for loongarch64
tcg/loongarch64: Use cpuinfo.h
tcg/loongarch64: Improve register allocation for INDEX_

Merge tag 'pull-tcg-20231106' of https://gitlab.com/rth7680/qemu into staging

util: Add cpuinfo for loongarch64
tcg/loongarch64: Use cpuinfo.h
tcg/loongarch64: Improve register allocation for INDEX_op_qemu_ld_a*_i128
host/include/loongarch64: Add atomic16 load and store
tcg: Move expanders out of line
tcg/mips: Always implement movcond
tcg/mips: Implement neg opcodes
tcg/loongarch64: Implement neg opcodes
tcg: Make movcond and neg required opcodes
tcg: Optimize env memory operations
tcg: Canonicalize sub of immediate to add
tcg/sparc64: Implement tcg_out_extrl_i64_i32

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# gpg: Signature made Tue 07 Nov 2023 10:47:25 HKT
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F

* tag 'pull-tcg-20231106' of https://gitlab.com/rth7680/qemu: (35 commits)
tcg/sparc64: Implement tcg_out_extrl_i64_i32
tcg/optimize: Canonicalize sub2 with constants to add2
tcg/optimize: Canonicalize subi to addi during optimization
tcg: Canonicalize subi to addi during opcode generation
tcg/optimize: Split out arg_new_constant
tcg: Eliminate duplicate env store operations
tcg/optimize: Optimize env memory operations
tcg/optimize: Split out cmp_better_copy
tcg/optimize: Pipe OptContext into reset_ts
tcg: Don't free vector results
tcg: Remove TCG_TARGET_HAS_neg_{i32,i64}
tcg/loongarch64: Implement neg opcodes
tcg/mips: Implement neg opcodes
tcg: Remove TCG_TARGET_HAS_movcond_{i32,i64}
tcg/mips: Always implement movcond
tcg/mips: Split out tcg_out_setcond_int
tcg: Move tcg_temp_free_* out of line
tcg: Move tcg_temp_new_*, tcg_global_mem_new_* out of line
tcg: Move tcg_constant_* out of line
tcg: Unexport tcg_gen_op*_{i32,i64}
...

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>

show more ...

tcg: Move tcg_constant_* out of line

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20231029210848.78234-10-richard.henderson@linaro.org>

tcg: Move tcg_gen_opN declarations to tcg-internal.h

These are used within tcg-op.c and tcg-op-ldst.c.
There are no uses outside tcg/.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org

tcg: Move tcg_gen_opN declarations to tcg-internal.h

These are used within tcg-op.c and tcg-op-ldst.c.
There are no uses outside tcg/.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20231029210848.78234-8-richard.henderson@linaro.org>

show more ...

tcg: Move vec_gen_* declarations to tcg-internal.h

These are used within tcg-op-vec.c and tcg/host/tcg-target.c.inc.
There are no uses outside tcg/.

Signed-off-by: Richard Henderson <richard.hender

tcg: Move vec_gen_* declarations to tcg-internal.h

These are used within tcg-op-vec.c and tcg/host/tcg-target.c.inc.
There are no uses outside tcg/.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20231029210848.78234-7-richard.henderson@linaro.org>

show more ...

Merge tag 'misc-20230831' of https://github.com/philmd/qemu into staging

Misc patches queue

Build fixes:
- Only define OS_OBJECT_USE_OBJC with gcc

Overall cleanups:
- Do not declare function proto

Merge tag 'misc-20230831' of https://github.com/philmd/qemu into staging

Misc patches queue

Build fixes:
- Only define OS_OBJECT_USE_OBJC with gcc

Overall cleanups:
- Do not declare function prototypes using 'extern' keyword
- Remove unmaintained HAX accelerator
- Have FEWatchFunc handlers return G_SOURCE_CONTINUE/REMOVE instead of boolean
- Avoid modifying QOM class internals from instance in pmbus_device
- Avoid variable-length array in xhci_get_port_bandwidth
- Remove unuseful kvmclock_create() stub
- Style: permit inline loop variables
- Various header cleanups
- Various spelling fixes

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# gpg: Signature made Thu 31 Aug 2023 13:48:53 EDT
# gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE

* tag 'misc-20230831' of https://github.com/philmd/qemu: (39 commits)
build: Only define OS_OBJECT_USE_OBJC with gcc
tests/tcg/aarch64: Rename bti-crt.inc.c -> bti-crt.c.inc
ui: spelling fixes
util: spelling fixes
util/fifo8: Fix typo in fifo8_push_all() description
hw/i386: Rename 'hw/kvm/clock.h' -> 'hw/i386/kvm/clock.h'
hw/i386: Remove unuseful kvmclock_create() stub
hw/usb/hcd-xhci: Avoid variable-length array in xhci_get_port_bandwidth()
hw/usb: spelling fixes
hw/sd: spelling fixes
hw/mips: spelling fixes
hw/display: spelling fixes
hw/ide: spelling fixes
hw/i2c: spelling fixes
hw/i2c/pmbus_device: Fix modifying QOM class internals from instance
hw/char/pl011: Replace magic values by register field definitions
hw/char/pl011: Remove duplicated PL011_INT_[RT]X definitions
hw/char/pl011: Display register name in trace events
hw/char/pl011: Restrict MemoryRegionOps implementation access sizes
hw/char: Have FEWatchFunc handlers return G_SOURCE_CONTINUE/REMOVE
...

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>

show more ...

bulk: Do not declare function prototypes using 'extern' keyword

By default, C function prototypes declared in headers are visible,
so there is no need to declare them as 'extern' functions.
Remove t

bulk: Do not declare function prototypes using 'extern' keyword

By default, C function prototypes declared in headers are visible,
so there is no need to declare them as 'extern' functions.
Remove this redundancy in a single bulk commit; do not modify:

- meson.build (used to check function availability at runtime)
- pc-bios/
- libdecnumber/
- tests/
- *.c

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20230605175647.88395-5-philmd@linaro.org>

show more ...

Merge tag 'pull-tcg-20230605' of https://gitlab.com/rth7680/qemu into staging

Build tcg/ once for system and once for user.
Unmap perf_marker.
Remove left over _link_error() definitions.

# -----BEG

Merge tag 'pull-tcg-20230605' of https://gitlab.com/rth7680/qemu into staging

Build tcg/ once for system and once for user.
Unmap perf_marker.
Remove left over _link_error() definitions.

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# gpg: Signature made Mon 05 Jun 2023 01:13:29 PM PDT
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [ultimate]

* tag 'pull-tcg-20230605' of https://gitlab.com/rth7680/qemu: (52 commits)
tcg/tcg-op-vec: Remove left over _link_error() definitions
accel/tcg: Unmap perf_marker
tcg: Build once for system and once for user-only
exec/poison: Do not poison CONFIG_SOFTMMU
plugins: Drop unused headers from exec/plugin-gen.h
plugins: Move plugin_insn_append to translator.c
tcg: Remove target-specific headers from tcg.[ch]
tcg: Move env defines out of NEED_CPU_H in helper-head.h
tcg: Fix PAGE/PROT confusion
accel/tcg: Tidy includes for translator.[ch]
target/arm: Add missing include of exec/exec-all.h
target/*: Add missing includes of exec/translation-block.h
target/mips: Tidy helpers for translation
target/arm: Tidy helpers for translation
accel/tcg: Move translator_fake_ldb out of line
target/ppc: Inline gen_icount_io_start()
accel/tcg: Introduce translator_io_start
accel/tcg: Move most of gen-icount.h into translator.c
include/exec: Remove CODE_GEN_AVG_BLOCK_SIZE
tcg: Spit out exec/translation-block.h
...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

tcg: Move TCGHelperInfo and dependencies to tcg/helper-info.h

This will be required outside of tcg-internal.h soon.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard He

tcg: Move TCGHelperInfo and dependencies to tcg/helper-info.h

This will be required outside of tcg-internal.h soon.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

Merge tag 'pull-tcg-20230516-3' of https://gitlab.com/rth7680/qemu into staging

tcg/i386: Fix tcg_out_addi_ptr for win64
tcg: Implement atomicity for TCGv_i128
tcg: First quarter of cleanups for bui

Merge tag 'pull-tcg-20230516-3' of https://gitlab.com/rth7680/qemu into staging

tcg/i386: Fix tcg_out_addi_ptr for win64
tcg: Implement atomicity for TCGv_i128
tcg: First quarter of cleanups for building tcg once

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# gpg: Signature made Tue 16 May 2023 09:29:35 PM PDT
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [ultimate]

* tag 'pull-tcg-20230516-3' of https://gitlab.com/rth7680/qemu: (74 commits)
tcg: Split out exec/user/guest-base.h
tcg: Add tlb_dyn_max_bits to TCGContext
tcg: Add page_bits and page_mask to TCGContext
tcg: Remove TARGET_LONG_BITS, TCG_TYPE_TL
tcg/mips: Remove TARGET_LONG_BITS, TCG_TYPE_TL
tcg/loongarch64: Remove TARGET_LONG_BITS, TCG_TYPE_TL
tcg/aarch64: Remove TARGET_LONG_BITS, TCG_TYPE_TL
tcg/aarch64: Remove USE_GUEST_BASE
tcg/arm: Remove TARGET_LONG_BITS
tcg/i386: Remove TARGET_LONG_BITS, TCG_TYPE_TL
tcg/i386: Adjust type of tlb_mask
tcg/i386: Conditionalize tcg_out_extu_i32_i64
tcg/i386: Always enable TCG_TARGET_HAS_extr[lh]_i64_i32
tcg/tci: Elimnate TARGET_LONG_BITS, target_ulong
tcg: Split INDEX_op_qemu_{ld,st}* for guest address size
tcg: Remove TCGv from tcg_gen_atomic_*
tcg: Remove TCGv from tcg_gen_qemu_{ld,st}_*
tcg: Add addr_type to TCGContext
accel/tcg: Widen plugin_gen_empty_mem_callback to i64
tcg: Reduce copies for plugin_gen_mem_callbacks
...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

tcg: Introduce tcg_target_has_memory_bswap

Replace the unparameterized TCG_TARGET_HAS_MEMORY_BSWAP macro
with a function with a memop argument.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

tcg: Introduce tcg_target_has_memory_bswap

Replace the unparameterized TCG_TARGET_HAS_MEMORY_BSWAP macro
with a function with a memop argument.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

Merge tag 'pull-tcg-20230505' of https://gitlab.com/rth7680/qemu into staging

softfloat: Fix the incorrect computation in float32_exp2
tcg: Remove compatability helpers for qemu ld/st
target/alpha:

Merge tag 'pull-tcg-20230505' of https://gitlab.com/rth7680/qemu into staging

softfloat: Fix the incorrect computation in float32_exp2
tcg: Remove compatability helpers for qemu ld/st
target/alpha: Remove TARGET_ALIGNED_ONLY
target/hppa: Remove TARGET_ALIGNED_ONLY
target/sparc: Remove TARGET_ALIGNED_ONLY
tcg: Cleanups preparing to unify calls to qemu_ld/st helpers

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# gpg: Signature made Fri 05 May 2023 10:23:33 PM BST
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [ultimate]

* tag 'pull-tcg-20230505' of https://gitlab.com/rth7680/qemu: (42 commits)
tcg: Widen helper_*_st[bw]_mmu val arguments
tcg: Introduce arg_slot_stk_ofs
tcg: Replace REG_P with arg_loc_reg_p
tcg: Move TCGLabelQemuLdst to tcg.c
tcg/sparc64: Pass TCGType to tcg_out_qemu_{ld,st}
tcg/sparc64: Drop is_64 test from tcg_out_qemu_ld data return
tcg/s390x: Introduce HostAddress
tcg/s390x: Pass TCGType to tcg_out_qemu_{ld,st}
tcg/riscv: Rationalize args to tcg_out_qemu_{ld,st}
tcg/riscv: Require TCG_TARGET_REG_BITS == 64
tcg/ppc: Introduce HostAddress
tcg/ppc: Rationalize args to tcg_out_qemu_{ld,st}
tcg/mips: Rationalize args to tcg_out_qemu_{ld,st}
tcg/loongarch64: Introduce HostAddress
tcg/loongarch64: Rationalize args to tcg_out_qemu_{ld,st}
tcg/arm: Introduce HostAddress
tcg/arm: Rationalize args to tcg_out_qemu_{ld,st}
tcg/aarch64: Introduce HostAddress
tcg/aarch64: Rationalize args to tcg_out_qemu_{ld,st}
tcg/i386: Introduce tcg_out_testi
...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

tcg: Replace REG_P with arg_loc_reg_p

An inline function is safer than a macro, and REG_P
was rather too generic.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Hend

tcg: Replace REG_P with arg_loc_reg_p

An inline function is safer than a macro, and REG_P
was rather too generic.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

Merge tag 'pull-tcg-20230204' of https://gitlab.com/rth7680/qemu into staging

tcg: Add support for TCGv_i128 in parameters and returns.
tcg: Add support for TCGv_i128 in cmpxchg.
tcg: Test CPUJumpCa

Merge tag 'pull-tcg-20230204' of https://gitlab.com/rth7680/qemu into staging

tcg: Add support for TCGv_i128 in parameters and returns.
tcg: Add support for TCGv_i128 in cmpxchg.
tcg: Test CPUJumpCache in tb_jmp_cache_clear_page
tcg: Split out tcg_gen_nonatomic_cmpxchg_i{32,64}
tcg/aarch64: Fix patching of LDR in tb_target_set_jmp_target
target/arm: Use tcg_gen_atomic_cmpxchg_i128
target/i386: Use tcg_gen_atomic_cmpxchg_i128
target/i386: Use tcg_gen_nonatomic_cmpxchg_i{32,64}
target/s390x: Use tcg_gen_atomic_cmpxchg_i128
target/s390x: Use TCGv_i128 in passing and returning float128
target/s390x: Implement CC_OP_NZ in gen_op_calc_cc

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# gpg: Signature made Sat 04 Feb 2023 16:30:46 GMT
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F

* tag 'pull-tcg-20230204' of https://gitlab.com/rth7680/qemu: (40 commits)
tcg/aarch64: Fix patching of LDR in tb_target_set_jmp_target
target/i386: Inline cmpxchg16b
target/i386: Inline cmpxchg8b
target/i386: Split out gen_cmpxchg8b, gen_cmpxchg16b
target/s390x: Implement CC_OP_NZ in gen_op_calc_cc
target/s390x: Use tcg_gen_atomic_cmpxchg_i128 for CDSG
target/s390x: Use Int128 for passing float128
target/s390x: Use Int128 for returning float128
target/s390x: Copy wout_x1 to wout_x1_P
target/s390x: Use Int128 for return from TRE
target/s390x: Use Int128 for return from CKSM
target/s390x: Use Int128 for return from CLST
target/s390x: Use a single return for helper_divs64/u64
target/s390x: Use a single return for helper_divs32/u32
tests/tcg/s390x: Add cdsg.c
tests/tcg/s390x: Add long-double.c
tests/tcg/s390x: Add clst.c
tests/tcg/s390x: Add div.c
target/ppc: Use tcg_gen_atomic_cmpxchg_i128 for STQCX
target/arm: Use tcg_gen_atomic_cmpxchg_i128 for CASP
...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...