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74abb45d |
| 31-May-2024 |
Richard Henderson <richard.henderson@linaro.org> |
Merge tag 'pull-target-arm-20240531' of https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm: * hw/intc/arm_gic: Fix set pending of PPIs * hw/intc/arm_gic: Fix writes to GICD_IT
Merge tag 'pull-target-arm-20240531' of https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm: * hw/intc/arm_gic: Fix set pending of PPIs * hw/intc/arm_gic: Fix writes to GICD_ITARGETSRn * xilinx_zynq: Add cache controller * xilinx_zynq: Support up to two CPU cores * tests/avocado: update sbsa-ref firmware * sbsa-ref: move to Neoverse-N2 as default * More decodetree conversion of A64 ASIMD insns * docs/system/target-arm: Re-alphabetize board list * Implement FEAT WFxT and enable for '-cpu max' * hw/usb/hcd-ohci: Fix #1510, #303: pid not IN or OUT
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* tag 'pull-target-arm-20240531' of https://git.linaro.org/people/pmaydell/qemu-arm: (43 commits) hw/usb/hcd-ohci: Fix #1510, #303: pid not IN or OUT target/arm: Implement FEAT WFxT and enable for '-cpu max' accel/tcg: Make TCGCPUOps::cpu_exec_halt return bool for whether to halt docs/system/target-arm: Re-alphabetize board list target/arm: Disable SVE extensions when SVE is disabled target/arm: Convert FCSEL to decodetree target/arm: Convert FMADD, FMSUB, FNMADD, FNMSUB to decodetree target/arm: Convert SQDMULH, SQRDMULH to decodetree target/arm: Tidy SQDMULH, SQRDMULH (vector) target/arm: Convert MLA, MLS to decodetree target/arm: Convert MUL, PMUL to decodetree target/arm: Convert SABA, SABD, UABA, UABD to decodetree target/arm: Convert SMAX, SMIN, UMAX, UMIN to decodetree target/arm: Convert SRHADD, URHADD to decodetree target/arm: Convert SRHADD, URHADD to gvec target/arm: Convert SHSUB, UHSUB to decodetree target/arm: Convert SHSUB, UHSUB to gvec target/arm: Convert SHADD, UHADD to decodetree target/arm: Convert SHADD, UHADD to gvec target/arm: Use TCG_COND_TSTNE in gen_cmtst_vec ...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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#
1217edac |
| 28-May-2024 |
Richard Henderson <richard.henderson@linaro.org> |
target/arm: Inline scalar SUQADD and USQADD
This eliminates the last uses of these neon helpers. Incorporate the MO_64 expanders as an option to the vector expander.
Reviewed-by: Peter Maydell <pet
target/arm: Inline scalar SUQADD and USQADD
This eliminates the last uses of these neon helpers. Incorporate the MO_64 expanders as an option to the vector expander.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240528203044.612851-6-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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8f6343ae |
| 28-May-2024 |
Richard Henderson <richard.henderson@linaro.org> |
target/arm: Convert SUQADD and USQADD to gvec
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240528203044.612851-5-richard.henderson@linaro.org Signed-off-by: Peter Ma
target/arm: Convert SUQADD and USQADD to gvec
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240528203044.612851-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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f8e5c833 |
| 28-May-2024 |
Richard Henderson <richard.henderson@linaro.org> |
Merge tag 'pull-target-arm-20240528' of https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue: * xlnx_dpdma: fix descriptor endianness bug * hvf: arm: Fix encodings for ID_
Merge tag 'pull-target-arm-20240528' of https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue: * xlnx_dpdma: fix descriptor endianness bug * hvf: arm: Fix encodings for ID_AA64PFR1_EL1 and debug System registers * hw/arm/npcm7xx: remove setting of mp-affinity * hw/char: Correct STM32L4x5 usart register CR2 field ADD_0 size * hw/intc/arm_gic: Fix handling of NS view of GICC_APR<n> * hw/input/tsc2005: Fix -Wchar-subscripts warning in tsc2005_txrx() * hw: arm: Remove use of tabs in some source files * docs/system: Remove ADC from raspi documentation * target/arm: Start of the conversion of A64 SIMD to decodetree
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* tag 'pull-target-arm-20240528' of https://git.linaro.org/people/pmaydell/qemu-arm: (42 commits) target/arm: Convert disas_simd_3same_logic to decodetree target/arm: Convert FMLAL, FMLSL to decodetree target/arm: Use gvec for neon pmax, pmin target/arm: Convert SMAXP, SMINP, UMAXP, UMINP to decodetree target/arm: Use gvec for neon padd target/arm: Convert ADDP to decodetree target/arm: Use gvec for neon faddp, fmaxp, fminp target/arm: Convert FMAXP, FMINP, FMAXNMP, FMINNMP to decodetree target/arm: Convert FADDP to decodetree target/arm: Convert FRECPS, FRSQRTS to decodetree target/arm: Convert FABD to decodetree target/arm: Convert FCMEQ, FCMGE, FCMGT, FACGE, FACGT to decodetree target/arm: Convert FMLA, FMLS to decodetree target/arm: Convert FNMUL to decodetree target/arm: Expand vfp neg and abs inline target/arm: Introduce vfp_load_reg16 target/arm: Convert FMAX, FMIN, FMAXNM, FMINNM to decodetree target/arm: Convert FADD, FSUB, FDIV, FMUL to decodetree target/arm: Convert FMULX to decodetree target/arm: Convert Advanced SIMD copy to decodetree ...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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a11efe30 |
| 24-May-2024 |
Richard Henderson <richard.henderson@linaro.org> |
target/arm: Split out gengvec64.c
Split some routines out of translate-a64.c and translate-sve.c that are used by both.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe M
target/arm: Split out gengvec64.c
Split some routines out of translate-a64.c and translate-sve.c that are used by both.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240524232121.284515-9-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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