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d495e432 |
| 30-Jun-2022 |
Richard Henderson <richard.henderson@linaro.org> |
Merge tag 'pull-aspeed-20220630' of https://github.com/legoater/qemu into staging
aspeed queue:
* m25p80 improvements (Iris) * Code cleanup in preparation of multi SoC machine (Peter) * New MAX3178
Merge tag 'pull-aspeed-20220630' of https://github.com/legoater/qemu into staging
aspeed queue:
* m25p80 improvements (Iris) * Code cleanup in preparation of multi SoC machine (Peter) * New MAX31785 model (Mahesh) * New Qualcomm machines (Jae and Graeme) * Core I2C slave mode (Klaus) * Aspeed I2C slave mode for old and new register interface (Peter and Klaus) * New Aspeed PECI model (Peter) * Various small fixes
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* tag 'pull-aspeed-20220630' of https://github.com/legoater/qemu: (27 commits) hw/misc/aspeed: Add PECI controller hw/i2c/aspeed: Add new-registers DMA slave mode RX support hw/i2c/aspeed: add slave device in old register mode hw/i2c: add asynchronous send hw/i2c: support multiple masters hw/i2c/aspeed: Fix MASTER_EN missing error message hw/i2c/aspeed: Fix DMA len write-enable bit handling hw/i2c/aspeed: Fix R_I2CD_FUN_CTRL reference hw/arm/aspeed: firework: add I2C MUXes for VR channels hw/arm/aspeed: firework: Add Thermal Diodes hw/arm/aspeed: Add MAX31785 Fan controllers hw/sensor: add Maxim MAX31785 device hw/i2c: pmbus: Page #255 is valid page for read requests. hw/arm/aspeed: add Qualcomm Firework BMC machine hw/arm/aspeed: add support for the Qualcomm DC-SCM v1 board aspeed: Remove use of qemu_get_cpu aspeed: Map unimplemented devices in SoC memory aspeed: Remove usage of sysbus_mmio_map aspeed: Add memory property to Aspeed SoC aspeed: Set CPU memory property explicitly ...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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55c57023 |
| 30-Jun-2022 |
Peter Delevoryas <pdel@fb.com> |
hw/misc/aspeed: Add PECI controller
This introduces a really basic PECI controller that responses to commands by always setting the response code to success and then raising an interrupt to indicate
hw/misc/aspeed: Add PECI controller
This introduces a really basic PECI controller that responses to commands by always setting the response code to success and then raising an interrupt to indicate the command is done. This helps avoid getting hit with constant errors if the driver continuously attempts to send a command and keeps timing out.
The AST2400 and AST2500 only included registers up to 0x5C, not 0xFC. They supported PECI 1.1, 2.0, and 3.0. The AST2600 and AST1030 support PECI 4.0, which includes more read/write buffer registers from 0x80 to 0xFC to support 64-byte mode.
This patch doesn't attempt to handle that, or to create a different version of the controller for the different generations, since it's only implementing functionality that is common to all generations.
The basic sequence of events is that the firmware will read and write to various registers and then trigger a command by setting the FIRE bit in the command register (similar to the I2C controller).
Then the firmware waits for an interrupt from the PECI controller, expecting the interrupt status register to be filled in with info on what happened. If the command was transmitted and received successfully, then response codes from the host CPU will be found in the data buffer registers.
Signed-off-by: Peter Delevoryas <pdel@fb.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220630045133.32251-12-me@pjd.dev> [ clg: s/sysbus_mmio_map/aspeed_mmio_map/ ] Signed-off-by: Cédric Le Goater <clg@kaod.org>
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