#
553f648d |
| 08-May-2025 |
Heiko Stuebner <heiko@sntech.de> |
clk: rockchip: rename gate-grf clk file
All Rockchip clock types live in files starting with clk-foo, so rename the newly added gate-grf-clock to follow that scheme.
Signed-off-by: Heiko Stuebner <
clk: rockchip: rename gate-grf clk file
All Rockchip clock types live in files starting with clk-foo, so rename the newly added gate-grf-clock to follow that scheme.
Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20250508182752.1925313-3-heiko@sntech.de
show more ...
|
#
e277168c |
| 02-May-2025 |
Nicolas Frattaroli <nicolas.frattaroli@collabora.com> |
clk: rockchip: introduce GRF gates
Some rockchip SoCs, namely the RK3576, have bits in a General Register File (GRF) that act just like clock gates. The downstream vendor kernel simply maps over the
clk: rockchip: introduce GRF gates
Some rockchip SoCs, namely the RK3576, have bits in a General Register File (GRF) that act just like clock gates. The downstream vendor kernel simply maps over the already mapped GRF range with a generic clock gate driver. This solution isn't suitable for upstream, as a memory range will be in use by multiple drivers at the same time, and it leaks implementation details into the device tree.
Instead, implement this with a new clock branch type in the Rockchip clock driver: GRF gates. Somewhat akin to MUXGRF, this clock branch depends on the type of GRF, but functions like a gate instead.
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com> Link: https://lore.kernel.org/r/20250502-rk3576-sai-v3-3-376cef19dd7c@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
show more ...
|