x86: nVMX: Introduce skip_exit_insn()

Signed-off-by: Liran Alon <liran.alon@oracle.com>
Signed-off-by: Jim Mattson <jmattson@google.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

nVMX x86: "virtualize APIC accesses" must be unset if "virtualize x2APIC" is set

According to section "Checks on VMX Controls" in Intel SDM vol 3C,
the following check needs to be enforced on vmentr

nVMX x86: "virtualize APIC accesses" must be unset if "virtualize x2APIC" is set

According to section "Checks on VMX Controls" in Intel SDM vol 3C,
the following check needs to be enforced on vmentry of L2 guests:

If the "virtualize x2APIC mode" VM-execution control is 1, the
"virtualize APIC accesses" VM-execution control must be 0.

This unit-test validates the above vmentry check.

Signed-off-by: Krish Sadhukhan <krish.sadhukhan@oracle.com>
Reviewed-by: Jim Mattson <jmattson@google.com>
Reviewed-by: Karl Heubaum <karl.heubaum@oracle.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

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nVMX x86: APIC virtual controls must be unset if "Use TPR shadow" is unset

According to section "Checks on VMX Controls" in Intel SDM vol 3C, the
following check needs to be enforced on vmentry of L

nVMX x86: APIC virtual controls must be unset if "Use TPR shadow" is unset

According to section "Checks on VMX Controls" in Intel SDM vol 3C, the
following check needs to be enforced on vmentry of L2 guests:

If the "use TPR shadow" VM-execution control is 0, the following
VM-execution controls must also be 0: "virtualize x2APIC mode",
"APIC-register virtualization" and "virtual-interrupt delivery".

This unit-test validates the above vmentry check.

Signed-off-by: Krish Sadhukhan <krish.sadhukhan@oracle.com>
Reviewed-by: Karl Heubaum <karl.heubaum@oracle.com>
Reviewed-by: Jim Mattson <jmattson@google.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

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x86: Add test for nested VM entry prereqs

This patch adds a test for the prereq checks done as a part of a nested
VM launch related to event injection.

Signed-off-by: Marc Orr <marcorr@google.com>

x86: Add test for nested VM entry prereqs

This patch adds a test for the prereq checks done as a part of a nested
VM launch related to event injection.

Signed-off-by: Marc Orr <marcorr@google.com>
Message-Id: <20180626014818.26541-1-marcorr@google.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

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vmx: fix CR8 load intercept test

If the RAX register has invalid bits set, a mov to CR8 instruction can
raise a #GP. This has not been happening so far only because the compiler
gods were good frie

vmx: fix CR8 load intercept test

If the RAX register has invalid bits set, a mov to CR8 instruction can
raise a #GP. This has not been happening so far only because the compiler
gods were good friends with the original author of the tests; but they
did not like Thomas as well, and the test started failing with commit
19230e96697efa1e65a8945b6911a6eb4506d4e9 (Make vmx_tests.c compilable with
-Wmissing-prototypes and -Wstrict-prototypes).

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

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Make vmx_tests.c compilable with -Wmissing-prototypes and -Wstrict-prototypes

... to make sure that we're calling the functions with the right
parameters everywhere...

Signed-off-by: Thomas Huth <t

Make vmx_tests.c compilable with -Wmissing-prototypes and -Wstrict-prototypes

... to make sure that we're calling the functions with the right
parameters everywhere...

Signed-off-by: Thomas Huth <thuth@redhat.com>
Message-Id: <1530086528-21665-2-git-send-email-thuth@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

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vmx: run EPT tests last

There is some state corruption happening during the EPT test that is causing
failures in vmx_eoi_bitmap_ioapic_scan_test. Move the tests last while the
root cause is investi

vmx: run EPT tests last

There is some state corruption happening during the EPT test that is causing
failures in vmx_eoi_bitmap_ioapic_scan_test. Move the tests last while the
root cause is investigated.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

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vmx_tests: remove #UD exception handler at the end of the test

Be tidy and avoid interactions between tests.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

nvmx: Check exit qualification RD/WR permission for MMIO accesses

Validate that a write MMIO access that follows a read MMIO access would
have the correct access captured in the exit qualification.

nvmx: Check exit qualification RD/WR permission for MMIO accesses

Validate that a write MMIO access that follows a read MMIO access would
have the correct access captured in the exit qualification.

Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Radim Krčmář <rkrcmar@redhat.com>
Cc: kvm@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: KarimAllah Ahmed <karahmed@amazon.de>
Message-Id: <1519841208-23349-1-git-send-email-karahmed@amazon.de>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

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x86: Add test for checking APIC-access page on vmentry of L2 guests

According to the sub-section titled 'VM-Execution Control Fields' in the
section titled 'Basic VM-Entry Checks' in Intel SDM vol.

x86: Add test for checking APIC-access page on vmentry of L2 guests

According to the sub-section titled 'VM-Execution Control Fields' in the
section titled 'Basic VM-Entry Checks' in Intel SDM vol. 3C, the following
vmentry check must be enforced:

If the 'virtualize APIC-accesses' VM-execution control is 1, the
APIC-access address must satisfy the following checks:

- Bits 11:0 of the address must be 0.
- The address should not set any bits beyond the processor's
physical-address width.

This patch adds a unit-test to validate the vmentry check.

Signed-off-by: Krish Sadhukhan <krish.sadhukhan@oracle.com>
Reviewed-by: Mihai Carabas <mihai.carabas@oracle.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

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x86: nVMX: Verify pass-through IOAPIC & LAPIC to guest after ioapic scan

Verify that L1 pass-through of IOAPIC & LAPIC to L2 works
even if another CPU triggers an ioapic scan while first CPU
runs gu

x86: nVMX: Verify pass-through IOAPIC & LAPIC to guest after ioapic scan

Verify that L1 pass-through of IOAPIC & LAPIC to L2 works
even if another CPU triggers an ioapic scan while first CPU
runs guest.

This basically makes sure that vcpu->arch.ioapic_handled_vectors is
updated correctly even for vCPUs that is currently running guest.

For more details, refer to message of KVM commit
("KVM: nVMX: Do not load EOI-exitmap while running L2")

Signed-off-by: Liran Alon <liran.alon@oracle.com>
Reviewed-by: Krish Sadhukhan <krish.sadhukhan@oracle.com>
Message-Id: <1521674594-12085-8-git-send-email-liran.alon@oracle.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

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x86: nVMX: Verify pass-through LAPIC & IO-APIC to guest

Test configures VMCS to run guest with LAPIC & IO-APIC pass-through:
* MSR-bitmap is empty (no intercept on access to x2APIC MSRs).
* No exit

x86: nVMX: Verify pass-through LAPIC & IO-APIC to guest

Test configures VMCS to run guest with LAPIC & IO-APIC pass-through:
* MSR-bitmap is empty (no intercept on access to x2APIC MSRs).
* No exit on external-interrupts
* No tpr-shadow, virtualize-apic-access and virtualize-x2apic-mode.

To verify pass-through works correctly, guest asserts irq-line to trigger
a level-triggered interrupt that should be injected directly to guest.
In guest interrupt-handler, a vmcall will verify remote_irr=1 before
EOI. Then, guest issues EOI and another vmcall to verify remote_irr
was cleared.

Signed-off-by: Elazar Leibovich <elazar.leibovich@oracle.com>
Co-authored-by: Liran Alon <liran.alon@oracle.com>
Signed-off-by: Liran Alon <liran.alon@oracle.com>
Reviewed-by: Krish Sadhukhan <krish.sadhukhan@oracle.com>
Message-Id: <1521674594-12085-7-git-send-email-liran.alon@oracle.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

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x86: nVMX: Verify vmcs12 EOI-exit-bitmap not corrupted on L1 IOAPIC scan

This test aims to verify that L1 IOAPIC scan requests don't corrupt
vmcs02->eoi_exit_bitmap which should always be equal to
v

x86: nVMX: Verify vmcs12 EOI-exit-bitmap not corrupted on L1 IOAPIC scan

This test aims to verify that L1 IOAPIC scan requests don't corrupt
vmcs02->eoi_exit_bitmap which should always be equal to
vmcs12->eoi_exit_bitmap.

Test configures CPU0 to run L2 with virtual-interrupt-delivery and
empty EOI-exit-bitmap. Therefore, expecting no vmexit on EOI_INDUCED
when L2 performs EOI. Before L2 performs EOI, test makes CPU1 modify
IOAPIC redirection table which will trigger an IOAPIC scan on all
vCPUs. Then, L2 performs EOI followed by a VMCALL. Test fails if
L1 got a vmexit other than VMCALL.

The issue tested in this patch was fixed in KVM commit
("KVM: nVMX: Do not load EOI-exitmap while running L2").
For more details, refer to that commit message.

Signed-off-by: Arbel Moshe <arbel.moshe@oracle.com>
Suggested-by: Liran Alon <liran.alon@oracle.com>
Signed-off-by: Liran Alon <liran.alon@oracle.com>
Reviewed-by: Krish Sadhukhan <krish.sadhukhan@oracle.com>
Message-Id: <1521674594-12085-6-git-send-email-liran.alon@oracle.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

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x86: Add test for checking NMI controls on vmentry of L2 guests

This test validates the following vmentry checks from Intel SDM 26.2.1.1:

1. If the “NMI exiting” VM-execution control is 0,
the

x86: Add test for checking NMI controls on vmentry of L2 guests

This test validates the following vmentry checks from Intel SDM 26.2.1.1:

1. If the “NMI exiting” VM-execution control is 0,
the “virtual NMIs” VM-execution control must be 0.

2. If the “virtual NMIs” VM-execution control is 0,
the “NMI-window exiting” VM-execution control must be 0.

Signed-off-by: Krish Sadhukhan <krish.sadhukhan@oracle.com>
Reviewed-by: Liran Alon <liran.alon@oracle.com>
Signed-off-by: Radim Krčmář <rkrcmar@redhat.com>

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kvm-unit-tests: vmx: add a test for injecting events to halted L2

This patch leverages existing "interrupt" tests. What the patch does is L1
puts L2 in halt state and injects an event to L2. Then ch

kvm-unit-tests: vmx: add a test for injecting events to halted L2

This patch leverages existing "interrupt" tests. What the patch does is L1
puts L2 in halt state and injects an event to L2. Then check a flag to
identify whether event injection succeeds or not.

Reviewed-by: Liran Alon <liran.alon@oracle.com>
Signed-off-by: Chao Gao <chao.gao@intel.com>
Message-Id: <1518314807-31821-1-git-send-email-chao.gao@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

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x86: Add test for TPR threshold and vTPR check on VM-entry

This test checks that a nested VM-entry fails if the "use TPR shadow"
VM-execution control is set, the "virtual-interrupt delivery"
VM-exec

x86: Add test for TPR threshold and vTPR check on VM-entry

This test checks that a nested VM-entry fails if the "use TPR shadow"
VM-execution control is set, the "virtual-interrupt delivery"
VM-execution control is clear, "virtualize APIC accesses" is clear and
bits 3:0 of TPR threshold is greater than bits 7:4 of vTPR.

Signed-off-by: Krish Sadhukhan <krish.sadhukhan@oracle.com>
Reviewed-by: Jim Mattson <jmattson@google.com>
Message-Id: <20171130003755.25658-2-krish.sadhukhan@oracle.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

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vmx: fixes for MAXPHYADDR requirement

The EPT access tests require at least 41 bits of guest physical address
space. This is because the test data needs a separate PML4 entry in the
EPT table. How

vmx: fixes for MAXPHYADDR requirement

The EPT access tests require at least 41 bits of guest physical address
space. This is because the test data needs a separate PML4 entry in the
EPT table. However, many consumer-grade processors have only 36 or
39-bit MAXPHYADDR, and the tests fail there with a page fault due to
reserved bits set in the guest (GVA->GPA) page tables.

Add a test on MAXPHYADDR and skip the tests if they cannot run on the
system under test, and only require 40 bits to lower the requirements.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Radim Krčmář <rkrcmar@redhat.com>

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lib: move page allocator here from x86

This is another step in porting the x86 (v)malloc implementation to
other architectures.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

lib: start moving vmalloc to generic code

For now, vmalloc provides a primitive that allocates contiguous virtual
address. Together with a page allocator that allocates single
physical memory pages

lib: start moving vmalloc to generic code

For now, vmalloc provides a primitive that allocates contiguous virtual
address. Together with a page allocator that allocates single
physical memory pages, it will provide an implementation of
alloc_ops for when an MMU is enabled.

Before doing that, however, we need to move the page allocator and
give lib/alloc.c's malloc feature parity with lib/x86/vm.c's vmalloc.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

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x86: vmx: add test for L1 CR4 load

Test whether KVM loads the correct L1 CR4 as guest CR4 when emulating
L2 to L1 exit.

Signed-off-by: Haozhong Zhang <haozhong.zhang@intel.com>
Signed-off-by: Paolo

x86: vmx: add test for L1 CR4 load

Test whether KVM loads the correct L1 CR4 as guest CR4 when emulating
L2 to L1 exit.

Signed-off-by: Haozhong Zhang <haozhong.zhang@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

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x86: xfail some VMX control field tests

When the APIC virtualization address references unbacked memory, kvm
incorrectly fails a VM-entry with "invalid control field(s)." Until
this can be fixed, ju

x86: xfail some VMX control field tests

When the APIC virtualization address references unbacked memory, kvm
incorrectly fails a VM-entry with "invalid control field(s)." Until
this can be fixed, just skip the VMX control field tests that populate
a VMCS field with a physical address that isn't backed.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

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x86: Add test for TPR threshold check on VM-entry

This test checks that a nested VM-entry fails if the "use TPR shadow"
VM-execution control is set, the "virtual-interrupt delivery"
VM-execution con

x86: Add test for TPR threshold check on VM-entry

This test checks that a nested VM-entry fails if the "use TPR shadow"
VM-execution control is set, the "virtual-interrupt delivery"
VM-execution control is clear, and the TPR threshold is greater than
0xf.

Signed-off-by: Jim Mattson <jmattson@google.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

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Test of virtual-APIC address

This test checks that a nested VM-entry fails if the "use TPR shadow"
VM-execution control is set and the virtual-APIC address is illegal. A
legal virtual-apic address i

Test of virtual-APIC address

This test checks that a nested VM-entry fails if the "use TPR shadow"
VM-execution control is set and the virtual-APIC address is illegal. A
legal virtual-apic address is 4k-aligned and within the physical
address space supported by the processor.

Signed-off-by: Jim Mattson <jmattson@google.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

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Test CR3 target count validation

If the CR3 target count is too high, VM-entry should fail.

Signed-off-by: Jim Mattson <jmattson@google.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

Test of VMCS processor-based controls

This test checks that a nested VM-entry fails if reserved bits in the
primary processor-based VM-execution controls are not set properly
(according to either th

Test of VMCS processor-based controls

This test checks that a nested VM-entry fails if reserved bits in the
primary processor-based VM-execution controls are not set properly
(according to either the IA32_VMX_PROCBASED_CTLS MSR or the
IA32_VMX_TRUE_PROCBASED_CTLS MSR, as appropriate). It also checks that
a nested VM-entry fails if the "activate secondary controls"
VM-execution control is set and a reserved bit is set in the secondary
processor-based VM-execution controls (according to the
IA32_VMX_PROCBASED_CTLS2 MSR).

Signed-off-by: Jim Mattson <jmattson@google.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

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