1 /* 2 * All test cases of nested virtualization should be in this file 3 * 4 * Author : Arthur Chunqi Li <yzt356@gmail.com> 5 */ 6 #include "vmx.h" 7 #include "msr.h" 8 #include "processor.h" 9 #include "vm.h" 10 #include "pci.h" 11 #include "fwcfg.h" 12 #include "isr.h" 13 #include "desc.h" 14 #include "apic.h" 15 #include "types.h" 16 #include "vmalloc.h" 17 #include "alloc_page.h" 18 #include "smp.h" 19 #include "delay.h" 20 21 #define NONCANONICAL 0xaaaaaaaaaaaaaaaaull 22 23 #define VPID_CAP_INVVPID_TYPES_SHIFT 40 24 25 u64 ia32_pat; 26 u64 ia32_efer; 27 void *io_bitmap_a, *io_bitmap_b; 28 u16 ioport; 29 30 unsigned long *pml4; 31 u64 eptp; 32 void *data_page1, *data_page2; 33 34 phys_addr_t pci_physaddr; 35 36 void *pml_log; 37 #define PML_INDEX 512 38 39 static inline unsigned ffs(unsigned x) 40 { 41 int pos = -1; 42 43 __asm__ __volatile__("bsf %1, %%eax; cmovnz %%eax, %0" 44 : "+r"(pos) : "rm"(x) : "eax"); 45 return pos + 1; 46 } 47 48 static inline void vmcall() 49 { 50 asm volatile("vmcall"); 51 } 52 53 void basic_guest_main() 54 { 55 report("Basic VMX test", 1); 56 } 57 58 int basic_exit_handler() 59 { 60 report("Basic VMX test", 0); 61 print_vmexit_info(); 62 return VMX_TEST_EXIT; 63 } 64 65 void vmenter_main() 66 { 67 u64 rax; 68 u64 rsp, resume_rsp; 69 70 report("test vmlaunch", 1); 71 72 asm volatile( 73 "mov %%rsp, %0\n\t" 74 "mov %3, %%rax\n\t" 75 "vmcall\n\t" 76 "mov %%rax, %1\n\t" 77 "mov %%rsp, %2\n\t" 78 : "=r"(rsp), "=r"(rax), "=r"(resume_rsp) 79 : "g"(0xABCD)); 80 report("test vmresume", (rax == 0xFFFF) && (rsp == resume_rsp)); 81 } 82 83 int vmenter_exit_handler() 84 { 85 u64 guest_rip; 86 ulong reason; 87 88 guest_rip = vmcs_read(GUEST_RIP); 89 reason = vmcs_read(EXI_REASON) & 0xff; 90 switch (reason) { 91 case VMX_VMCALL: 92 if (regs.rax != 0xABCD) { 93 report("test vmresume", 0); 94 return VMX_TEST_VMEXIT; 95 } 96 regs.rax = 0xFFFF; 97 vmcs_write(GUEST_RIP, guest_rip + 3); 98 return VMX_TEST_RESUME; 99 default: 100 report("test vmresume", 0); 101 print_vmexit_info(); 102 } 103 return VMX_TEST_VMEXIT; 104 } 105 106 u32 preempt_scale; 107 volatile unsigned long long tsc_val; 108 volatile u32 preempt_val; 109 u64 saved_rip; 110 111 int preemption_timer_init() 112 { 113 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 114 printf("\tPreemption timer is not supported\n"); 115 return VMX_TEST_EXIT; 116 } 117 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) | PIN_PREEMPT); 118 preempt_val = 10000000; 119 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 120 preempt_scale = rdmsr(MSR_IA32_VMX_MISC) & 0x1F; 121 122 if (!(ctrl_exit_rev.clr & EXI_SAVE_PREEMPT)) 123 printf("\tSave preemption value is not supported\n"); 124 125 return VMX_TEST_START; 126 } 127 128 void preemption_timer_main() 129 { 130 tsc_val = rdtsc(); 131 if (ctrl_exit_rev.clr & EXI_SAVE_PREEMPT) { 132 vmx_set_test_stage(0); 133 vmcall(); 134 if (vmx_get_test_stage() == 1) 135 vmcall(); 136 } 137 vmx_set_test_stage(1); 138 while (vmx_get_test_stage() == 1) { 139 if (((rdtsc() - tsc_val) >> preempt_scale) 140 > 10 * preempt_val) { 141 vmx_set_test_stage(2); 142 vmcall(); 143 } 144 } 145 tsc_val = rdtsc(); 146 asm volatile ("hlt"); 147 vmcall(); 148 vmx_set_test_stage(5); 149 vmcall(); 150 } 151 152 int preemption_timer_exit_handler() 153 { 154 bool guest_halted; 155 u64 guest_rip; 156 ulong reason; 157 u32 insn_len; 158 u32 ctrl_exit; 159 160 guest_rip = vmcs_read(GUEST_RIP); 161 reason = vmcs_read(EXI_REASON) & 0xff; 162 insn_len = vmcs_read(EXI_INST_LEN); 163 switch (reason) { 164 case VMX_PREEMPT: 165 switch (vmx_get_test_stage()) { 166 case 1: 167 case 2: 168 report("busy-wait for preemption timer", 169 ((rdtsc() - tsc_val) >> preempt_scale) >= 170 preempt_val); 171 vmx_set_test_stage(3); 172 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 173 return VMX_TEST_RESUME; 174 case 3: 175 guest_halted = 176 (vmcs_read(GUEST_ACTV_STATE) == ACTV_HLT); 177 report("preemption timer during hlt", 178 ((rdtsc() - tsc_val) >> preempt_scale) >= 179 preempt_val && guest_halted); 180 vmx_set_test_stage(4); 181 vmcs_write(PIN_CONTROLS, 182 vmcs_read(PIN_CONTROLS) & ~PIN_PREEMPT); 183 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 184 return VMX_TEST_RESUME; 185 case 4: 186 report("preemption timer with 0 value", 187 saved_rip == guest_rip); 188 break; 189 default: 190 report("Invalid stage.", false); 191 print_vmexit_info(); 192 break; 193 } 194 break; 195 case VMX_VMCALL: 196 vmcs_write(GUEST_RIP, guest_rip + insn_len); 197 switch (vmx_get_test_stage()) { 198 case 0: 199 report("Keep preemption value", 200 vmcs_read(PREEMPT_TIMER_VALUE) == preempt_val); 201 vmx_set_test_stage(1); 202 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 203 ctrl_exit = (vmcs_read(EXI_CONTROLS) | 204 EXI_SAVE_PREEMPT) & ctrl_exit_rev.clr; 205 vmcs_write(EXI_CONTROLS, ctrl_exit); 206 return VMX_TEST_RESUME; 207 case 1: 208 report("Save preemption value", 209 vmcs_read(PREEMPT_TIMER_VALUE) < preempt_val); 210 return VMX_TEST_RESUME; 211 case 2: 212 report("busy-wait for preemption timer", 0); 213 vmx_set_test_stage(3); 214 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 215 return VMX_TEST_RESUME; 216 case 3: 217 report("preemption timer during hlt", 0); 218 vmx_set_test_stage(4); 219 /* fall through */ 220 case 4: 221 vmcs_write(PIN_CONTROLS, 222 vmcs_read(PIN_CONTROLS) | PIN_PREEMPT); 223 vmcs_write(PREEMPT_TIMER_VALUE, 0); 224 saved_rip = guest_rip + insn_len; 225 return VMX_TEST_RESUME; 226 case 5: 227 report("preemption timer with 0 value (vmcall stage 5)", 0); 228 break; 229 default: 230 // Should not reach here 231 report("unexpected stage, %d", false, 232 vmx_get_test_stage()); 233 print_vmexit_info(); 234 return VMX_TEST_VMEXIT; 235 } 236 break; 237 default: 238 report("Unknown exit reason, %ld", false, reason); 239 print_vmexit_info(); 240 } 241 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_PREEMPT); 242 return VMX_TEST_VMEXIT; 243 } 244 245 void msr_bmp_init() 246 { 247 void *msr_bitmap; 248 u32 ctrl_cpu0; 249 250 msr_bitmap = alloc_page(); 251 memset(msr_bitmap, 0x0, PAGE_SIZE); 252 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 253 ctrl_cpu0 |= CPU_MSR_BITMAP; 254 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 255 vmcs_write(MSR_BITMAP, (u64)msr_bitmap); 256 } 257 258 static int test_ctrl_pat_init() 259 { 260 u64 ctrl_ent; 261 u64 ctrl_exi; 262 263 msr_bmp_init(); 264 if (!(ctrl_exit_rev.clr & EXI_SAVE_PAT) && 265 !(ctrl_exit_rev.clr & EXI_LOAD_PAT) && 266 !(ctrl_enter_rev.clr & ENT_LOAD_PAT)) { 267 printf("\tSave/load PAT is not supported\n"); 268 return 1; 269 } 270 271 ctrl_ent = vmcs_read(ENT_CONTROLS); 272 ctrl_exi = vmcs_read(EXI_CONTROLS); 273 ctrl_ent |= ctrl_enter_rev.clr & ENT_LOAD_PAT; 274 ctrl_exi |= ctrl_exit_rev.clr & (EXI_SAVE_PAT | EXI_LOAD_PAT); 275 vmcs_write(ENT_CONTROLS, ctrl_ent); 276 vmcs_write(EXI_CONTROLS, ctrl_exi); 277 ia32_pat = rdmsr(MSR_IA32_CR_PAT); 278 vmcs_write(GUEST_PAT, 0x0); 279 vmcs_write(HOST_PAT, ia32_pat); 280 return VMX_TEST_START; 281 } 282 283 static void test_ctrl_pat_main() 284 { 285 u64 guest_ia32_pat; 286 287 guest_ia32_pat = rdmsr(MSR_IA32_CR_PAT); 288 if (!(ctrl_enter_rev.clr & ENT_LOAD_PAT)) 289 printf("\tENT_LOAD_PAT is not supported.\n"); 290 else { 291 if (guest_ia32_pat != 0) { 292 report("Entry load PAT", 0); 293 return; 294 } 295 } 296 wrmsr(MSR_IA32_CR_PAT, 0x6); 297 vmcall(); 298 guest_ia32_pat = rdmsr(MSR_IA32_CR_PAT); 299 if (ctrl_enter_rev.clr & ENT_LOAD_PAT) 300 report("Entry load PAT", guest_ia32_pat == ia32_pat); 301 } 302 303 static int test_ctrl_pat_exit_handler() 304 { 305 u64 guest_rip; 306 ulong reason; 307 u64 guest_pat; 308 309 guest_rip = vmcs_read(GUEST_RIP); 310 reason = vmcs_read(EXI_REASON) & 0xff; 311 switch (reason) { 312 case VMX_VMCALL: 313 guest_pat = vmcs_read(GUEST_PAT); 314 if (!(ctrl_exit_rev.clr & EXI_SAVE_PAT)) { 315 printf("\tEXI_SAVE_PAT is not supported\n"); 316 vmcs_write(GUEST_PAT, 0x6); 317 } else { 318 report("Exit save PAT", guest_pat == 0x6); 319 } 320 if (!(ctrl_exit_rev.clr & EXI_LOAD_PAT)) 321 printf("\tEXI_LOAD_PAT is not supported\n"); 322 else 323 report("Exit load PAT", rdmsr(MSR_IA32_CR_PAT) == ia32_pat); 324 vmcs_write(GUEST_PAT, ia32_pat); 325 vmcs_write(GUEST_RIP, guest_rip + 3); 326 return VMX_TEST_RESUME; 327 default: 328 printf("ERROR : Undefined exit reason, reason = %ld.\n", reason); 329 break; 330 } 331 return VMX_TEST_VMEXIT; 332 } 333 334 static int test_ctrl_efer_init() 335 { 336 u64 ctrl_ent; 337 u64 ctrl_exi; 338 339 msr_bmp_init(); 340 ctrl_ent = vmcs_read(ENT_CONTROLS) | ENT_LOAD_EFER; 341 ctrl_exi = vmcs_read(EXI_CONTROLS) | EXI_SAVE_EFER | EXI_LOAD_EFER; 342 vmcs_write(ENT_CONTROLS, ctrl_ent & ctrl_enter_rev.clr); 343 vmcs_write(EXI_CONTROLS, ctrl_exi & ctrl_exit_rev.clr); 344 ia32_efer = rdmsr(MSR_EFER); 345 vmcs_write(GUEST_EFER, ia32_efer ^ EFER_NX); 346 vmcs_write(HOST_EFER, ia32_efer ^ EFER_NX); 347 return VMX_TEST_START; 348 } 349 350 static void test_ctrl_efer_main() 351 { 352 u64 guest_ia32_efer; 353 354 guest_ia32_efer = rdmsr(MSR_EFER); 355 if (!(ctrl_enter_rev.clr & ENT_LOAD_EFER)) 356 printf("\tENT_LOAD_EFER is not supported.\n"); 357 else { 358 if (guest_ia32_efer != (ia32_efer ^ EFER_NX)) { 359 report("Entry load EFER", 0); 360 return; 361 } 362 } 363 wrmsr(MSR_EFER, ia32_efer); 364 vmcall(); 365 guest_ia32_efer = rdmsr(MSR_EFER); 366 if (ctrl_enter_rev.clr & ENT_LOAD_EFER) 367 report("Entry load EFER", guest_ia32_efer == ia32_efer); 368 } 369 370 static int test_ctrl_efer_exit_handler() 371 { 372 u64 guest_rip; 373 ulong reason; 374 u64 guest_efer; 375 376 guest_rip = vmcs_read(GUEST_RIP); 377 reason = vmcs_read(EXI_REASON) & 0xff; 378 switch (reason) { 379 case VMX_VMCALL: 380 guest_efer = vmcs_read(GUEST_EFER); 381 if (!(ctrl_exit_rev.clr & EXI_SAVE_EFER)) { 382 printf("\tEXI_SAVE_EFER is not supported\n"); 383 vmcs_write(GUEST_EFER, ia32_efer); 384 } else { 385 report("Exit save EFER", guest_efer == ia32_efer); 386 } 387 if (!(ctrl_exit_rev.clr & EXI_LOAD_EFER)) { 388 printf("\tEXI_LOAD_EFER is not supported\n"); 389 wrmsr(MSR_EFER, ia32_efer ^ EFER_NX); 390 } else { 391 report("Exit load EFER", rdmsr(MSR_EFER) == (ia32_efer ^ EFER_NX)); 392 } 393 vmcs_write(GUEST_PAT, ia32_efer); 394 vmcs_write(GUEST_RIP, guest_rip + 3); 395 return VMX_TEST_RESUME; 396 default: 397 printf("ERROR : Undefined exit reason, reason = %ld.\n", reason); 398 break; 399 } 400 return VMX_TEST_VMEXIT; 401 } 402 403 u32 guest_cr0, guest_cr4; 404 405 static void cr_shadowing_main() 406 { 407 u32 cr0, cr4, tmp; 408 409 // Test read through 410 vmx_set_test_stage(0); 411 guest_cr0 = read_cr0(); 412 if (vmx_get_test_stage() == 1) 413 report("Read through CR0", 0); 414 else 415 vmcall(); 416 vmx_set_test_stage(1); 417 guest_cr4 = read_cr4(); 418 if (vmx_get_test_stage() == 2) 419 report("Read through CR4", 0); 420 else 421 vmcall(); 422 // Test write through 423 guest_cr0 = guest_cr0 ^ (X86_CR0_TS | X86_CR0_MP); 424 guest_cr4 = guest_cr4 ^ (X86_CR4_TSD | X86_CR4_DE); 425 vmx_set_test_stage(2); 426 write_cr0(guest_cr0); 427 if (vmx_get_test_stage() == 3) 428 report("Write throuth CR0", 0); 429 else 430 vmcall(); 431 vmx_set_test_stage(3); 432 write_cr4(guest_cr4); 433 if (vmx_get_test_stage() == 4) 434 report("Write through CR4", 0); 435 else 436 vmcall(); 437 // Test read shadow 438 vmx_set_test_stage(4); 439 vmcall(); 440 cr0 = read_cr0(); 441 if (vmx_get_test_stage() != 5) 442 report("Read shadowing CR0", cr0 == guest_cr0); 443 vmx_set_test_stage(5); 444 cr4 = read_cr4(); 445 if (vmx_get_test_stage() != 6) 446 report("Read shadowing CR4", cr4 == guest_cr4); 447 // Test write shadow (same value with shadow) 448 vmx_set_test_stage(6); 449 write_cr0(guest_cr0); 450 if (vmx_get_test_stage() == 7) 451 report("Write shadowing CR0 (same value with shadow)", 0); 452 else 453 vmcall(); 454 vmx_set_test_stage(7); 455 write_cr4(guest_cr4); 456 if (vmx_get_test_stage() == 8) 457 report("Write shadowing CR4 (same value with shadow)", 0); 458 else 459 vmcall(); 460 // Test write shadow (different value) 461 vmx_set_test_stage(8); 462 tmp = guest_cr0 ^ X86_CR0_TS; 463 asm volatile("mov %0, %%rsi\n\t" 464 "mov %%rsi, %%cr0\n\t" 465 ::"m"(tmp) 466 :"rsi", "memory", "cc"); 467 report("Write shadowing different X86_CR0_TS", vmx_get_test_stage() == 9); 468 vmx_set_test_stage(9); 469 tmp = guest_cr0 ^ X86_CR0_MP; 470 asm volatile("mov %0, %%rsi\n\t" 471 "mov %%rsi, %%cr0\n\t" 472 ::"m"(tmp) 473 :"rsi", "memory", "cc"); 474 report("Write shadowing different X86_CR0_MP", vmx_get_test_stage() == 10); 475 vmx_set_test_stage(10); 476 tmp = guest_cr4 ^ X86_CR4_TSD; 477 asm volatile("mov %0, %%rsi\n\t" 478 "mov %%rsi, %%cr4\n\t" 479 ::"m"(tmp) 480 :"rsi", "memory", "cc"); 481 report("Write shadowing different X86_CR4_TSD", vmx_get_test_stage() == 11); 482 vmx_set_test_stage(11); 483 tmp = guest_cr4 ^ X86_CR4_DE; 484 asm volatile("mov %0, %%rsi\n\t" 485 "mov %%rsi, %%cr4\n\t" 486 ::"m"(tmp) 487 :"rsi", "memory", "cc"); 488 report("Write shadowing different X86_CR4_DE", vmx_get_test_stage() == 12); 489 } 490 491 static int cr_shadowing_exit_handler() 492 { 493 u64 guest_rip; 494 ulong reason; 495 u32 insn_len; 496 u32 exit_qual; 497 498 guest_rip = vmcs_read(GUEST_RIP); 499 reason = vmcs_read(EXI_REASON) & 0xff; 500 insn_len = vmcs_read(EXI_INST_LEN); 501 exit_qual = vmcs_read(EXI_QUALIFICATION); 502 switch (reason) { 503 case VMX_VMCALL: 504 switch (vmx_get_test_stage()) { 505 case 0: 506 report("Read through CR0", guest_cr0 == vmcs_read(GUEST_CR0)); 507 break; 508 case 1: 509 report("Read through CR4", guest_cr4 == vmcs_read(GUEST_CR4)); 510 break; 511 case 2: 512 report("Write through CR0", guest_cr0 == vmcs_read(GUEST_CR0)); 513 break; 514 case 3: 515 report("Write through CR4", guest_cr4 == vmcs_read(GUEST_CR4)); 516 break; 517 case 4: 518 guest_cr0 = vmcs_read(GUEST_CR0) ^ (X86_CR0_TS | X86_CR0_MP); 519 guest_cr4 = vmcs_read(GUEST_CR4) ^ (X86_CR4_TSD | X86_CR4_DE); 520 vmcs_write(CR0_MASK, X86_CR0_TS | X86_CR0_MP); 521 vmcs_write(CR0_READ_SHADOW, guest_cr0 & (X86_CR0_TS | X86_CR0_MP)); 522 vmcs_write(CR4_MASK, X86_CR4_TSD | X86_CR4_DE); 523 vmcs_write(CR4_READ_SHADOW, guest_cr4 & (X86_CR4_TSD | X86_CR4_DE)); 524 break; 525 case 6: 526 report("Write shadowing CR0 (same value)", 527 guest_cr0 == (vmcs_read(GUEST_CR0) ^ (X86_CR0_TS | X86_CR0_MP))); 528 break; 529 case 7: 530 report("Write shadowing CR4 (same value)", 531 guest_cr4 == (vmcs_read(GUEST_CR4) ^ (X86_CR4_TSD | X86_CR4_DE))); 532 break; 533 default: 534 // Should not reach here 535 report("unexpected stage, %d", false, 536 vmx_get_test_stage()); 537 print_vmexit_info(); 538 return VMX_TEST_VMEXIT; 539 } 540 vmcs_write(GUEST_RIP, guest_rip + insn_len); 541 return VMX_TEST_RESUME; 542 case VMX_CR: 543 switch (vmx_get_test_stage()) { 544 case 4: 545 report("Read shadowing CR0", 0); 546 vmx_inc_test_stage(); 547 break; 548 case 5: 549 report("Read shadowing CR4", 0); 550 vmx_inc_test_stage(); 551 break; 552 case 6: 553 report("Write shadowing CR0 (same value)", 0); 554 vmx_inc_test_stage(); 555 break; 556 case 7: 557 report("Write shadowing CR4 (same value)", 0); 558 vmx_inc_test_stage(); 559 break; 560 case 8: 561 case 9: 562 // 0x600 encodes "mov %esi, %cr0" 563 if (exit_qual == 0x600) 564 vmx_inc_test_stage(); 565 break; 566 case 10: 567 case 11: 568 // 0x604 encodes "mov %esi, %cr4" 569 if (exit_qual == 0x604) 570 vmx_inc_test_stage(); 571 break; 572 default: 573 // Should not reach here 574 report("unexpected stage, %d", false, 575 vmx_get_test_stage()); 576 print_vmexit_info(); 577 return VMX_TEST_VMEXIT; 578 } 579 vmcs_write(GUEST_RIP, guest_rip + insn_len); 580 return VMX_TEST_RESUME; 581 default: 582 report("Unknown exit reason, %ld", false, reason); 583 print_vmexit_info(); 584 } 585 return VMX_TEST_VMEXIT; 586 } 587 588 static int iobmp_init() 589 { 590 u32 ctrl_cpu0; 591 592 io_bitmap_a = alloc_page(); 593 io_bitmap_b = alloc_page(); 594 memset(io_bitmap_a, 0x0, PAGE_SIZE); 595 memset(io_bitmap_b, 0x0, PAGE_SIZE); 596 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 597 ctrl_cpu0 |= CPU_IO_BITMAP; 598 ctrl_cpu0 &= (~CPU_IO); 599 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 600 vmcs_write(IO_BITMAP_A, (u64)io_bitmap_a); 601 vmcs_write(IO_BITMAP_B, (u64)io_bitmap_b); 602 return VMX_TEST_START; 603 } 604 605 static void iobmp_main() 606 { 607 // stage 0, test IO pass 608 vmx_set_test_stage(0); 609 inb(0x5000); 610 outb(0x0, 0x5000); 611 report("I/O bitmap - I/O pass", vmx_get_test_stage() == 0); 612 // test IO width, in/out 613 ((u8 *)io_bitmap_a)[0] = 0xFF; 614 vmx_set_test_stage(2); 615 inb(0x0); 616 report("I/O bitmap - trap in", vmx_get_test_stage() == 3); 617 vmx_set_test_stage(3); 618 outw(0x0, 0x0); 619 report("I/O bitmap - trap out", vmx_get_test_stage() == 4); 620 vmx_set_test_stage(4); 621 inl(0x0); 622 report("I/O bitmap - I/O width, long", vmx_get_test_stage() == 5); 623 // test low/high IO port 624 vmx_set_test_stage(5); 625 ((u8 *)io_bitmap_a)[0x5000 / 8] = (1 << (0x5000 % 8)); 626 inb(0x5000); 627 report("I/O bitmap - I/O port, low part", vmx_get_test_stage() == 6); 628 vmx_set_test_stage(6); 629 ((u8 *)io_bitmap_b)[0x1000 / 8] = (1 << (0x1000 % 8)); 630 inb(0x9000); 631 report("I/O bitmap - I/O port, high part", vmx_get_test_stage() == 7); 632 // test partial pass 633 vmx_set_test_stage(7); 634 inl(0x4FFF); 635 report("I/O bitmap - partial pass", vmx_get_test_stage() == 8); 636 // test overrun 637 vmx_set_test_stage(8); 638 memset(io_bitmap_a, 0x0, PAGE_SIZE); 639 memset(io_bitmap_b, 0x0, PAGE_SIZE); 640 inl(0xFFFF); 641 report("I/O bitmap - overrun", vmx_get_test_stage() == 9); 642 vmx_set_test_stage(9); 643 vmcall(); 644 outb(0x0, 0x0); 645 report("I/O bitmap - ignore unconditional exiting", 646 vmx_get_test_stage() == 9); 647 vmx_set_test_stage(10); 648 vmcall(); 649 outb(0x0, 0x0); 650 report("I/O bitmap - unconditional exiting", 651 vmx_get_test_stage() == 11); 652 } 653 654 static int iobmp_exit_handler() 655 { 656 u64 guest_rip; 657 ulong reason, exit_qual; 658 u32 insn_len, ctrl_cpu0; 659 660 guest_rip = vmcs_read(GUEST_RIP); 661 reason = vmcs_read(EXI_REASON) & 0xff; 662 exit_qual = vmcs_read(EXI_QUALIFICATION); 663 insn_len = vmcs_read(EXI_INST_LEN); 664 switch (reason) { 665 case VMX_IO: 666 switch (vmx_get_test_stage()) { 667 case 0: 668 case 1: 669 vmx_inc_test_stage(); 670 break; 671 case 2: 672 report("I/O bitmap - I/O width, byte", 673 (exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_BYTE); 674 report("I/O bitmap - I/O direction, in", exit_qual & VMX_IO_IN); 675 vmx_inc_test_stage(); 676 break; 677 case 3: 678 report("I/O bitmap - I/O width, word", 679 (exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_WORD); 680 report("I/O bitmap - I/O direction, out", 681 !(exit_qual & VMX_IO_IN)); 682 vmx_inc_test_stage(); 683 break; 684 case 4: 685 report("I/O bitmap - I/O width, long", 686 (exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_LONG); 687 vmx_inc_test_stage(); 688 break; 689 case 5: 690 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x5000) 691 vmx_inc_test_stage(); 692 break; 693 case 6: 694 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x9000) 695 vmx_inc_test_stage(); 696 break; 697 case 7: 698 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x4FFF) 699 vmx_inc_test_stage(); 700 break; 701 case 8: 702 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0xFFFF) 703 vmx_inc_test_stage(); 704 break; 705 case 9: 706 case 10: 707 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 708 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0 & ~CPU_IO); 709 vmx_inc_test_stage(); 710 break; 711 default: 712 // Should not reach here 713 report("unexpected stage, %d", false, 714 vmx_get_test_stage()); 715 print_vmexit_info(); 716 return VMX_TEST_VMEXIT; 717 } 718 vmcs_write(GUEST_RIP, guest_rip + insn_len); 719 return VMX_TEST_RESUME; 720 case VMX_VMCALL: 721 switch (vmx_get_test_stage()) { 722 case 9: 723 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 724 ctrl_cpu0 |= CPU_IO | CPU_IO_BITMAP; 725 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 726 break; 727 case 10: 728 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 729 ctrl_cpu0 = (ctrl_cpu0 & ~CPU_IO_BITMAP) | CPU_IO; 730 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 731 break; 732 default: 733 // Should not reach here 734 report("unexpected stage, %d", false, 735 vmx_get_test_stage()); 736 print_vmexit_info(); 737 return VMX_TEST_VMEXIT; 738 } 739 vmcs_write(GUEST_RIP, guest_rip + insn_len); 740 return VMX_TEST_RESUME; 741 default: 742 printf("guest_rip = %#lx\n", guest_rip); 743 printf("\tERROR : Undefined exit reason, reason = %ld.\n", reason); 744 break; 745 } 746 return VMX_TEST_VMEXIT; 747 } 748 749 #define INSN_CPU0 0 750 #define INSN_CPU1 1 751 #define INSN_ALWAYS_TRAP 2 752 753 #define FIELD_EXIT_QUAL (1 << 0) 754 #define FIELD_INSN_INFO (1 << 1) 755 756 asm( 757 "insn_hlt: hlt;ret\n\t" 758 "insn_invlpg: invlpg 0x12345678;ret\n\t" 759 "insn_mwait: xor %eax, %eax; xor %ecx, %ecx; mwait;ret\n\t" 760 "insn_rdpmc: xor %ecx, %ecx; rdpmc;ret\n\t" 761 "insn_rdtsc: rdtsc;ret\n\t" 762 "insn_cr3_load: mov cr3,%rax; mov %rax,%cr3;ret\n\t" 763 "insn_cr3_store: mov %cr3,%rax;ret\n\t" 764 #ifdef __x86_64__ 765 "insn_cr8_load: mov %rax,%cr8;ret\n\t" 766 "insn_cr8_store: mov %cr8,%rax;ret\n\t" 767 #endif 768 "insn_monitor: xor %eax, %eax; xor %ecx, %ecx; xor %edx, %edx; monitor;ret\n\t" 769 "insn_pause: pause;ret\n\t" 770 "insn_wbinvd: wbinvd;ret\n\t" 771 "insn_cpuid: mov $10, %eax; cpuid;ret\n\t" 772 "insn_invd: invd;ret\n\t" 773 "insn_sgdt: sgdt gdt64_desc;ret\n\t" 774 "insn_lgdt: lgdt gdt64_desc;ret\n\t" 775 "insn_sidt: sidt idt_descr;ret\n\t" 776 "insn_lidt: lidt idt_descr;ret\n\t" 777 "insn_sldt: sldt %ax;ret\n\t" 778 "insn_lldt: xor %eax, %eax; lldt %ax;ret\n\t" 779 "insn_str: str %ax;ret\n\t" 780 "insn_rdrand: rdrand %rax;ret\n\t" 781 "insn_rdseed: rdseed %rax;ret\n\t" 782 ); 783 extern void insn_hlt(); 784 extern void insn_invlpg(); 785 extern void insn_mwait(); 786 extern void insn_rdpmc(); 787 extern void insn_rdtsc(); 788 extern void insn_cr3_load(); 789 extern void insn_cr3_store(); 790 #ifdef __x86_64__ 791 extern void insn_cr8_load(); 792 extern void insn_cr8_store(); 793 #endif 794 extern void insn_monitor(); 795 extern void insn_pause(); 796 extern void insn_wbinvd(); 797 extern void insn_sgdt(); 798 extern void insn_lgdt(); 799 extern void insn_sidt(); 800 extern void insn_lidt(); 801 extern void insn_sldt(); 802 extern void insn_lldt(); 803 extern void insn_str(); 804 extern void insn_cpuid(); 805 extern void insn_invd(); 806 extern void insn_rdrand(); 807 extern void insn_rdseed(); 808 809 u32 cur_insn; 810 u64 cr3; 811 812 struct insn_table { 813 const char *name; 814 u32 flag; 815 void (*insn_func)(); 816 u32 type; 817 u32 reason; 818 ulong exit_qual; 819 u32 insn_info; 820 // Use FIELD_EXIT_QUAL and FIELD_INSN_INFO to define 821 // which field need to be tested, reason is always tested 822 u32 test_field; 823 }; 824 825 /* 826 * Add more test cases of instruction intercept here. Elements in this 827 * table is: 828 * name/control flag/insn function/type/exit reason/exit qulification/ 829 * instruction info/field to test 830 * The last field defines which fields (exit_qual and insn_info) need to be 831 * tested in exit handler. If set to 0, only "reason" is checked. 832 */ 833 static struct insn_table insn_table[] = { 834 // Flags for Primary Processor-Based VM-Execution Controls 835 {"HLT", CPU_HLT, insn_hlt, INSN_CPU0, 12, 0, 0, 0}, 836 {"INVLPG", CPU_INVLPG, insn_invlpg, INSN_CPU0, 14, 837 0x12345678, 0, FIELD_EXIT_QUAL}, 838 {"MWAIT", CPU_MWAIT, insn_mwait, INSN_CPU0, 36, 0, 0, 0}, 839 {"RDPMC", CPU_RDPMC, insn_rdpmc, INSN_CPU0, 15, 0, 0, 0}, 840 {"RDTSC", CPU_RDTSC, insn_rdtsc, INSN_CPU0, 16, 0, 0, 0}, 841 {"CR3 load", CPU_CR3_LOAD, insn_cr3_load, INSN_CPU0, 28, 0x3, 0, 842 FIELD_EXIT_QUAL}, 843 {"CR3 store", CPU_CR3_STORE, insn_cr3_store, INSN_CPU0, 28, 0x13, 0, 844 FIELD_EXIT_QUAL}, 845 #ifdef __x86_64__ 846 {"CR8 load", CPU_CR8_LOAD, insn_cr8_load, INSN_CPU0, 28, 0x8, 0, 847 FIELD_EXIT_QUAL}, 848 {"CR8 store", CPU_CR8_STORE, insn_cr8_store, INSN_CPU0, 28, 0x18, 0, 849 FIELD_EXIT_QUAL}, 850 #endif 851 {"MONITOR", CPU_MONITOR, insn_monitor, INSN_CPU0, 39, 0, 0, 0}, 852 {"PAUSE", CPU_PAUSE, insn_pause, INSN_CPU0, 40, 0, 0, 0}, 853 // Flags for Secondary Processor-Based VM-Execution Controls 854 {"WBINVD", CPU_WBINVD, insn_wbinvd, INSN_CPU1, 54, 0, 0, 0}, 855 {"DESC_TABLE (SGDT)", CPU_DESC_TABLE, insn_sgdt, INSN_CPU1, 46, 0, 0, 0}, 856 {"DESC_TABLE (LGDT)", CPU_DESC_TABLE, insn_lgdt, INSN_CPU1, 46, 0, 0, 0}, 857 {"DESC_TABLE (SIDT)", CPU_DESC_TABLE, insn_sidt, INSN_CPU1, 46, 0, 0, 0}, 858 {"DESC_TABLE (LIDT)", CPU_DESC_TABLE, insn_lidt, INSN_CPU1, 46, 0, 0, 0}, 859 {"DESC_TABLE (SLDT)", CPU_DESC_TABLE, insn_sldt, INSN_CPU1, 47, 0, 0, 0}, 860 {"DESC_TABLE (LLDT)", CPU_DESC_TABLE, insn_lldt, INSN_CPU1, 47, 0, 0, 0}, 861 {"DESC_TABLE (STR)", CPU_DESC_TABLE, insn_str, INSN_CPU1, 47, 0, 0, 0}, 862 /* LTR causes a #GP if done with a busy selector, so it is not tested. */ 863 {"RDRAND", CPU_RDRAND, insn_rdrand, INSN_CPU1, VMX_RDRAND, 0, 0, 0}, 864 {"RDSEED", CPU_RDSEED, insn_rdseed, INSN_CPU1, VMX_RDSEED, 0, 0, 0}, 865 // Instructions always trap 866 {"CPUID", 0, insn_cpuid, INSN_ALWAYS_TRAP, 10, 0, 0, 0}, 867 {"INVD", 0, insn_invd, INSN_ALWAYS_TRAP, 13, 0, 0, 0}, 868 // Instructions never trap 869 {NULL}, 870 }; 871 872 static int insn_intercept_init() 873 { 874 u32 ctrl_cpu; 875 876 ctrl_cpu = ctrl_cpu_rev[0].set | CPU_SECONDARY; 877 ctrl_cpu &= ctrl_cpu_rev[0].clr; 878 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu); 879 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu_rev[1].set); 880 cr3 = read_cr3(); 881 return VMX_TEST_START; 882 } 883 884 static void insn_intercept_main() 885 { 886 for (cur_insn = 0; insn_table[cur_insn].name != NULL; cur_insn++) { 887 vmx_set_test_stage(cur_insn * 2); 888 if ((insn_table[cur_insn].type == INSN_CPU0 && 889 !(ctrl_cpu_rev[0].clr & insn_table[cur_insn].flag)) || 890 (insn_table[cur_insn].type == INSN_CPU1 && 891 !(ctrl_cpu_rev[1].clr & insn_table[cur_insn].flag))) { 892 printf("\tCPU_CTRL%d.CPU_%s is not supported.\n", 893 insn_table[cur_insn].type - INSN_CPU0, 894 insn_table[cur_insn].name); 895 continue; 896 } 897 898 if ((insn_table[cur_insn].type == INSN_CPU0 && 899 !(ctrl_cpu_rev[0].set & insn_table[cur_insn].flag)) || 900 (insn_table[cur_insn].type == INSN_CPU1 && 901 !(ctrl_cpu_rev[1].set & insn_table[cur_insn].flag))) { 902 /* skip hlt, it stalls the guest and is tested below */ 903 if (insn_table[cur_insn].insn_func != insn_hlt) 904 insn_table[cur_insn].insn_func(); 905 report("execute %s", vmx_get_test_stage() == cur_insn * 2, 906 insn_table[cur_insn].name); 907 } else if (insn_table[cur_insn].type != INSN_ALWAYS_TRAP) 908 printf("\tCPU_CTRL%d.CPU_%s always traps.\n", 909 insn_table[cur_insn].type - INSN_CPU0, 910 insn_table[cur_insn].name); 911 912 vmcall(); 913 914 insn_table[cur_insn].insn_func(); 915 report("intercept %s", vmx_get_test_stage() == cur_insn * 2 + 1, 916 insn_table[cur_insn].name); 917 918 vmx_set_test_stage(cur_insn * 2 + 1); 919 vmcall(); 920 } 921 } 922 923 static int insn_intercept_exit_handler() 924 { 925 u64 guest_rip; 926 u32 reason; 927 ulong exit_qual; 928 u32 insn_len; 929 u32 insn_info; 930 bool pass; 931 932 guest_rip = vmcs_read(GUEST_RIP); 933 reason = vmcs_read(EXI_REASON) & 0xff; 934 exit_qual = vmcs_read(EXI_QUALIFICATION); 935 insn_len = vmcs_read(EXI_INST_LEN); 936 insn_info = vmcs_read(EXI_INST_INFO); 937 938 if (reason == VMX_VMCALL) { 939 u32 val = 0; 940 941 if (insn_table[cur_insn].type == INSN_CPU0) 942 val = vmcs_read(CPU_EXEC_CTRL0); 943 else if (insn_table[cur_insn].type == INSN_CPU1) 944 val = vmcs_read(CPU_EXEC_CTRL1); 945 946 if (vmx_get_test_stage() & 1) 947 val &= ~insn_table[cur_insn].flag; 948 else 949 val |= insn_table[cur_insn].flag; 950 951 if (insn_table[cur_insn].type == INSN_CPU0) 952 vmcs_write(CPU_EXEC_CTRL0, val | ctrl_cpu_rev[0].set); 953 else if (insn_table[cur_insn].type == INSN_CPU1) 954 vmcs_write(CPU_EXEC_CTRL1, val | ctrl_cpu_rev[1].set); 955 } else { 956 pass = (cur_insn * 2 == vmx_get_test_stage()) && 957 insn_table[cur_insn].reason == reason; 958 if (insn_table[cur_insn].test_field & FIELD_EXIT_QUAL && 959 insn_table[cur_insn].exit_qual != exit_qual) 960 pass = false; 961 if (insn_table[cur_insn].test_field & FIELD_INSN_INFO && 962 insn_table[cur_insn].insn_info != insn_info) 963 pass = false; 964 if (pass) 965 vmx_inc_test_stage(); 966 } 967 vmcs_write(GUEST_RIP, guest_rip + insn_len); 968 return VMX_TEST_RESUME; 969 } 970 971 972 /* Enables EPT and sets up the identity map. */ 973 static int setup_ept(bool enable_ad) 974 { 975 unsigned long end_of_memory; 976 u32 ctrl_cpu[2]; 977 978 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 979 !(ctrl_cpu_rev[1].clr & CPU_EPT)) { 980 printf("\tEPT is not supported"); 981 return 1; 982 } 983 984 985 if (!(ept_vpid.val & EPT_CAP_UC) && 986 !(ept_vpid.val & EPT_CAP_WB)) { 987 printf("\tEPT paging-structure memory type " 988 "UC&WB are not supported\n"); 989 return 1; 990 } 991 if (ept_vpid.val & EPT_CAP_UC) 992 eptp = EPT_MEM_TYPE_UC; 993 else 994 eptp = EPT_MEM_TYPE_WB; 995 if (!(ept_vpid.val & EPT_CAP_PWL4)) { 996 printf("\tPWL4 is not supported\n"); 997 return 1; 998 } 999 ctrl_cpu[0] = vmcs_read(CPU_EXEC_CTRL0); 1000 ctrl_cpu[1] = vmcs_read(CPU_EXEC_CTRL1); 1001 ctrl_cpu[0] = (ctrl_cpu[0] | CPU_SECONDARY) 1002 & ctrl_cpu_rev[0].clr; 1003 ctrl_cpu[1] = (ctrl_cpu[1] | CPU_EPT) 1004 & ctrl_cpu_rev[1].clr; 1005 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu[0]); 1006 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu[1]); 1007 eptp |= (3 << EPTP_PG_WALK_LEN_SHIFT); 1008 pml4 = alloc_page(); 1009 memset(pml4, 0, PAGE_SIZE); 1010 eptp |= virt_to_phys(pml4); 1011 if (enable_ad) 1012 eptp |= EPTP_AD_FLAG; 1013 vmcs_write(EPTP, eptp); 1014 end_of_memory = fwcfg_get_u64(FW_CFG_RAM_SIZE); 1015 if (end_of_memory < (1ul << 32)) 1016 end_of_memory = (1ul << 32); 1017 /* Cannot use large EPT pages if we need to track EPT 1018 * accessed/dirty bits at 4K granularity. 1019 */ 1020 setup_ept_range(pml4, 0, end_of_memory, 0, 1021 !enable_ad && ept_2m_supported(), 1022 EPT_WA | EPT_RA | EPT_EA); 1023 return 0; 1024 } 1025 1026 static void ept_enable_ad_bits(void) 1027 { 1028 eptp |= EPTP_AD_FLAG; 1029 vmcs_write(EPTP, eptp); 1030 } 1031 1032 static void ept_disable_ad_bits(void) 1033 { 1034 eptp &= ~EPTP_AD_FLAG; 1035 vmcs_write(EPTP, eptp); 1036 } 1037 1038 static void ept_enable_ad_bits_or_skip_test(void) 1039 { 1040 if (!ept_ad_bits_supported()) 1041 test_skip("EPT AD bits not supported."); 1042 ept_enable_ad_bits(); 1043 } 1044 1045 static int apic_version; 1046 1047 static int ept_init_common(bool have_ad) 1048 { 1049 int ret; 1050 struct pci_dev pcidev; 1051 1052 if (setup_ept(have_ad)) 1053 return VMX_TEST_EXIT; 1054 data_page1 = alloc_page(); 1055 data_page2 = alloc_page(); 1056 memset(data_page1, 0x0, PAGE_SIZE); 1057 memset(data_page2, 0x0, PAGE_SIZE); 1058 *((u32 *)data_page1) = MAGIC_VAL_1; 1059 *((u32 *)data_page2) = MAGIC_VAL_2; 1060 install_ept(pml4, (unsigned long)data_page1, (unsigned long)data_page2, 1061 EPT_RA | EPT_WA | EPT_EA); 1062 1063 apic_version = apic_read(APIC_LVR); 1064 1065 ret = pci_find_dev(PCI_VENDOR_ID_REDHAT, PCI_DEVICE_ID_REDHAT_TEST); 1066 if (ret != PCIDEVADDR_INVALID) { 1067 pci_dev_init(&pcidev, ret); 1068 pci_physaddr = pcidev.resource[PCI_TESTDEV_BAR_MEM]; 1069 } 1070 1071 return VMX_TEST_START; 1072 } 1073 1074 static int ept_init() 1075 { 1076 return ept_init_common(false); 1077 } 1078 1079 static void ept_common() 1080 { 1081 vmx_set_test_stage(0); 1082 if (*((u32 *)data_page2) != MAGIC_VAL_1 || 1083 *((u32 *)data_page1) != MAGIC_VAL_1) 1084 report("EPT basic framework - read", 0); 1085 else { 1086 *((u32 *)data_page2) = MAGIC_VAL_3; 1087 vmcall(); 1088 if (vmx_get_test_stage() == 1) { 1089 if (*((u32 *)data_page1) == MAGIC_VAL_3 && 1090 *((u32 *)data_page2) == MAGIC_VAL_2) 1091 report("EPT basic framework", 1); 1092 else 1093 report("EPT basic framework - remap", 1); 1094 } 1095 } 1096 // Test EPT Misconfigurations 1097 vmx_set_test_stage(1); 1098 vmcall(); 1099 *((u32 *)data_page1) = MAGIC_VAL_1; 1100 if (vmx_get_test_stage() != 2) { 1101 report("EPT misconfigurations", 0); 1102 goto t1; 1103 } 1104 vmx_set_test_stage(2); 1105 vmcall(); 1106 *((u32 *)data_page1) = MAGIC_VAL_1; 1107 report("EPT misconfigurations", vmx_get_test_stage() == 3); 1108 t1: 1109 // Test EPT violation 1110 vmx_set_test_stage(3); 1111 vmcall(); 1112 *((u32 *)data_page1) = MAGIC_VAL_1; 1113 report("EPT violation - page permission", vmx_get_test_stage() == 4); 1114 // Violation caused by EPT paging structure 1115 vmx_set_test_stage(4); 1116 vmcall(); 1117 *((u32 *)data_page1) = MAGIC_VAL_2; 1118 report("EPT violation - paging structure", vmx_get_test_stage() == 5); 1119 1120 // MMIO Read/Write 1121 vmx_set_test_stage(5); 1122 vmcall(); 1123 1124 *(u32 volatile *)pci_physaddr; 1125 report("MMIO EPT violation - read", vmx_get_test_stage() == 6); 1126 1127 *(u32 volatile *)pci_physaddr = MAGIC_VAL_1; 1128 report("MMIO EPT violation - write", vmx_get_test_stage() == 7); 1129 } 1130 1131 static void ept_main() 1132 { 1133 ept_common(); 1134 1135 // Test EPT access to L1 MMIO 1136 vmx_set_test_stage(7); 1137 report("EPT - MMIO access", *((u32 *)0xfee00030UL) == apic_version); 1138 1139 // Test invalid operand for INVEPT 1140 vmcall(); 1141 report("EPT - unsupported INVEPT", vmx_get_test_stage() == 8); 1142 } 1143 1144 bool invept_test(int type, u64 eptp) 1145 { 1146 bool ret, supported; 1147 1148 supported = ept_vpid.val & (EPT_CAP_INVEPT_SINGLE >> INVEPT_SINGLE << type); 1149 ret = invept(type, eptp); 1150 1151 if (ret == !supported) 1152 return false; 1153 1154 if (!supported) 1155 printf("WARNING: unsupported invept passed!\n"); 1156 else 1157 printf("WARNING: invept failed!\n"); 1158 1159 return true; 1160 } 1161 1162 static int pml_exit_handler(void) 1163 { 1164 u16 index, count; 1165 ulong reason = vmcs_read(EXI_REASON) & 0xff; 1166 u64 *pmlbuf = pml_log; 1167 u64 guest_rip = vmcs_read(GUEST_RIP);; 1168 u64 guest_cr3 = vmcs_read(GUEST_CR3); 1169 u32 insn_len = vmcs_read(EXI_INST_LEN); 1170 1171 switch (reason) { 1172 case VMX_VMCALL: 1173 switch (vmx_get_test_stage()) { 1174 case 0: 1175 index = vmcs_read(GUEST_PML_INDEX); 1176 for (count = index + 1; count < PML_INDEX; count++) { 1177 if (pmlbuf[count] == (u64)data_page2) { 1178 vmx_inc_test_stage(); 1179 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page2); 1180 break; 1181 } 1182 } 1183 break; 1184 case 1: 1185 index = vmcs_read(GUEST_PML_INDEX); 1186 /* Keep clearing the dirty bit till a overflow */ 1187 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page2); 1188 break; 1189 default: 1190 report("unexpected stage, %d.", false, 1191 vmx_get_test_stage()); 1192 print_vmexit_info(); 1193 return VMX_TEST_VMEXIT; 1194 } 1195 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1196 return VMX_TEST_RESUME; 1197 case VMX_PML_FULL: 1198 vmx_inc_test_stage(); 1199 vmcs_write(GUEST_PML_INDEX, PML_INDEX - 1); 1200 return VMX_TEST_RESUME; 1201 default: 1202 report("Unknown exit reason, %ld", false, reason); 1203 print_vmexit_info(); 1204 } 1205 return VMX_TEST_VMEXIT; 1206 } 1207 1208 static int ept_exit_handler_common(bool have_ad) 1209 { 1210 u64 guest_rip; 1211 u64 guest_cr3; 1212 ulong reason; 1213 u32 insn_len; 1214 u32 exit_qual; 1215 static unsigned long data_page1_pte, data_page1_pte_pte, memaddr_pte; 1216 1217 guest_rip = vmcs_read(GUEST_RIP); 1218 guest_cr3 = vmcs_read(GUEST_CR3); 1219 reason = vmcs_read(EXI_REASON) & 0xff; 1220 insn_len = vmcs_read(EXI_INST_LEN); 1221 exit_qual = vmcs_read(EXI_QUALIFICATION); 1222 switch (reason) { 1223 case VMX_VMCALL: 1224 switch (vmx_get_test_stage()) { 1225 case 0: 1226 check_ept_ad(pml4, guest_cr3, 1227 (unsigned long)data_page1, 1228 have_ad ? EPT_ACCESS_FLAG : 0, 1229 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1230 check_ept_ad(pml4, guest_cr3, 1231 (unsigned long)data_page2, 1232 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0, 1233 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1234 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1235 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page2); 1236 if (have_ad) 1237 ept_sync(INVEPT_SINGLE, eptp);; 1238 if (*((u32 *)data_page1) == MAGIC_VAL_3 && 1239 *((u32 *)data_page2) == MAGIC_VAL_2) { 1240 vmx_inc_test_stage(); 1241 install_ept(pml4, (unsigned long)data_page2, 1242 (unsigned long)data_page2, 1243 EPT_RA | EPT_WA | EPT_EA); 1244 } else 1245 report("EPT basic framework - write", 0); 1246 break; 1247 case 1: 1248 install_ept(pml4, (unsigned long)data_page1, 1249 (unsigned long)data_page1, EPT_WA); 1250 ept_sync(INVEPT_SINGLE, eptp); 1251 break; 1252 case 2: 1253 install_ept(pml4, (unsigned long)data_page1, 1254 (unsigned long)data_page1, 1255 EPT_RA | EPT_WA | EPT_EA | 1256 (2 << EPT_MEM_TYPE_SHIFT)); 1257 ept_sync(INVEPT_SINGLE, eptp); 1258 break; 1259 case 3: 1260 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1261 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)data_page1, 1262 1, &data_page1_pte)); 1263 set_ept_pte(pml4, (unsigned long)data_page1, 1264 1, data_page1_pte & ~EPT_PRESENT); 1265 ept_sync(INVEPT_SINGLE, eptp); 1266 break; 1267 case 4: 1268 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)data_page1, 1269 2, &data_page1_pte)); 1270 data_page1_pte &= PAGE_MASK; 1271 TEST_ASSERT(get_ept_pte(pml4, data_page1_pte, 1272 2, &data_page1_pte_pte)); 1273 set_ept_pte(pml4, data_page1_pte, 2, 1274 data_page1_pte_pte & ~EPT_PRESENT); 1275 ept_sync(INVEPT_SINGLE, eptp); 1276 break; 1277 case 5: 1278 install_ept(pml4, (unsigned long)pci_physaddr, 1279 (unsigned long)pci_physaddr, 0); 1280 ept_sync(INVEPT_SINGLE, eptp); 1281 break; 1282 case 7: 1283 if (!invept_test(0, eptp)) 1284 vmx_inc_test_stage(); 1285 break; 1286 // Should not reach here 1287 default: 1288 report("ERROR - unexpected stage, %d.", false, 1289 vmx_get_test_stage()); 1290 print_vmexit_info(); 1291 return VMX_TEST_VMEXIT; 1292 } 1293 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1294 return VMX_TEST_RESUME; 1295 case VMX_EPT_MISCONFIG: 1296 switch (vmx_get_test_stage()) { 1297 case 1: 1298 case 2: 1299 vmx_inc_test_stage(); 1300 install_ept(pml4, (unsigned long)data_page1, 1301 (unsigned long)data_page1, 1302 EPT_RA | EPT_WA | EPT_EA); 1303 ept_sync(INVEPT_SINGLE, eptp); 1304 break; 1305 // Should not reach here 1306 default: 1307 report("ERROR - unexpected stage, %d.", false, 1308 vmx_get_test_stage()); 1309 print_vmexit_info(); 1310 return VMX_TEST_VMEXIT; 1311 } 1312 return VMX_TEST_RESUME; 1313 case VMX_EPT_VIOLATION: 1314 switch(vmx_get_test_stage()) { 1315 case 3: 1316 check_ept_ad(pml4, guest_cr3, (unsigned long)data_page1, 0, 1317 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1318 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1319 if (exit_qual == (EPT_VLT_WR | EPT_VLT_LADDR_VLD | 1320 EPT_VLT_PADDR)) 1321 vmx_inc_test_stage(); 1322 set_ept_pte(pml4, (unsigned long)data_page1, 1323 1, data_page1_pte | (EPT_PRESENT)); 1324 ept_sync(INVEPT_SINGLE, eptp); 1325 break; 1326 case 4: 1327 check_ept_ad(pml4, guest_cr3, (unsigned long)data_page1, 0, 1328 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1329 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1330 if (exit_qual == (EPT_VLT_RD | 1331 (have_ad ? EPT_VLT_WR : 0) | 1332 EPT_VLT_LADDR_VLD)) 1333 vmx_inc_test_stage(); 1334 set_ept_pte(pml4, data_page1_pte, 2, 1335 data_page1_pte_pte | (EPT_PRESENT)); 1336 ept_sync(INVEPT_SINGLE, eptp); 1337 break; 1338 case 5: 1339 if (exit_qual & EPT_VLT_RD) 1340 vmx_inc_test_stage(); 1341 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)pci_physaddr, 1342 1, &memaddr_pte)); 1343 set_ept_pte(pml4, memaddr_pte, 1, memaddr_pte | EPT_RA); 1344 ept_sync(INVEPT_SINGLE, eptp); 1345 break; 1346 case 6: 1347 if (exit_qual & EPT_VLT_WR) 1348 vmx_inc_test_stage(); 1349 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)pci_physaddr, 1350 1, &memaddr_pte)); 1351 set_ept_pte(pml4, memaddr_pte, 1, memaddr_pte | EPT_RA | EPT_WA); 1352 ept_sync(INVEPT_SINGLE, eptp); 1353 break; 1354 default: 1355 // Should not reach here 1356 report("ERROR : unexpected stage, %d", false, 1357 vmx_get_test_stage()); 1358 print_vmexit_info(); 1359 return VMX_TEST_VMEXIT; 1360 } 1361 return VMX_TEST_RESUME; 1362 default: 1363 report("Unknown exit reason, %ld", false, reason); 1364 print_vmexit_info(); 1365 } 1366 return VMX_TEST_VMEXIT; 1367 } 1368 1369 static int ept_exit_handler() 1370 { 1371 return ept_exit_handler_common(false); 1372 } 1373 1374 static int eptad_init() 1375 { 1376 int r = ept_init_common(true); 1377 1378 if (r == VMX_TEST_EXIT) 1379 return r; 1380 1381 if ((rdmsr(MSR_IA32_VMX_EPT_VPID_CAP) & EPT_CAP_AD_FLAG) == 0) { 1382 printf("\tEPT A/D bits are not supported"); 1383 return VMX_TEST_EXIT; 1384 } 1385 1386 return r; 1387 } 1388 1389 static int pml_init() 1390 { 1391 u32 ctrl_cpu; 1392 int r = eptad_init(); 1393 1394 if (r == VMX_TEST_EXIT) 1395 return r; 1396 1397 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1398 !(ctrl_cpu_rev[1].clr & CPU_PML)) { 1399 printf("\tPML is not supported"); 1400 return VMX_TEST_EXIT; 1401 } 1402 1403 pml_log = alloc_page(); 1404 memset(pml_log, 0x0, PAGE_SIZE); 1405 vmcs_write(PMLADDR, (u64)pml_log); 1406 vmcs_write(GUEST_PML_INDEX, PML_INDEX - 1); 1407 1408 ctrl_cpu = vmcs_read(CPU_EXEC_CTRL1) | CPU_PML; 1409 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu); 1410 1411 return VMX_TEST_START; 1412 } 1413 1414 static void pml_main() 1415 { 1416 int count = 0; 1417 1418 vmx_set_test_stage(0); 1419 *((u32 *)data_page2) = 0x1; 1420 vmcall(); 1421 report("PML - Dirty GPA Logging", vmx_get_test_stage() == 1); 1422 1423 while (vmx_get_test_stage() == 1) { 1424 vmcall(); 1425 *((u32 *)data_page2) = 0x1; 1426 if (count++ > PML_INDEX) 1427 break; 1428 } 1429 report("PML Full Event", vmx_get_test_stage() == 2); 1430 } 1431 1432 static void eptad_main() 1433 { 1434 ept_common(); 1435 } 1436 1437 static int eptad_exit_handler() 1438 { 1439 return ept_exit_handler_common(true); 1440 } 1441 1442 bool invvpid_test(int type, u16 vpid) 1443 { 1444 bool ret, supported; 1445 1446 supported = ept_vpid.val & 1447 (VPID_CAP_INVVPID_ADDR >> INVVPID_ADDR << type); 1448 ret = invvpid(type, vpid, 0); 1449 1450 if (ret == !supported) 1451 return false; 1452 1453 if (!supported) 1454 printf("WARNING: unsupported invvpid passed!\n"); 1455 else 1456 printf("WARNING: invvpid failed!\n"); 1457 1458 return true; 1459 } 1460 1461 static int vpid_init() 1462 { 1463 u32 ctrl_cpu1; 1464 1465 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1466 !(ctrl_cpu_rev[1].clr & CPU_VPID)) { 1467 printf("\tVPID is not supported"); 1468 return VMX_TEST_EXIT; 1469 } 1470 1471 ctrl_cpu1 = vmcs_read(CPU_EXEC_CTRL1); 1472 ctrl_cpu1 |= CPU_VPID; 1473 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu1); 1474 return VMX_TEST_START; 1475 } 1476 1477 static void vpid_main() 1478 { 1479 vmx_set_test_stage(0); 1480 vmcall(); 1481 report("INVVPID SINGLE ADDRESS", vmx_get_test_stage() == 1); 1482 vmx_set_test_stage(2); 1483 vmcall(); 1484 report("INVVPID SINGLE", vmx_get_test_stage() == 3); 1485 vmx_set_test_stage(4); 1486 vmcall(); 1487 report("INVVPID ALL", vmx_get_test_stage() == 5); 1488 } 1489 1490 static int vpid_exit_handler() 1491 { 1492 u64 guest_rip; 1493 ulong reason; 1494 u32 insn_len; 1495 1496 guest_rip = vmcs_read(GUEST_RIP); 1497 reason = vmcs_read(EXI_REASON) & 0xff; 1498 insn_len = vmcs_read(EXI_INST_LEN); 1499 1500 switch (reason) { 1501 case VMX_VMCALL: 1502 switch(vmx_get_test_stage()) { 1503 case 0: 1504 if (!invvpid_test(INVVPID_ADDR, 1)) 1505 vmx_inc_test_stage(); 1506 break; 1507 case 2: 1508 if (!invvpid_test(INVVPID_CONTEXT_GLOBAL, 1)) 1509 vmx_inc_test_stage(); 1510 break; 1511 case 4: 1512 if (!invvpid_test(INVVPID_ALL, 1)) 1513 vmx_inc_test_stage(); 1514 break; 1515 default: 1516 report("ERROR: unexpected stage, %d", false, 1517 vmx_get_test_stage()); 1518 print_vmexit_info(); 1519 return VMX_TEST_VMEXIT; 1520 } 1521 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1522 return VMX_TEST_RESUME; 1523 default: 1524 report("Unknown exit reason, %ld", false, reason); 1525 print_vmexit_info(); 1526 } 1527 return VMX_TEST_VMEXIT; 1528 } 1529 1530 #define TIMER_VECTOR 222 1531 1532 static volatile bool timer_fired; 1533 1534 static void timer_isr(isr_regs_t *regs) 1535 { 1536 timer_fired = true; 1537 apic_write(APIC_EOI, 0); 1538 } 1539 1540 static int interrupt_init(struct vmcs *vmcs) 1541 { 1542 msr_bmp_init(); 1543 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 1544 handle_irq(TIMER_VECTOR, timer_isr); 1545 return VMX_TEST_START; 1546 } 1547 1548 static void interrupt_main(void) 1549 { 1550 long long start, loops; 1551 1552 vmx_set_test_stage(0); 1553 1554 apic_write(APIC_LVTT, TIMER_VECTOR); 1555 irq_enable(); 1556 1557 apic_write(APIC_TMICT, 1); 1558 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1559 asm volatile ("nop"); 1560 report("direct interrupt while running guest", timer_fired); 1561 1562 apic_write(APIC_TMICT, 0); 1563 irq_disable(); 1564 vmcall(); 1565 timer_fired = false; 1566 apic_write(APIC_TMICT, 1); 1567 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1568 asm volatile ("nop"); 1569 report("intercepted interrupt while running guest", timer_fired); 1570 1571 irq_enable(); 1572 apic_write(APIC_TMICT, 0); 1573 irq_disable(); 1574 vmcall(); 1575 timer_fired = false; 1576 start = rdtsc(); 1577 apic_write(APIC_TMICT, 1000000); 1578 1579 asm volatile ("sti; hlt"); 1580 1581 report("direct interrupt + hlt", 1582 rdtsc() - start > 1000000 && timer_fired); 1583 1584 apic_write(APIC_TMICT, 0); 1585 irq_disable(); 1586 vmcall(); 1587 timer_fired = false; 1588 start = rdtsc(); 1589 apic_write(APIC_TMICT, 1000000); 1590 1591 asm volatile ("sti; hlt"); 1592 1593 report("intercepted interrupt + hlt", 1594 rdtsc() - start > 10000 && timer_fired); 1595 1596 apic_write(APIC_TMICT, 0); 1597 irq_disable(); 1598 vmcall(); 1599 timer_fired = false; 1600 start = rdtsc(); 1601 apic_write(APIC_TMICT, 1000000); 1602 1603 irq_enable(); 1604 asm volatile ("nop"); 1605 vmcall(); 1606 1607 report("direct interrupt + activity state hlt", 1608 rdtsc() - start > 10000 && timer_fired); 1609 1610 apic_write(APIC_TMICT, 0); 1611 irq_disable(); 1612 vmcall(); 1613 timer_fired = false; 1614 start = rdtsc(); 1615 apic_write(APIC_TMICT, 1000000); 1616 1617 irq_enable(); 1618 asm volatile ("nop"); 1619 vmcall(); 1620 1621 report("intercepted interrupt + activity state hlt", 1622 rdtsc() - start > 10000 && timer_fired); 1623 1624 apic_write(APIC_TMICT, 0); 1625 irq_disable(); 1626 vmx_set_test_stage(7); 1627 vmcall(); 1628 timer_fired = false; 1629 apic_write(APIC_TMICT, 1); 1630 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1631 asm volatile ("nop"); 1632 report("running a guest with interrupt acknowledgement set", timer_fired); 1633 1634 apic_write(APIC_TMICT, 0); 1635 irq_enable(); 1636 timer_fired = false; 1637 vmcall(); 1638 report("Inject an event to a halted guest", timer_fired); 1639 } 1640 1641 static int interrupt_exit_handler(void) 1642 { 1643 u64 guest_rip = vmcs_read(GUEST_RIP); 1644 ulong reason = vmcs_read(EXI_REASON) & 0xff; 1645 u32 insn_len = vmcs_read(EXI_INST_LEN); 1646 1647 switch (reason) { 1648 case VMX_VMCALL: 1649 switch (vmx_get_test_stage()) { 1650 case 0: 1651 case 2: 1652 case 5: 1653 vmcs_write(PIN_CONTROLS, 1654 vmcs_read(PIN_CONTROLS) | PIN_EXTINT); 1655 break; 1656 case 7: 1657 vmcs_write(EXI_CONTROLS, vmcs_read(EXI_CONTROLS) | EXI_INTA); 1658 vmcs_write(PIN_CONTROLS, 1659 vmcs_read(PIN_CONTROLS) | PIN_EXTINT); 1660 break; 1661 case 1: 1662 case 3: 1663 vmcs_write(PIN_CONTROLS, 1664 vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 1665 break; 1666 case 4: 1667 case 6: 1668 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 1669 break; 1670 1671 case 8: 1672 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 1673 vmcs_write(ENT_INTR_INFO, 1674 TIMER_VECTOR | 1675 (VMX_INTR_TYPE_EXT_INTR << INTR_INFO_INTR_TYPE_SHIFT) | 1676 INTR_INFO_VALID_MASK); 1677 break; 1678 } 1679 vmx_inc_test_stage(); 1680 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1681 return VMX_TEST_RESUME; 1682 case VMX_EXTINT: 1683 if (vmcs_read(EXI_CONTROLS) & EXI_INTA) { 1684 int vector = vmcs_read(EXI_INTR_INFO) & 0xff; 1685 handle_external_interrupt(vector); 1686 } else { 1687 irq_enable(); 1688 asm volatile ("nop"); 1689 irq_disable(); 1690 } 1691 if (vmx_get_test_stage() >= 2) 1692 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 1693 return VMX_TEST_RESUME; 1694 default: 1695 report("Unknown exit reason, %ld", false, reason); 1696 print_vmexit_info(); 1697 } 1698 1699 return VMX_TEST_VMEXIT; 1700 } 1701 1702 static int dbgctls_init(struct vmcs *vmcs) 1703 { 1704 u64 dr7 = 0x402; 1705 u64 zero = 0; 1706 1707 msr_bmp_init(); 1708 asm volatile( 1709 "mov %0,%%dr0\n\t" 1710 "mov %0,%%dr1\n\t" 1711 "mov %0,%%dr2\n\t" 1712 "mov %1,%%dr7\n\t" 1713 : : "r" (zero), "r" (dr7)); 1714 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x1); 1715 vmcs_write(GUEST_DR7, 0x404); 1716 vmcs_write(GUEST_DEBUGCTL, 0x2); 1717 1718 vmcs_write(ENT_CONTROLS, vmcs_read(ENT_CONTROLS) | ENT_LOAD_DBGCTLS); 1719 vmcs_write(EXI_CONTROLS, vmcs_read(EXI_CONTROLS) | EXI_SAVE_DBGCTLS); 1720 1721 return VMX_TEST_START; 1722 } 1723 1724 static void dbgctls_main(void) 1725 { 1726 u64 dr7, debugctl; 1727 1728 asm volatile("mov %%dr7,%0" : "=r" (dr7)); 1729 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR); 1730 /* Commented out: KVM does not support DEBUGCTL so far */ 1731 (void)debugctl; 1732 report("Load debug controls", dr7 == 0x404 /* && debugctl == 0x2 */); 1733 1734 dr7 = 0x408; 1735 asm volatile("mov %0,%%dr7" : : "r" (dr7)); 1736 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x3); 1737 1738 vmx_set_test_stage(0); 1739 vmcall(); 1740 report("Save debug controls", vmx_get_test_stage() == 1); 1741 1742 if (ctrl_enter_rev.set & ENT_LOAD_DBGCTLS || 1743 ctrl_exit_rev.set & EXI_SAVE_DBGCTLS) { 1744 printf("\tDebug controls are always loaded/saved\n"); 1745 return; 1746 } 1747 vmx_set_test_stage(2); 1748 vmcall(); 1749 1750 asm volatile("mov %%dr7,%0" : "=r" (dr7)); 1751 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR); 1752 /* Commented out: KVM does not support DEBUGCTL so far */ 1753 (void)debugctl; 1754 report("Guest=host debug controls", dr7 == 0x402 /* && debugctl == 0x1 */); 1755 1756 dr7 = 0x408; 1757 asm volatile("mov %0,%%dr7" : : "r" (dr7)); 1758 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x3); 1759 1760 vmx_set_test_stage(3); 1761 vmcall(); 1762 report("Don't save debug controls", vmx_get_test_stage() == 4); 1763 } 1764 1765 static int dbgctls_exit_handler(void) 1766 { 1767 unsigned int reason = vmcs_read(EXI_REASON) & 0xff; 1768 u32 insn_len = vmcs_read(EXI_INST_LEN); 1769 u64 guest_rip = vmcs_read(GUEST_RIP); 1770 u64 dr7, debugctl; 1771 1772 asm volatile("mov %%dr7,%0" : "=r" (dr7)); 1773 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR); 1774 1775 switch (reason) { 1776 case VMX_VMCALL: 1777 switch (vmx_get_test_stage()) { 1778 case 0: 1779 if (dr7 == 0x400 && debugctl == 0 && 1780 vmcs_read(GUEST_DR7) == 0x408 /* && 1781 Commented out: KVM does not support DEBUGCTL so far 1782 vmcs_read(GUEST_DEBUGCTL) == 0x3 */) 1783 vmx_inc_test_stage(); 1784 break; 1785 case 2: 1786 dr7 = 0x402; 1787 asm volatile("mov %0,%%dr7" : : "r" (dr7)); 1788 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x1); 1789 vmcs_write(GUEST_DR7, 0x404); 1790 vmcs_write(GUEST_DEBUGCTL, 0x2); 1791 1792 vmcs_write(ENT_CONTROLS, 1793 vmcs_read(ENT_CONTROLS) & ~ENT_LOAD_DBGCTLS); 1794 vmcs_write(EXI_CONTROLS, 1795 vmcs_read(EXI_CONTROLS) & ~EXI_SAVE_DBGCTLS); 1796 break; 1797 case 3: 1798 if (dr7 == 0x400 && debugctl == 0 && 1799 vmcs_read(GUEST_DR7) == 0x404 /* && 1800 Commented out: KVM does not support DEBUGCTL so far 1801 vmcs_read(GUEST_DEBUGCTL) == 0x2 */) 1802 vmx_inc_test_stage(); 1803 break; 1804 } 1805 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1806 return VMX_TEST_RESUME; 1807 default: 1808 report("Unknown exit reason, %d", false, reason); 1809 print_vmexit_info(); 1810 } 1811 return VMX_TEST_VMEXIT; 1812 } 1813 1814 struct vmx_msr_entry { 1815 u32 index; 1816 u32 reserved; 1817 u64 value; 1818 } __attribute__((packed)); 1819 1820 #define MSR_MAGIC 0x31415926 1821 struct vmx_msr_entry *exit_msr_store, *entry_msr_load, *exit_msr_load; 1822 1823 static int msr_switch_init(struct vmcs *vmcs) 1824 { 1825 msr_bmp_init(); 1826 exit_msr_store = alloc_page(); 1827 exit_msr_load = alloc_page(); 1828 entry_msr_load = alloc_page(); 1829 memset(exit_msr_store, 0, PAGE_SIZE); 1830 memset(exit_msr_load, 0, PAGE_SIZE); 1831 memset(entry_msr_load, 0, PAGE_SIZE); 1832 entry_msr_load[0].index = MSR_KERNEL_GS_BASE; 1833 entry_msr_load[0].value = MSR_MAGIC; 1834 1835 vmx_set_test_stage(1); 1836 vmcs_write(ENT_MSR_LD_CNT, 1); 1837 vmcs_write(ENTER_MSR_LD_ADDR, (u64)entry_msr_load); 1838 vmcs_write(EXI_MSR_ST_CNT, 1); 1839 vmcs_write(EXIT_MSR_ST_ADDR, (u64)exit_msr_store); 1840 vmcs_write(EXI_MSR_LD_CNT, 1); 1841 vmcs_write(EXIT_MSR_LD_ADDR, (u64)exit_msr_load); 1842 return VMX_TEST_START; 1843 } 1844 1845 static void msr_switch_main() 1846 { 1847 if (vmx_get_test_stage() == 1) { 1848 report("VM entry MSR load", 1849 rdmsr(MSR_KERNEL_GS_BASE) == MSR_MAGIC); 1850 vmx_set_test_stage(2); 1851 wrmsr(MSR_KERNEL_GS_BASE, MSR_MAGIC + 1); 1852 exit_msr_store[0].index = MSR_KERNEL_GS_BASE; 1853 exit_msr_load[0].index = MSR_KERNEL_GS_BASE; 1854 exit_msr_load[0].value = MSR_MAGIC + 2; 1855 } 1856 vmcall(); 1857 } 1858 1859 static int msr_switch_exit_handler() 1860 { 1861 ulong reason; 1862 1863 reason = vmcs_read(EXI_REASON); 1864 if (reason == VMX_VMCALL && vmx_get_test_stage() == 2) { 1865 report("VM exit MSR store", 1866 exit_msr_store[0].value == MSR_MAGIC + 1); 1867 report("VM exit MSR load", 1868 rdmsr(MSR_KERNEL_GS_BASE) == MSR_MAGIC + 2); 1869 vmx_set_test_stage(3); 1870 entry_msr_load[0].index = MSR_FS_BASE; 1871 return VMX_TEST_RESUME; 1872 } 1873 printf("ERROR %s: unexpected stage=%u or reason=%lu\n", 1874 __func__, vmx_get_test_stage(), reason); 1875 return VMX_TEST_EXIT; 1876 } 1877 1878 static int msr_switch_entry_failure(struct vmentry_failure *failure) 1879 { 1880 ulong reason; 1881 1882 if (failure->early) { 1883 printf("ERROR %s: early exit\n", __func__); 1884 return VMX_TEST_EXIT; 1885 } 1886 1887 reason = vmcs_read(EXI_REASON); 1888 if (reason == (VMX_ENTRY_FAILURE | VMX_FAIL_MSR) && 1889 vmx_get_test_stage() == 3) { 1890 report("VM entry MSR load: try to load FS_BASE", 1891 vmcs_read(EXI_QUALIFICATION) == 1); 1892 return VMX_TEST_VMEXIT; 1893 } 1894 printf("ERROR %s: unexpected stage=%u or reason=%lu\n", 1895 __func__, vmx_get_test_stage(), reason); 1896 return VMX_TEST_EXIT; 1897 } 1898 1899 static int vmmcall_init(struct vmcs *vmcs ) 1900 { 1901 vmcs_write(EXC_BITMAP, 1 << UD_VECTOR); 1902 return VMX_TEST_START; 1903 } 1904 1905 static void vmmcall_main(void) 1906 { 1907 asm volatile( 1908 "mov $0xABCD, %%rax\n\t" 1909 "vmmcall\n\t" 1910 ::: "rax"); 1911 1912 report("VMMCALL", 0); 1913 } 1914 1915 static int vmmcall_exit_handler() 1916 { 1917 ulong reason; 1918 1919 reason = vmcs_read(EXI_REASON); 1920 switch (reason) { 1921 case VMX_VMCALL: 1922 printf("here\n"); 1923 report("VMMCALL triggers #UD", 0); 1924 break; 1925 case VMX_EXC_NMI: 1926 report("VMMCALL triggers #UD", 1927 (vmcs_read(EXI_INTR_INFO) & 0xff) == UD_VECTOR); 1928 break; 1929 default: 1930 report("Unknown exit reason, %ld", false, reason); 1931 print_vmexit_info(); 1932 } 1933 1934 return VMX_TEST_VMEXIT; 1935 } 1936 1937 static int disable_rdtscp_init(struct vmcs *vmcs) 1938 { 1939 u32 ctrl_cpu1; 1940 1941 if (ctrl_cpu_rev[0].clr & CPU_SECONDARY) { 1942 ctrl_cpu1 = vmcs_read(CPU_EXEC_CTRL1); 1943 ctrl_cpu1 &= ~CPU_RDTSCP; 1944 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu1); 1945 } 1946 1947 return VMX_TEST_START; 1948 } 1949 1950 static void disable_rdtscp_ud_handler(struct ex_regs *regs) 1951 { 1952 switch (vmx_get_test_stage()) { 1953 case 0: 1954 report("RDTSCP triggers #UD", true); 1955 vmx_inc_test_stage(); 1956 regs->rip += 3; 1957 break; 1958 case 2: 1959 report("RDPID triggers #UD", true); 1960 vmx_inc_test_stage(); 1961 regs->rip += 4; 1962 break; 1963 } 1964 return; 1965 1966 } 1967 1968 static void disable_rdtscp_main(void) 1969 { 1970 /* Test that #UD is properly injected in L2. */ 1971 handle_exception(UD_VECTOR, disable_rdtscp_ud_handler); 1972 1973 vmx_set_test_stage(0); 1974 asm volatile("rdtscp" : : : "eax", "ecx", "edx"); 1975 vmcall(); 1976 asm volatile(".byte 0xf3, 0x0f, 0xc7, 0xf8" : : : "eax"); 1977 vmcall(); 1978 } 1979 1980 static int disable_rdtscp_exit_handler(void) 1981 { 1982 unsigned int reason = vmcs_read(EXI_REASON) & 0xff; 1983 1984 switch (reason) { 1985 case VMX_VMCALL: 1986 switch (vmx_get_test_stage()) { 1987 case 0: 1988 report("RDTSCP triggers #UD", false); 1989 vmx_inc_test_stage(); 1990 /* fallthrough */ 1991 case 1: 1992 vmx_inc_test_stage(); 1993 vmcs_write(GUEST_RIP, vmcs_read(GUEST_RIP) + 3); 1994 return VMX_TEST_RESUME; 1995 case 2: 1996 report("RDPID triggers #UD", false); 1997 break; 1998 } 1999 break; 2000 2001 default: 2002 report("Unknown exit reason, %d", false, reason); 2003 print_vmexit_info(); 2004 } 2005 return VMX_TEST_VMEXIT; 2006 } 2007 2008 int int3_init() 2009 { 2010 vmcs_write(EXC_BITMAP, ~0u); 2011 return VMX_TEST_START; 2012 } 2013 2014 void int3_guest_main() 2015 { 2016 asm volatile ("int3"); 2017 } 2018 2019 int int3_exit_handler() 2020 { 2021 u32 reason = vmcs_read(EXI_REASON); 2022 u32 intr_info = vmcs_read(EXI_INTR_INFO); 2023 2024 report("L1 intercepts #BP", reason == VMX_EXC_NMI && 2025 (intr_info & INTR_INFO_VALID_MASK) && 2026 (intr_info & INTR_INFO_VECTOR_MASK) == BP_VECTOR && 2027 ((intr_info & INTR_INFO_INTR_TYPE_MASK) >> 2028 INTR_INFO_INTR_TYPE_SHIFT) == VMX_INTR_TYPE_SOFT_EXCEPTION); 2029 2030 return VMX_TEST_VMEXIT; 2031 } 2032 2033 int into_init() 2034 { 2035 vmcs_write(EXC_BITMAP, ~0u); 2036 return VMX_TEST_START; 2037 } 2038 2039 void into_guest_main() 2040 { 2041 struct far_pointer32 fp = { 2042 .offset = (uintptr_t)&&into, 2043 .selector = KERNEL_CS32, 2044 }; 2045 register uintptr_t rsp asm("rsp"); 2046 2047 if (fp.offset != (uintptr_t)&&into) { 2048 printf("Code address too high.\n"); 2049 return; 2050 } 2051 if ((u32)rsp != rsp) { 2052 printf("Stack address too high.\n"); 2053 return; 2054 } 2055 2056 asm goto ("lcall *%0" : : "m" (fp) : "rax" : into); 2057 return; 2058 into: 2059 asm volatile (".code32;" 2060 "movl $0x7fffffff, %eax;" 2061 "addl %eax, %eax;" 2062 "into;" 2063 "lret;" 2064 ".code64"); 2065 __builtin_unreachable(); 2066 } 2067 2068 int into_exit_handler() 2069 { 2070 u32 reason = vmcs_read(EXI_REASON); 2071 u32 intr_info = vmcs_read(EXI_INTR_INFO); 2072 2073 report("L1 intercepts #OF", reason == VMX_EXC_NMI && 2074 (intr_info & INTR_INFO_VALID_MASK) && 2075 (intr_info & INTR_INFO_VECTOR_MASK) == OF_VECTOR && 2076 ((intr_info & INTR_INFO_INTR_TYPE_MASK) >> 2077 INTR_INFO_INTR_TYPE_SHIFT) == VMX_INTR_TYPE_SOFT_EXCEPTION); 2078 2079 return VMX_TEST_VMEXIT; 2080 } 2081 2082 static void exit_monitor_from_l2_main(void) 2083 { 2084 printf("Calling exit(0) from l2...\n"); 2085 exit(0); 2086 } 2087 2088 static int exit_monitor_from_l2_handler(void) 2089 { 2090 report("The guest should have killed the VMM", false); 2091 return VMX_TEST_EXIT; 2092 } 2093 2094 static void assert_exit_reason(u64 expected) 2095 { 2096 u64 actual = vmcs_read(EXI_REASON); 2097 2098 TEST_ASSERT_EQ_MSG(expected, actual, "Expected %s, got %s.", 2099 exit_reason_description(expected), 2100 exit_reason_description(actual)); 2101 } 2102 2103 static void skip_exit_vmcall() 2104 { 2105 u64 guest_rip = vmcs_read(GUEST_RIP); 2106 u32 insn_len = vmcs_read(EXI_INST_LEN); 2107 2108 assert_exit_reason(VMX_VMCALL); 2109 vmcs_write(GUEST_RIP, guest_rip + insn_len); 2110 } 2111 2112 static void v2_null_test_guest(void) 2113 { 2114 } 2115 2116 static void v2_null_test(void) 2117 { 2118 test_set_guest(v2_null_test_guest); 2119 enter_guest(); 2120 report(__func__, 1); 2121 } 2122 2123 static void v2_multiple_entries_test_guest(void) 2124 { 2125 vmx_set_test_stage(1); 2126 vmcall(); 2127 vmx_set_test_stage(2); 2128 } 2129 2130 static void v2_multiple_entries_test(void) 2131 { 2132 test_set_guest(v2_multiple_entries_test_guest); 2133 enter_guest(); 2134 TEST_ASSERT_EQ(vmx_get_test_stage(), 1); 2135 skip_exit_vmcall(); 2136 enter_guest(); 2137 TEST_ASSERT_EQ(vmx_get_test_stage(), 2); 2138 report(__func__, 1); 2139 } 2140 2141 static int fixture_test_data = 1; 2142 2143 static void fixture_test_teardown(void *data) 2144 { 2145 *((int *) data) = 1; 2146 } 2147 2148 static void fixture_test_guest(void) 2149 { 2150 fixture_test_data++; 2151 } 2152 2153 2154 static void fixture_test_setup(void) 2155 { 2156 TEST_ASSERT_EQ_MSG(1, fixture_test_data, 2157 "fixture_test_teardown didn't run?!"); 2158 fixture_test_data = 2; 2159 test_add_teardown(fixture_test_teardown, &fixture_test_data); 2160 test_set_guest(fixture_test_guest); 2161 } 2162 2163 static void fixture_test_case1(void) 2164 { 2165 fixture_test_setup(); 2166 TEST_ASSERT_EQ(2, fixture_test_data); 2167 enter_guest(); 2168 TEST_ASSERT_EQ(3, fixture_test_data); 2169 report(__func__, 1); 2170 } 2171 2172 static void fixture_test_case2(void) 2173 { 2174 fixture_test_setup(); 2175 TEST_ASSERT_EQ(2, fixture_test_data); 2176 enter_guest(); 2177 TEST_ASSERT_EQ(3, fixture_test_data); 2178 report(__func__, 1); 2179 } 2180 2181 enum ept_access_op { 2182 OP_READ, 2183 OP_WRITE, 2184 OP_EXEC, 2185 OP_FLUSH_TLB, 2186 OP_EXIT, 2187 }; 2188 2189 static struct ept_access_test_data { 2190 unsigned long gpa; 2191 unsigned long *gva; 2192 unsigned long hpa; 2193 unsigned long *hva; 2194 enum ept_access_op op; 2195 } ept_access_test_data; 2196 2197 extern unsigned char ret42_start; 2198 extern unsigned char ret42_end; 2199 2200 /* Returns 42. */ 2201 asm( 2202 ".align 64\n" 2203 "ret42_start:\n" 2204 "mov $42, %eax\n" 2205 "ret\n" 2206 "ret42_end:\n" 2207 ); 2208 2209 static void 2210 diagnose_ept_violation_qual(u64 expected, u64 actual) 2211 { 2212 2213 #define DIAGNOSE(flag) \ 2214 do { \ 2215 if ((expected & flag) != (actual & flag)) \ 2216 printf(#flag " %sexpected\n", \ 2217 (expected & flag) ? "" : "un"); \ 2218 } while (0) 2219 2220 DIAGNOSE(EPT_VLT_RD); 2221 DIAGNOSE(EPT_VLT_WR); 2222 DIAGNOSE(EPT_VLT_FETCH); 2223 DIAGNOSE(EPT_VLT_PERM_RD); 2224 DIAGNOSE(EPT_VLT_PERM_WR); 2225 DIAGNOSE(EPT_VLT_PERM_EX); 2226 DIAGNOSE(EPT_VLT_LADDR_VLD); 2227 DIAGNOSE(EPT_VLT_PADDR); 2228 2229 #undef DIAGNOSE 2230 } 2231 2232 static void do_ept_access_op(enum ept_access_op op) 2233 { 2234 ept_access_test_data.op = op; 2235 enter_guest(); 2236 } 2237 2238 /* 2239 * Force the guest to flush its TLB (i.e., flush gva -> gpa mappings). Only 2240 * needed by tests that modify guest PTEs. 2241 */ 2242 static void ept_access_test_guest_flush_tlb(void) 2243 { 2244 do_ept_access_op(OP_FLUSH_TLB); 2245 skip_exit_vmcall(); 2246 } 2247 2248 /* 2249 * Modifies the EPT entry at @level in the mapping of @gpa. First clears the 2250 * bits in @clear then sets the bits in @set. @mkhuge transforms the entry into 2251 * a huge page. 2252 */ 2253 static unsigned long ept_twiddle(unsigned long gpa, bool mkhuge, int level, 2254 unsigned long clear, unsigned long set) 2255 { 2256 struct ept_access_test_data *data = &ept_access_test_data; 2257 unsigned long orig_pte; 2258 unsigned long pte; 2259 2260 /* Screw with the mapping at the requested level. */ 2261 TEST_ASSERT(get_ept_pte(pml4, gpa, level, &orig_pte)); 2262 pte = orig_pte; 2263 if (mkhuge) 2264 pte = (orig_pte & ~EPT_ADDR_MASK) | data->hpa | EPT_LARGE_PAGE; 2265 else 2266 pte = orig_pte; 2267 pte = (pte & ~clear) | set; 2268 set_ept_pte(pml4, gpa, level, pte); 2269 ept_sync(INVEPT_SINGLE, eptp); 2270 2271 return orig_pte; 2272 } 2273 2274 static void ept_untwiddle(unsigned long gpa, int level, unsigned long orig_pte) 2275 { 2276 set_ept_pte(pml4, gpa, level, orig_pte); 2277 } 2278 2279 static void do_ept_violation(bool leaf, enum ept_access_op op, 2280 u64 expected_qual, u64 expected_paddr) 2281 { 2282 u64 qual; 2283 2284 /* Try the access and observe the violation. */ 2285 do_ept_access_op(op); 2286 2287 assert_exit_reason(VMX_EPT_VIOLATION); 2288 2289 qual = vmcs_read(EXI_QUALIFICATION); 2290 2291 diagnose_ept_violation_qual(expected_qual, qual); 2292 TEST_EXPECT_EQ(expected_qual, qual); 2293 2294 #if 0 2295 /* Disable for now otherwise every test will fail */ 2296 TEST_EXPECT_EQ(vmcs_read(GUEST_LINEAR_ADDRESS), 2297 (unsigned long) ( 2298 op == OP_EXEC ? data->gva + 1 : data->gva)); 2299 #endif 2300 /* 2301 * TODO: tests that probe expected_paddr in pages other than the one at 2302 * the beginning of the 1g region. 2303 */ 2304 TEST_EXPECT_EQ(vmcs_read(INFO_PHYS_ADDR), expected_paddr); 2305 } 2306 2307 static void 2308 ept_violation_at_level_mkhuge(bool mkhuge, int level, unsigned long clear, 2309 unsigned long set, enum ept_access_op op, 2310 u64 expected_qual) 2311 { 2312 struct ept_access_test_data *data = &ept_access_test_data; 2313 unsigned long orig_pte; 2314 2315 orig_pte = ept_twiddle(data->gpa, mkhuge, level, clear, set); 2316 2317 do_ept_violation(level == 1 || mkhuge, op, expected_qual, 2318 op == OP_EXEC ? data->gpa + sizeof(unsigned long) : 2319 data->gpa); 2320 2321 /* Fix the violation and resume the op loop. */ 2322 ept_untwiddle(data->gpa, level, orig_pte); 2323 enter_guest(); 2324 skip_exit_vmcall(); 2325 } 2326 2327 static void 2328 ept_violation_at_level(int level, unsigned long clear, unsigned long set, 2329 enum ept_access_op op, u64 expected_qual) 2330 { 2331 ept_violation_at_level_mkhuge(false, level, clear, set, op, 2332 expected_qual); 2333 if (ept_huge_pages_supported(level)) 2334 ept_violation_at_level_mkhuge(true, level, clear, set, op, 2335 expected_qual); 2336 } 2337 2338 static void ept_violation(unsigned long clear, unsigned long set, 2339 enum ept_access_op op, u64 expected_qual) 2340 { 2341 ept_violation_at_level(1, clear, set, op, expected_qual); 2342 ept_violation_at_level(2, clear, set, op, expected_qual); 2343 ept_violation_at_level(3, clear, set, op, expected_qual); 2344 ept_violation_at_level(4, clear, set, op, expected_qual); 2345 } 2346 2347 static void ept_access_violation(unsigned long access, enum ept_access_op op, 2348 u64 expected_qual) 2349 { 2350 ept_violation(EPT_PRESENT, access, op, 2351 expected_qual | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2352 } 2353 2354 /* 2355 * For translations that don't involve a GVA, that is physical address (paddr) 2356 * accesses, EPT violations don't set the flag EPT_VLT_PADDR. For a typical 2357 * guest memory access, the hardware does GVA -> GPA -> HPA. However, certain 2358 * translations don't involve GVAs, such as when the hardware does the guest 2359 * page table walk. For example, in translating GVA_1 -> GPA_1, the guest MMU 2360 * might try to set an A bit on a guest PTE. If the GPA_2 that the PTE resides 2361 * on isn't present in the EPT, then the EPT violation will be for GPA_2 and 2362 * the EPT_VLT_PADDR bit will be clear in the exit qualification. 2363 * 2364 * Note that paddr violations can also be triggered by loading PAE page tables 2365 * with wonky addresses. We don't test that yet. 2366 * 2367 * This function modifies the EPT entry that maps the GPA that the guest page 2368 * table entry mapping ept_access_data.gva resides on. 2369 * 2370 * @ept_access EPT permissions to set. Other permissions are cleared. 2371 * 2372 * @pte_ad Set the A/D bits on the guest PTE accordingly. 2373 * 2374 * @op Guest operation to perform with ept_access_data.gva. 2375 * 2376 * @expect_violation 2377 * Is a violation expected during the paddr access? 2378 * 2379 * @expected_qual Expected qualification for the EPT violation. 2380 * EPT_VLT_PADDR should be clear. 2381 */ 2382 static void ept_access_paddr(unsigned long ept_access, unsigned long pte_ad, 2383 enum ept_access_op op, bool expect_violation, 2384 u64 expected_qual) 2385 { 2386 struct ept_access_test_data *data = &ept_access_test_data; 2387 unsigned long *ptep; 2388 unsigned long gpa; 2389 unsigned long orig_epte; 2390 2391 /* Modify the guest PTE mapping data->gva according to @pte_ad. */ 2392 ptep = get_pte_level(current_page_table(), data->gva, /*level=*/1); 2393 TEST_ASSERT(ptep); 2394 TEST_ASSERT_EQ(*ptep & PT_ADDR_MASK, data->gpa); 2395 *ptep = (*ptep & ~PT_AD_MASK) | pte_ad; 2396 ept_access_test_guest_flush_tlb(); 2397 2398 /* 2399 * Now modify the access bits on the EPT entry for the GPA that the 2400 * guest PTE resides on. Note that by modifying a single EPT entry, 2401 * we're potentially affecting 512 guest PTEs. However, we've carefully 2402 * constructed our test such that those other 511 PTEs aren't used by 2403 * the guest: data->gva is at the beginning of a 1G huge page, thus the 2404 * PTE we're modifying is at the beginning of a 4K page and the 2405 * following 511 entires are also under our control (and not touched by 2406 * the guest). 2407 */ 2408 gpa = virt_to_phys(ptep); 2409 TEST_ASSERT_EQ(gpa & ~PAGE_MASK, 0); 2410 /* 2411 * Make sure the guest page table page is mapped with a 4K EPT entry, 2412 * otherwise our level=1 twiddling below will fail. We use the 2413 * identity map (gpa = gpa) since page tables are shared with the host. 2414 */ 2415 install_ept(pml4, gpa, gpa, EPT_PRESENT); 2416 orig_epte = ept_twiddle(gpa, /*mkhuge=*/0, /*level=*/1, 2417 /*clear=*/EPT_PRESENT, /*set=*/ept_access); 2418 2419 if (expect_violation) { 2420 do_ept_violation(/*leaf=*/true, op, 2421 expected_qual | EPT_VLT_LADDR_VLD, gpa); 2422 ept_untwiddle(gpa, /*level=*/1, orig_epte); 2423 do_ept_access_op(op); 2424 } else { 2425 do_ept_access_op(op); 2426 ept_untwiddle(gpa, /*level=*/1, orig_epte); 2427 } 2428 2429 TEST_ASSERT(*ptep & PT_ACCESSED_MASK); 2430 if ((pte_ad & PT_DIRTY_MASK) || op == OP_WRITE) 2431 TEST_ASSERT(*ptep & PT_DIRTY_MASK); 2432 2433 skip_exit_vmcall(); 2434 } 2435 2436 static void ept_access_allowed_paddr(unsigned long ept_access, 2437 unsigned long pte_ad, 2438 enum ept_access_op op) 2439 { 2440 ept_access_paddr(ept_access, pte_ad, op, /*expect_violation=*/false, 2441 /*expected_qual=*/-1); 2442 } 2443 2444 static void ept_access_violation_paddr(unsigned long ept_access, 2445 unsigned long pte_ad, 2446 enum ept_access_op op, 2447 u64 expected_qual) 2448 { 2449 ept_access_paddr(ept_access, pte_ad, op, /*expect_violation=*/true, 2450 expected_qual); 2451 } 2452 2453 2454 static void ept_allowed_at_level_mkhuge(bool mkhuge, int level, 2455 unsigned long clear, 2456 unsigned long set, 2457 enum ept_access_op op) 2458 { 2459 struct ept_access_test_data *data = &ept_access_test_data; 2460 unsigned long orig_pte; 2461 2462 orig_pte = ept_twiddle(data->gpa, mkhuge, level, clear, set); 2463 2464 /* No violation. Should proceed to vmcall. */ 2465 do_ept_access_op(op); 2466 skip_exit_vmcall(); 2467 2468 ept_untwiddle(data->gpa, level, orig_pte); 2469 } 2470 2471 static void ept_allowed_at_level(int level, unsigned long clear, 2472 unsigned long set, enum ept_access_op op) 2473 { 2474 ept_allowed_at_level_mkhuge(false, level, clear, set, op); 2475 if (ept_huge_pages_supported(level)) 2476 ept_allowed_at_level_mkhuge(true, level, clear, set, op); 2477 } 2478 2479 static void ept_allowed(unsigned long clear, unsigned long set, 2480 enum ept_access_op op) 2481 { 2482 ept_allowed_at_level(1, clear, set, op); 2483 ept_allowed_at_level(2, clear, set, op); 2484 ept_allowed_at_level(3, clear, set, op); 2485 ept_allowed_at_level(4, clear, set, op); 2486 } 2487 2488 static void ept_ignored_bit(int bit) 2489 { 2490 /* Set the bit. */ 2491 ept_allowed(0, 1ul << bit, OP_READ); 2492 ept_allowed(0, 1ul << bit, OP_WRITE); 2493 ept_allowed(0, 1ul << bit, OP_EXEC); 2494 2495 /* Clear the bit. */ 2496 ept_allowed(1ul << bit, 0, OP_READ); 2497 ept_allowed(1ul << bit, 0, OP_WRITE); 2498 ept_allowed(1ul << bit, 0, OP_EXEC); 2499 } 2500 2501 static void ept_access_allowed(unsigned long access, enum ept_access_op op) 2502 { 2503 ept_allowed(EPT_PRESENT, access, op); 2504 } 2505 2506 2507 static void ept_misconfig_at_level_mkhuge_op(bool mkhuge, int level, 2508 unsigned long clear, 2509 unsigned long set, 2510 enum ept_access_op op) 2511 { 2512 struct ept_access_test_data *data = &ept_access_test_data; 2513 unsigned long orig_pte; 2514 2515 orig_pte = ept_twiddle(data->gpa, mkhuge, level, clear, set); 2516 2517 do_ept_access_op(op); 2518 assert_exit_reason(VMX_EPT_MISCONFIG); 2519 2520 /* Intel 27.2.1, "For all other VM exits, this field is cleared." */ 2521 #if 0 2522 /* broken: */ 2523 TEST_EXPECT_EQ_MSG(vmcs_read(EXI_QUALIFICATION), 0); 2524 #endif 2525 #if 0 2526 /* 2527 * broken: 2528 * According to description of exit qual for EPT violation, 2529 * EPT_VLT_LADDR_VLD indicates if GUEST_LINEAR_ADDRESS is valid. 2530 * However, I can't find anything that says GUEST_LINEAR_ADDRESS ought 2531 * to be set for msiconfig. 2532 */ 2533 TEST_EXPECT_EQ(vmcs_read(GUEST_LINEAR_ADDRESS), 2534 (unsigned long) ( 2535 op == OP_EXEC ? data->gva + 1 : data->gva)); 2536 #endif 2537 2538 /* Fix the violation and resume the op loop. */ 2539 ept_untwiddle(data->gpa, level, orig_pte); 2540 enter_guest(); 2541 skip_exit_vmcall(); 2542 } 2543 2544 static void ept_misconfig_at_level_mkhuge(bool mkhuge, int level, 2545 unsigned long clear, 2546 unsigned long set) 2547 { 2548 /* The op shouldn't matter (read, write, exec), so try them all! */ 2549 ept_misconfig_at_level_mkhuge_op(mkhuge, level, clear, set, OP_READ); 2550 ept_misconfig_at_level_mkhuge_op(mkhuge, level, clear, set, OP_WRITE); 2551 ept_misconfig_at_level_mkhuge_op(mkhuge, level, clear, set, OP_EXEC); 2552 } 2553 2554 static void ept_misconfig_at_level(int level, unsigned long clear, 2555 unsigned long set) 2556 { 2557 ept_misconfig_at_level_mkhuge(false, level, clear, set); 2558 if (ept_huge_pages_supported(level)) 2559 ept_misconfig_at_level_mkhuge(true, level, clear, set); 2560 } 2561 2562 static void ept_misconfig(unsigned long clear, unsigned long set) 2563 { 2564 ept_misconfig_at_level(1, clear, set); 2565 ept_misconfig_at_level(2, clear, set); 2566 ept_misconfig_at_level(3, clear, set); 2567 ept_misconfig_at_level(4, clear, set); 2568 } 2569 2570 static void ept_access_misconfig(unsigned long access) 2571 { 2572 ept_misconfig(EPT_PRESENT, access); 2573 } 2574 2575 static void ept_reserved_bit_at_level_nohuge(int level, int bit) 2576 { 2577 /* Setting the bit causes a misconfig. */ 2578 ept_misconfig_at_level_mkhuge(false, level, 0, 1ul << bit); 2579 2580 /* Making the entry non-present turns reserved bits into ignored. */ 2581 ept_violation_at_level(level, EPT_PRESENT, 1ul << bit, OP_READ, 2582 EPT_VLT_RD | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2583 } 2584 2585 static void ept_reserved_bit_at_level_huge(int level, int bit) 2586 { 2587 /* Setting the bit causes a misconfig. */ 2588 ept_misconfig_at_level_mkhuge(true, level, 0, 1ul << bit); 2589 2590 /* Making the entry non-present turns reserved bits into ignored. */ 2591 ept_violation_at_level(level, EPT_PRESENT, 1ul << bit, OP_READ, 2592 EPT_VLT_RD | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2593 } 2594 2595 static void ept_reserved_bit_at_level(int level, int bit) 2596 { 2597 /* Setting the bit causes a misconfig. */ 2598 ept_misconfig_at_level(level, 0, 1ul << bit); 2599 2600 /* Making the entry non-present turns reserved bits into ignored. */ 2601 ept_violation_at_level(level, EPT_PRESENT, 1ul << bit, OP_READ, 2602 EPT_VLT_RD | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2603 } 2604 2605 static void ept_reserved_bit(int bit) 2606 { 2607 ept_reserved_bit_at_level(1, bit); 2608 ept_reserved_bit_at_level(2, bit); 2609 ept_reserved_bit_at_level(3, bit); 2610 ept_reserved_bit_at_level(4, bit); 2611 } 2612 2613 #define PAGE_2M_ORDER 9 2614 #define PAGE_1G_ORDER 18 2615 2616 static void *get_1g_page(void) 2617 { 2618 static void *alloc; 2619 2620 if (!alloc) 2621 alloc = alloc_pages(PAGE_1G_ORDER); 2622 return alloc; 2623 } 2624 2625 static void ept_access_test_teardown(void *unused) 2626 { 2627 /* Exit the guest cleanly. */ 2628 do_ept_access_op(OP_EXIT); 2629 } 2630 2631 static void ept_access_test_guest(void) 2632 { 2633 struct ept_access_test_data *data = &ept_access_test_data; 2634 int (*code)(void) = (int (*)(void)) &data->gva[1]; 2635 2636 while (true) { 2637 switch (data->op) { 2638 case OP_READ: 2639 TEST_ASSERT_EQ(*data->gva, MAGIC_VAL_1); 2640 break; 2641 case OP_WRITE: 2642 *data->gva = MAGIC_VAL_2; 2643 TEST_ASSERT_EQ(*data->gva, MAGIC_VAL_2); 2644 *data->gva = MAGIC_VAL_1; 2645 break; 2646 case OP_EXEC: 2647 TEST_ASSERT_EQ(42, code()); 2648 break; 2649 case OP_FLUSH_TLB: 2650 write_cr3(read_cr3()); 2651 break; 2652 case OP_EXIT: 2653 return; 2654 default: 2655 TEST_ASSERT_MSG(false, "Unknown op %d", data->op); 2656 } 2657 vmcall(); 2658 } 2659 } 2660 2661 static void ept_access_test_setup(void) 2662 { 2663 struct ept_access_test_data *data = &ept_access_test_data; 2664 unsigned long npages = 1ul << PAGE_1G_ORDER; 2665 unsigned long size = npages * PAGE_SIZE; 2666 unsigned long *page_table = current_page_table(); 2667 unsigned long pte; 2668 2669 if (setup_ept(false)) 2670 test_skip("EPT not supported"); 2671 2672 /* We use data->gpa = 1 << 39 so that test data has a separate pml4 entry */ 2673 if (cpuid_maxphyaddr() < 40) 2674 test_skip("Test needs MAXPHYADDR >= 40"); 2675 2676 test_set_guest(ept_access_test_guest); 2677 test_add_teardown(ept_access_test_teardown, NULL); 2678 2679 data->hva = get_1g_page(); 2680 TEST_ASSERT(data->hva); 2681 data->hpa = virt_to_phys(data->hva); 2682 2683 data->gpa = 1ul << 39; 2684 data->gva = (void *) ALIGN((unsigned long) alloc_vpages(npages * 2), 2685 size); 2686 TEST_ASSERT(!any_present_pages(page_table, data->gva, size)); 2687 install_pages(page_table, data->gpa, size, data->gva); 2688 2689 /* 2690 * Make sure nothing's mapped here so the tests that screw with the 2691 * pml4 entry don't inadvertently break something. 2692 */ 2693 TEST_ASSERT(get_ept_pte(pml4, data->gpa, 4, &pte) && pte == 0); 2694 TEST_ASSERT(get_ept_pte(pml4, data->gpa + size - 1, 4, &pte) && pte == 0); 2695 install_ept(pml4, data->hpa, data->gpa, EPT_PRESENT); 2696 2697 data->hva[0] = MAGIC_VAL_1; 2698 memcpy(&data->hva[1], &ret42_start, &ret42_end - &ret42_start); 2699 } 2700 2701 static void ept_access_test_not_present(void) 2702 { 2703 ept_access_test_setup(); 2704 /* --- */ 2705 ept_access_violation(0, OP_READ, EPT_VLT_RD); 2706 ept_access_violation(0, OP_WRITE, EPT_VLT_WR); 2707 ept_access_violation(0, OP_EXEC, EPT_VLT_FETCH); 2708 } 2709 2710 static void ept_access_test_read_only(void) 2711 { 2712 ept_access_test_setup(); 2713 2714 /* r-- */ 2715 ept_access_allowed(EPT_RA, OP_READ); 2716 ept_access_violation(EPT_RA, OP_WRITE, EPT_VLT_WR | EPT_VLT_PERM_RD); 2717 ept_access_violation(EPT_RA, OP_EXEC, EPT_VLT_FETCH | EPT_VLT_PERM_RD); 2718 } 2719 2720 static void ept_access_test_write_only(void) 2721 { 2722 ept_access_test_setup(); 2723 /* -w- */ 2724 ept_access_misconfig(EPT_WA); 2725 } 2726 2727 static void ept_access_test_read_write(void) 2728 { 2729 ept_access_test_setup(); 2730 /* rw- */ 2731 ept_access_allowed(EPT_RA | EPT_WA, OP_READ); 2732 ept_access_allowed(EPT_RA | EPT_WA, OP_WRITE); 2733 ept_access_violation(EPT_RA | EPT_WA, OP_EXEC, 2734 EPT_VLT_FETCH | EPT_VLT_PERM_RD | EPT_VLT_PERM_WR); 2735 } 2736 2737 2738 static void ept_access_test_execute_only(void) 2739 { 2740 ept_access_test_setup(); 2741 /* --x */ 2742 if (ept_execute_only_supported()) { 2743 ept_access_violation(EPT_EA, OP_READ, 2744 EPT_VLT_RD | EPT_VLT_PERM_EX); 2745 ept_access_violation(EPT_EA, OP_WRITE, 2746 EPT_VLT_WR | EPT_VLT_PERM_EX); 2747 ept_access_allowed(EPT_EA, OP_EXEC); 2748 } else { 2749 ept_access_misconfig(EPT_EA); 2750 } 2751 } 2752 2753 static void ept_access_test_read_execute(void) 2754 { 2755 ept_access_test_setup(); 2756 /* r-x */ 2757 ept_access_allowed(EPT_RA | EPT_EA, OP_READ); 2758 ept_access_violation(EPT_RA | EPT_EA, OP_WRITE, 2759 EPT_VLT_WR | EPT_VLT_PERM_RD | EPT_VLT_PERM_EX); 2760 ept_access_allowed(EPT_RA | EPT_EA, OP_EXEC); 2761 } 2762 2763 static void ept_access_test_write_execute(void) 2764 { 2765 ept_access_test_setup(); 2766 /* -wx */ 2767 ept_access_misconfig(EPT_WA | EPT_EA); 2768 } 2769 2770 static void ept_access_test_read_write_execute(void) 2771 { 2772 ept_access_test_setup(); 2773 /* rwx */ 2774 ept_access_allowed(EPT_RA | EPT_WA | EPT_EA, OP_READ); 2775 ept_access_allowed(EPT_RA | EPT_WA | EPT_EA, OP_WRITE); 2776 ept_access_allowed(EPT_RA | EPT_WA | EPT_EA, OP_EXEC); 2777 } 2778 2779 static void ept_access_test_reserved_bits(void) 2780 { 2781 int i; 2782 int maxphyaddr; 2783 2784 ept_access_test_setup(); 2785 2786 /* Reserved bits above maxphyaddr. */ 2787 maxphyaddr = cpuid_maxphyaddr(); 2788 for (i = maxphyaddr; i <= 51; i++) { 2789 report_prefix_pushf("reserved_bit=%d", i); 2790 ept_reserved_bit(i); 2791 report_prefix_pop(); 2792 } 2793 2794 /* Level-specific reserved bits. */ 2795 ept_reserved_bit_at_level_nohuge(2, 3); 2796 ept_reserved_bit_at_level_nohuge(2, 4); 2797 ept_reserved_bit_at_level_nohuge(2, 5); 2798 ept_reserved_bit_at_level_nohuge(2, 6); 2799 /* 2M alignment. */ 2800 for (i = 12; i < 20; i++) { 2801 report_prefix_pushf("reserved_bit=%d", i); 2802 ept_reserved_bit_at_level_huge(2, i); 2803 report_prefix_pop(); 2804 } 2805 ept_reserved_bit_at_level_nohuge(3, 3); 2806 ept_reserved_bit_at_level_nohuge(3, 4); 2807 ept_reserved_bit_at_level_nohuge(3, 5); 2808 ept_reserved_bit_at_level_nohuge(3, 6); 2809 /* 1G alignment. */ 2810 for (i = 12; i < 29; i++) { 2811 report_prefix_pushf("reserved_bit=%d", i); 2812 ept_reserved_bit_at_level_huge(3, i); 2813 report_prefix_pop(); 2814 } 2815 ept_reserved_bit_at_level(4, 3); 2816 ept_reserved_bit_at_level(4, 4); 2817 ept_reserved_bit_at_level(4, 5); 2818 ept_reserved_bit_at_level(4, 6); 2819 ept_reserved_bit_at_level(4, 7); 2820 } 2821 2822 static void ept_access_test_ignored_bits(void) 2823 { 2824 ept_access_test_setup(); 2825 /* 2826 * Bits ignored at every level. Bits 8 and 9 (A and D) are ignored as 2827 * far as translation is concerned even if AD bits are enabled in the 2828 * EPTP. Bit 63 is ignored because "EPT-violation #VE" VM-execution 2829 * control is 0. 2830 */ 2831 ept_ignored_bit(8); 2832 ept_ignored_bit(9); 2833 ept_ignored_bit(10); 2834 ept_ignored_bit(11); 2835 ept_ignored_bit(52); 2836 ept_ignored_bit(53); 2837 ept_ignored_bit(54); 2838 ept_ignored_bit(55); 2839 ept_ignored_bit(56); 2840 ept_ignored_bit(57); 2841 ept_ignored_bit(58); 2842 ept_ignored_bit(59); 2843 ept_ignored_bit(60); 2844 ept_ignored_bit(61); 2845 ept_ignored_bit(62); 2846 ept_ignored_bit(63); 2847 } 2848 2849 static void ept_access_test_paddr_not_present_ad_disabled(void) 2850 { 2851 ept_access_test_setup(); 2852 ept_disable_ad_bits(); 2853 2854 ept_access_violation_paddr(0, PT_AD_MASK, OP_READ, EPT_VLT_RD); 2855 ept_access_violation_paddr(0, PT_AD_MASK, OP_WRITE, EPT_VLT_RD); 2856 ept_access_violation_paddr(0, PT_AD_MASK, OP_EXEC, EPT_VLT_RD); 2857 } 2858 2859 static void ept_access_test_paddr_not_present_ad_enabled(void) 2860 { 2861 u64 qual = EPT_VLT_RD | EPT_VLT_WR; 2862 2863 ept_access_test_setup(); 2864 ept_enable_ad_bits_or_skip_test(); 2865 2866 ept_access_violation_paddr(0, PT_AD_MASK, OP_READ, qual); 2867 ept_access_violation_paddr(0, PT_AD_MASK, OP_WRITE, qual); 2868 ept_access_violation_paddr(0, PT_AD_MASK, OP_EXEC, qual); 2869 } 2870 2871 static void ept_access_test_paddr_read_only_ad_disabled(void) 2872 { 2873 /* 2874 * When EPT AD bits are disabled, all accesses to guest paging 2875 * structures are reported separately as a read and (after 2876 * translation of the GPA to host physical address) a read+write 2877 * if the A/D bits have to be set. 2878 */ 2879 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD; 2880 2881 ept_access_test_setup(); 2882 ept_disable_ad_bits(); 2883 2884 /* Can't update A bit, so all accesses fail. */ 2885 ept_access_violation_paddr(EPT_RA, 0, OP_READ, qual); 2886 ept_access_violation_paddr(EPT_RA, 0, OP_WRITE, qual); 2887 ept_access_violation_paddr(EPT_RA, 0, OP_EXEC, qual); 2888 /* AD bits disabled, so only writes try to update the D bit. */ 2889 ept_access_allowed_paddr(EPT_RA, PT_ACCESSED_MASK, OP_READ); 2890 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_WRITE, qual); 2891 ept_access_allowed_paddr(EPT_RA, PT_ACCESSED_MASK, OP_EXEC); 2892 /* Both A and D already set, so read-only is OK. */ 2893 ept_access_allowed_paddr(EPT_RA, PT_AD_MASK, OP_READ); 2894 ept_access_allowed_paddr(EPT_RA, PT_AD_MASK, OP_WRITE); 2895 ept_access_allowed_paddr(EPT_RA, PT_AD_MASK, OP_EXEC); 2896 } 2897 2898 static void ept_access_test_paddr_read_only_ad_enabled(void) 2899 { 2900 /* 2901 * When EPT AD bits are enabled, all accesses to guest paging 2902 * structures are considered writes as far as EPT translation 2903 * is concerned. 2904 */ 2905 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD; 2906 2907 ept_access_test_setup(); 2908 ept_enable_ad_bits_or_skip_test(); 2909 2910 ept_access_violation_paddr(EPT_RA, 0, OP_READ, qual); 2911 ept_access_violation_paddr(EPT_RA, 0, OP_WRITE, qual); 2912 ept_access_violation_paddr(EPT_RA, 0, OP_EXEC, qual); 2913 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_READ, qual); 2914 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_WRITE, qual); 2915 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_EXEC, qual); 2916 ept_access_violation_paddr(EPT_RA, PT_AD_MASK, OP_READ, qual); 2917 ept_access_violation_paddr(EPT_RA, PT_AD_MASK, OP_WRITE, qual); 2918 ept_access_violation_paddr(EPT_RA, PT_AD_MASK, OP_EXEC, qual); 2919 } 2920 2921 static void ept_access_test_paddr_read_write(void) 2922 { 2923 ept_access_test_setup(); 2924 /* Read-write access to paging structure. */ 2925 ept_access_allowed_paddr(EPT_RA | EPT_WA, 0, OP_READ); 2926 ept_access_allowed_paddr(EPT_RA | EPT_WA, 0, OP_WRITE); 2927 ept_access_allowed_paddr(EPT_RA | EPT_WA, 0, OP_EXEC); 2928 } 2929 2930 static void ept_access_test_paddr_read_write_execute(void) 2931 { 2932 ept_access_test_setup(); 2933 /* RWX access to paging structure. */ 2934 ept_access_allowed_paddr(EPT_PRESENT, 0, OP_READ); 2935 ept_access_allowed_paddr(EPT_PRESENT, 0, OP_WRITE); 2936 ept_access_allowed_paddr(EPT_PRESENT, 0, OP_EXEC); 2937 } 2938 2939 static void ept_access_test_paddr_read_execute_ad_disabled(void) 2940 { 2941 /* 2942 * When EPT AD bits are disabled, all accesses to guest paging 2943 * structures are reported separately as a read and (after 2944 * translation of the GPA to host physical address) a read+write 2945 * if the A/D bits have to be set. 2946 */ 2947 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD | EPT_VLT_PERM_EX; 2948 2949 ept_access_test_setup(); 2950 ept_disable_ad_bits(); 2951 2952 /* Can't update A bit, so all accesses fail. */ 2953 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_READ, qual); 2954 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_WRITE, qual); 2955 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_EXEC, qual); 2956 /* AD bits disabled, so only writes try to update the D bit. */ 2957 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_READ); 2958 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_WRITE, qual); 2959 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_EXEC); 2960 /* Both A and D already set, so read-only is OK. */ 2961 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_READ); 2962 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_WRITE); 2963 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_EXEC); 2964 } 2965 2966 static void ept_access_test_paddr_read_execute_ad_enabled(void) 2967 { 2968 /* 2969 * When EPT AD bits are enabled, all accesses to guest paging 2970 * structures are considered writes as far as EPT translation 2971 * is concerned. 2972 */ 2973 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD | EPT_VLT_PERM_EX; 2974 2975 ept_access_test_setup(); 2976 ept_enable_ad_bits_or_skip_test(); 2977 2978 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_READ, qual); 2979 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_WRITE, qual); 2980 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_EXEC, qual); 2981 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_READ, qual); 2982 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_WRITE, qual); 2983 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_EXEC, qual); 2984 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_READ, qual); 2985 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_WRITE, qual); 2986 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_EXEC, qual); 2987 } 2988 2989 static void ept_access_test_paddr_not_present_page_fault(void) 2990 { 2991 ept_access_test_setup(); 2992 /* 2993 * TODO: test no EPT violation as long as guest PF occurs. e.g., GPA is 2994 * page is read-only in EPT but GVA is also mapped read only in PT. 2995 * Thus guest page fault before host takes EPT violation for trying to 2996 * update A bit. 2997 */ 2998 } 2999 3000 static void ept_access_test_force_2m_page(void) 3001 { 3002 ept_access_test_setup(); 3003 3004 TEST_ASSERT_EQ(ept_2m_supported(), true); 3005 ept_allowed_at_level_mkhuge(true, 2, 0, 0, OP_READ); 3006 ept_violation_at_level_mkhuge(true, 2, EPT_PRESENT, EPT_RA, OP_WRITE, 3007 EPT_VLT_WR | EPT_VLT_PERM_RD | 3008 EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 3009 ept_misconfig_at_level_mkhuge(true, 2, EPT_PRESENT, EPT_WA); 3010 } 3011 3012 static bool invvpid_valid(u64 type, u64 vpid, u64 gla) 3013 { 3014 u64 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 3015 3016 TEST_ASSERT(msr & VPID_CAP_INVVPID); 3017 3018 if (type < INVVPID_ADDR || type > INVVPID_CONTEXT_LOCAL) 3019 return false; 3020 3021 if (!(msr & (1ull << (type + VPID_CAP_INVVPID_TYPES_SHIFT)))) 3022 return false; 3023 3024 if (vpid >> 16) 3025 return false; 3026 3027 if (type != INVVPID_ALL && !vpid) 3028 return false; 3029 3030 if (type == INVVPID_ADDR && !is_canonical(gla)) 3031 return false; 3032 3033 return true; 3034 } 3035 3036 static void try_invvpid(u64 type, u64 vpid, u64 gla) 3037 { 3038 int rc; 3039 bool valid = invvpid_valid(type, vpid, gla); 3040 u64 expected = valid ? VMXERR_UNSUPPORTED_VMCS_COMPONENT 3041 : VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID; 3042 /* 3043 * Set VMX_INST_ERROR to VMXERR_UNVALID_VMCS_COMPONENT, so 3044 * that we can tell if it is updated by INVVPID. 3045 */ 3046 vmcs_read(~0); 3047 rc = invvpid(type, vpid, gla); 3048 report("INVVPID type %ld VPID %lx GLA %lx %s", 3049 !rc == valid, type, vpid, gla, 3050 valid ? "passes" : "fails"); 3051 report("After %s INVVPID, VMX_INST_ERR is %ld (actual %ld)", 3052 vmcs_read(VMX_INST_ERROR) == expected, 3053 rc ? "failed" : "successful", 3054 expected, vmcs_read(VMX_INST_ERROR)); 3055 } 3056 3057 static void ds_invvpid(void *data) 3058 { 3059 u64 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 3060 u64 type = ffs(msr >> VPID_CAP_INVVPID_TYPES_SHIFT) - 1; 3061 3062 TEST_ASSERT(type >= INVVPID_ADDR && type <= INVVPID_CONTEXT_LOCAL); 3063 asm volatile("invvpid %0, %1" 3064 : 3065 : "m"(*(struct invvpid_operand *)data), 3066 "r"(type)); 3067 } 3068 3069 /* 3070 * The SS override is ignored in 64-bit mode, so we use an addressing 3071 * mode with %rsp as the base register to generate an implicit SS 3072 * reference. 3073 */ 3074 static void ss_invvpid(void *data) 3075 { 3076 u64 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 3077 u64 type = ffs(msr >> VPID_CAP_INVVPID_TYPES_SHIFT) - 1; 3078 3079 TEST_ASSERT(type >= INVVPID_ADDR && type <= INVVPID_CONTEXT_LOCAL); 3080 asm volatile("sub %%rsp,%0; invvpid (%%rsp,%0,1), %1" 3081 : "+r"(data) 3082 : "r"(type)); 3083 } 3084 3085 static void invvpid_test_gp(void) 3086 { 3087 bool fault; 3088 3089 fault = test_for_exception(GP_VECTOR, &ds_invvpid, 3090 (void *)NONCANONICAL); 3091 report("INVVPID with non-canonical DS operand raises #GP", fault); 3092 } 3093 3094 static void invvpid_test_ss(void) 3095 { 3096 bool fault; 3097 3098 fault = test_for_exception(SS_VECTOR, &ss_invvpid, 3099 (void *)NONCANONICAL); 3100 report("INVVPID with non-canonical SS operand raises #SS", fault); 3101 } 3102 3103 static void invvpid_test_pf(void) 3104 { 3105 void *vpage = alloc_vpage(); 3106 bool fault; 3107 3108 fault = test_for_exception(PF_VECTOR, &ds_invvpid, vpage); 3109 report("INVVPID with unmapped operand raises #PF", fault); 3110 } 3111 3112 static void try_compat_invvpid(void *unused) 3113 { 3114 struct far_pointer32 fp = { 3115 .offset = (uintptr_t)&&invvpid, 3116 .selector = KERNEL_CS32, 3117 }; 3118 register uintptr_t rsp asm("rsp"); 3119 3120 TEST_ASSERT_MSG(fp.offset == (uintptr_t)&&invvpid, 3121 "Code address too high."); 3122 TEST_ASSERT_MSG(rsp == (u32)rsp, "Stack address too high."); 3123 3124 asm goto ("lcall *%0" : : "m" (fp) : "rax" : invvpid); 3125 return; 3126 invvpid: 3127 asm volatile (".code32;" 3128 "invvpid (%eax), %eax;" 3129 "lret;" 3130 ".code64"); 3131 __builtin_unreachable(); 3132 } 3133 3134 static void invvpid_test_compatibility_mode(void) 3135 { 3136 bool fault; 3137 3138 fault = test_for_exception(UD_VECTOR, &try_compat_invvpid, NULL); 3139 report("Compatibility mode INVVPID raises #UD", fault); 3140 } 3141 3142 static void invvpid_test_not_in_vmx_operation(void) 3143 { 3144 bool fault; 3145 3146 TEST_ASSERT(!vmx_off()); 3147 fault = test_for_exception(UD_VECTOR, &ds_invvpid, NULL); 3148 report("INVVPID outside of VMX operation raises #UD", fault); 3149 TEST_ASSERT(!vmx_on()); 3150 } 3151 3152 /* 3153 * This does not test real-address mode, virtual-8086 mode, protected mode, 3154 * or CPL > 0. 3155 */ 3156 static void invvpid_test_v2(void) 3157 { 3158 u64 msr; 3159 int i; 3160 unsigned types = 0; 3161 unsigned type; 3162 3163 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 3164 !(ctrl_cpu_rev[1].clr & CPU_VPID)) 3165 test_skip("VPID not supported"); 3166 3167 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 3168 3169 if (!(msr & VPID_CAP_INVVPID)) 3170 test_skip("INVVPID not supported.\n"); 3171 3172 if (msr & VPID_CAP_INVVPID_ADDR) 3173 types |= 1u << INVVPID_ADDR; 3174 if (msr & VPID_CAP_INVVPID_CXTGLB) 3175 types |= 1u << INVVPID_CONTEXT_GLOBAL; 3176 if (msr & VPID_CAP_INVVPID_ALL) 3177 types |= 1u << INVVPID_ALL; 3178 if (msr & VPID_CAP_INVVPID_CXTLOC) 3179 types |= 1u << INVVPID_CONTEXT_LOCAL; 3180 3181 if (!types) 3182 test_skip("No INVVPID types supported.\n"); 3183 3184 for (i = -127; i < 128; i++) 3185 try_invvpid(i, 0xffff, 0); 3186 3187 /* 3188 * VPID must not be more than 16 bits. 3189 */ 3190 for (i = 0; i < 64; i++) 3191 for (type = 0; type < 4; type++) 3192 if (types & (1u << type)) 3193 try_invvpid(type, 1ul << i, 0); 3194 3195 /* 3196 * VPID must not be zero, except for "all contexts." 3197 */ 3198 for (type = 0; type < 4; type++) 3199 if (types & (1u << type)) 3200 try_invvpid(type, 0, 0); 3201 3202 /* 3203 * The gla operand is only validated for single-address INVVPID. 3204 */ 3205 if (types & (1u << INVVPID_ADDR)) 3206 try_invvpid(INVVPID_ADDR, 0xffff, NONCANONICAL); 3207 3208 invvpid_test_gp(); 3209 invvpid_test_ss(); 3210 invvpid_test_pf(); 3211 invvpid_test_compatibility_mode(); 3212 invvpid_test_not_in_vmx_operation(); 3213 } 3214 3215 /* 3216 * Test for early VMLAUNCH failure. Returns true if VMLAUNCH makes it 3217 * at least as far as the guest-state checks. Returns false if the 3218 * VMLAUNCH fails early and execution falls through to the next 3219 * instruction. 3220 */ 3221 static bool vmlaunch_succeeds(void) 3222 { 3223 /* 3224 * Indirectly set VMX_INST_ERR to 12 ("VMREAD/VMWRITE from/to 3225 * unsupported VMCS component"). The caller can then check 3226 * to see if a failed VM-entry sets VMX_INST_ERR as expected. 3227 */ 3228 vmcs_write(~0u, 0); 3229 3230 vmcs_write(HOST_RIP, (uintptr_t)&&success); 3231 __asm__ __volatile__ goto ("vmwrite %%rsp, %0; vmlaunch" 3232 : 3233 : "r" ((u64)HOST_RSP) 3234 : "cc", "memory" 3235 : success); 3236 return false; 3237 success: 3238 TEST_ASSERT(vmcs_read(EXI_REASON) == 3239 (VMX_FAIL_STATE | VMX_ENTRY_FAILURE)); 3240 return true; 3241 } 3242 3243 /* 3244 * Try to launch the current VMCS. 3245 */ 3246 static void test_vmx_controls(bool controls_valid, bool xfail) 3247 { 3248 bool success = vmlaunch_succeeds(); 3249 u32 vmx_inst_err; 3250 3251 report_xfail("vmlaunch %s", xfail, success == controls_valid, 3252 controls_valid ? "succeeds" : "fails"); 3253 if (!success) { 3254 vmx_inst_err = vmcs_read(VMX_INST_ERROR); 3255 report("VMX inst error is %d (actual %d)", 3256 vmx_inst_err == VMXERR_ENTRY_INVALID_CONTROL_FIELD, 3257 VMXERR_ENTRY_INVALID_CONTROL_FIELD, vmx_inst_err); 3258 } 3259 } 3260 3261 /* 3262 * Test a particular value of a VM-execution control bit, if the value 3263 * is required or if the value is zero. 3264 */ 3265 static void test_rsvd_ctl_bit_value(const char *name, union vmx_ctrl_msr msr, 3266 enum Encoding encoding, unsigned bit, 3267 unsigned val) 3268 { 3269 u32 mask = 1u << bit; 3270 bool expected; 3271 u32 controls; 3272 3273 if (msr.set & mask) 3274 TEST_ASSERT(msr.clr & mask); 3275 3276 /* 3277 * We can't arbitrarily turn on a control bit, because it may 3278 * introduce dependencies on other VMCS fields. So, we only 3279 * test turning on bits that have a required setting. 3280 */ 3281 if (val && (msr.clr & mask) && !(msr.set & mask)) 3282 return; 3283 3284 report_prefix_pushf("%s %s bit %d", 3285 val ? "Set" : "Clear", name, bit); 3286 3287 controls = vmcs_read(encoding); 3288 if (val) { 3289 vmcs_write(encoding, msr.set | mask); 3290 expected = (msr.clr & mask); 3291 } else { 3292 vmcs_write(encoding, msr.set & ~mask); 3293 expected = !(msr.set & mask); 3294 } 3295 test_vmx_controls(expected, false); 3296 vmcs_write(encoding, controls); 3297 report_prefix_pop(); 3298 } 3299 3300 /* 3301 * Test reserved values of a VM-execution control bit, based on the 3302 * allowed bit settings from the corresponding VMX capability MSR. 3303 */ 3304 static void test_rsvd_ctl_bit(const char *name, union vmx_ctrl_msr msr, 3305 enum Encoding encoding, unsigned bit) 3306 { 3307 test_rsvd_ctl_bit_value(name, msr, encoding, bit, 0); 3308 test_rsvd_ctl_bit_value(name, msr, encoding, bit, 1); 3309 } 3310 3311 /* 3312 * Reserved bits in the pin-based VM-execution controls must be set 3313 * properly. Software may consult the VMX capability MSRs to determine 3314 * the proper settings. 3315 * [Intel SDM] 3316 */ 3317 static void test_pin_based_ctls(void) 3318 { 3319 unsigned bit; 3320 3321 printf("%s: %lx\n", basic.ctrl ? "MSR_IA32_VMX_TRUE_PIN" : 3322 "MSR_IA32_VMX_PINBASED_CTLS", ctrl_pin_rev.val); 3323 for (bit = 0; bit < 32; bit++) 3324 test_rsvd_ctl_bit("pin-based controls", 3325 ctrl_pin_rev, PIN_CONTROLS, bit); 3326 } 3327 3328 /* 3329 * Reserved bits in the primary processor-based VM-execution controls 3330 * must be set properly. Software may consult the VMX capability MSRs 3331 * to determine the proper settings. 3332 * [Intel SDM] 3333 */ 3334 static void test_primary_processor_based_ctls(void) 3335 { 3336 unsigned bit; 3337 3338 printf("\n%s: %lx\n", basic.ctrl ? "MSR_IA32_VMX_TRUE_PROC" : 3339 "MSR_IA32_VMX_PROCBASED_CTLS", ctrl_cpu_rev[0].val); 3340 for (bit = 0; bit < 32; bit++) 3341 test_rsvd_ctl_bit("primary processor-based controls", 3342 ctrl_cpu_rev[0], CPU_EXEC_CTRL0, bit); 3343 } 3344 3345 /* 3346 * If the "activate secondary controls" primary processor-based 3347 * VM-execution control is 1, reserved bits in the secondary 3348 * processor-based VM-execution controls must be cleared. Software may 3349 * consult the VMX capability MSRs to determine which bits are 3350 * reserved. 3351 * If the "activate secondary controls" primary processor-based 3352 * VM-execution control is 0 (or if the processor does not support the 3353 * 1-setting of that control), no checks are performed on the 3354 * secondary processor-based VM-execution controls. 3355 * [Intel SDM] 3356 */ 3357 static void test_secondary_processor_based_ctls(void) 3358 { 3359 u32 primary; 3360 u32 secondary; 3361 unsigned bit; 3362 3363 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY)) 3364 return; 3365 3366 primary = vmcs_read(CPU_EXEC_CTRL0); 3367 secondary = vmcs_read(CPU_EXEC_CTRL1); 3368 3369 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY); 3370 printf("\nMSR_IA32_VMX_PROCBASED_CTLS2: %lx\n", ctrl_cpu_rev[1].val); 3371 for (bit = 0; bit < 32; bit++) 3372 test_rsvd_ctl_bit("secondary processor-based controls", 3373 ctrl_cpu_rev[1], CPU_EXEC_CTRL1, bit); 3374 3375 /* 3376 * When the "activate secondary controls" VM-execution control 3377 * is clear, there are no checks on the secondary controls. 3378 */ 3379 vmcs_write(CPU_EXEC_CTRL0, primary & ~CPU_SECONDARY); 3380 vmcs_write(CPU_EXEC_CTRL1, ~0); 3381 report("Secondary processor-based controls ignored", 3382 vmlaunch_succeeds()); 3383 vmcs_write(CPU_EXEC_CTRL1, secondary); 3384 vmcs_write(CPU_EXEC_CTRL0, primary); 3385 } 3386 3387 static void try_cr3_target_count(unsigned i, unsigned max) 3388 { 3389 report_prefix_pushf("CR3 target count 0x%x", i); 3390 vmcs_write(CR3_TARGET_COUNT, i); 3391 test_vmx_controls(i <= max, false); 3392 report_prefix_pop(); 3393 } 3394 3395 /* 3396 * The CR3-target count must not be greater than 4. Future processors 3397 * may support a different number of CR3-target values. Software 3398 * should read the VMX capability MSR IA32_VMX_MISC to determine the 3399 * number of values supported. 3400 * [Intel SDM] 3401 */ 3402 static void test_cr3_targets(void) 3403 { 3404 unsigned supported_targets = (rdmsr(MSR_IA32_VMX_MISC) >> 16) & 0x1ff; 3405 u32 cr3_targets = vmcs_read(CR3_TARGET_COUNT); 3406 unsigned i; 3407 3408 printf("\nSupported CR3 targets: %d\n", supported_targets); 3409 TEST_ASSERT(supported_targets <= 256); 3410 3411 try_cr3_target_count(-1u, supported_targets); 3412 try_cr3_target_count(0x80000000, supported_targets); 3413 try_cr3_target_count(0x7fffffff, supported_targets); 3414 for (i = 0; i <= supported_targets + 1; i++) 3415 try_cr3_target_count(i, supported_targets); 3416 vmcs_write(CR3_TARGET_COUNT, cr3_targets); 3417 } 3418 3419 /* 3420 * Test a particular address setting for a physical page reference in 3421 * the VMCS. 3422 */ 3423 static void test_vmcs_page_addr(const char *name, 3424 enum Encoding encoding, 3425 bool ignored, 3426 bool xfail_beyond_mapped_ram, 3427 u64 addr) 3428 { 3429 bool xfail = 3430 (xfail_beyond_mapped_ram && 3431 addr > fwcfg_get_u64(FW_CFG_RAM_SIZE) - PAGE_SIZE && 3432 addr < (1ul << cpuid_maxphyaddr())); 3433 3434 report_prefix_pushf("%s = %lx", name, addr); 3435 vmcs_write(encoding, addr); 3436 test_vmx_controls(ignored || (IS_ALIGNED(addr, PAGE_SIZE) && 3437 addr < (1ul << cpuid_maxphyaddr())), 3438 xfail); 3439 report_prefix_pop(); 3440 xfail = false; 3441 } 3442 3443 /* 3444 * Test interesting values for a physical page reference in the VMCS. 3445 */ 3446 static void test_vmcs_page_values(const char *name, 3447 enum Encoding encoding, 3448 bool ignored, 3449 bool xfail_beyond_mapped_ram) 3450 { 3451 unsigned i; 3452 u64 orig_val = vmcs_read(encoding); 3453 3454 for (i = 0; i < 64; i++) 3455 test_vmcs_page_addr(name, encoding, ignored, 3456 xfail_beyond_mapped_ram, 1ul << i); 3457 3458 test_vmcs_page_addr(name, encoding, ignored, 3459 xfail_beyond_mapped_ram, PAGE_SIZE - 1); 3460 test_vmcs_page_addr(name, encoding, ignored, 3461 xfail_beyond_mapped_ram, PAGE_SIZE); 3462 test_vmcs_page_addr(name, encoding, ignored, 3463 xfail_beyond_mapped_ram, 3464 (1ul << cpuid_maxphyaddr()) - PAGE_SIZE); 3465 test_vmcs_page_addr(name, encoding, ignored, 3466 xfail_beyond_mapped_ram, 3467 -1ul); 3468 3469 vmcs_write(encoding, orig_val); 3470 } 3471 3472 /* 3473 * Test a physical page reference in the VMCS, when the corresponding 3474 * feature is enabled and when the corresponding feature is disabled. 3475 */ 3476 static void test_vmcs_page_reference(u32 control_bit, enum Encoding field, 3477 const char *field_name, 3478 const char *control_name, 3479 bool xfail_beyond_mapped_ram, 3480 bool control_primary) 3481 { 3482 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 3483 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 3484 u64 page_addr; 3485 3486 if (control_primary) { 3487 if (!(ctrl_cpu_rev[0].clr & control_bit)) 3488 return; 3489 } else { 3490 if (!(ctrl_cpu_rev[1].clr & control_bit)) 3491 return; 3492 } 3493 3494 page_addr = vmcs_read(field); 3495 3496 report_prefix_pushf("%s enabled", control_name); 3497 if (control_primary) { 3498 vmcs_write(CPU_EXEC_CTRL0, primary | control_bit); 3499 } else { 3500 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY); 3501 vmcs_write(CPU_EXEC_CTRL1, secondary | control_bit); 3502 } 3503 test_vmcs_page_values(field_name, field, false, xfail_beyond_mapped_ram); 3504 report_prefix_pop(); 3505 3506 report_prefix_pushf("%s disabled", control_name); 3507 if (control_primary) { 3508 vmcs_write(CPU_EXEC_CTRL0, primary & ~control_bit); 3509 } else { 3510 vmcs_write(CPU_EXEC_CTRL0, primary & ~CPU_SECONDARY); 3511 vmcs_write(CPU_EXEC_CTRL1, secondary & ~control_bit); 3512 } 3513 test_vmcs_page_values(field_name, field, true, false); 3514 report_prefix_pop(); 3515 3516 vmcs_write(field, page_addr); 3517 vmcs_write(CPU_EXEC_CTRL0, primary); 3518 } 3519 3520 /* 3521 * If the "use I/O bitmaps" VM-execution control is 1, bits 11:0 of 3522 * each I/O-bitmap address must be 0. Neither address should set any 3523 * bits beyond the processor's physical-address width. 3524 * [Intel SDM] 3525 */ 3526 static void test_io_bitmaps(void) 3527 { 3528 test_vmcs_page_reference(CPU_IO_BITMAP, IO_BITMAP_A, 3529 "I/O bitmap A", "Use I/O bitmaps", false, 3530 true); 3531 test_vmcs_page_reference(CPU_IO_BITMAP, IO_BITMAP_B, 3532 "I/O bitmap B", "Use I/O bitmaps", false, 3533 true); 3534 } 3535 3536 /* 3537 * If the "use MSR bitmaps" VM-execution control is 1, bits 11:0 of 3538 * the MSR-bitmap address must be 0. The address should not set any 3539 * bits beyond the processor's physical-address width. 3540 * [Intel SDM] 3541 */ 3542 static void test_msr_bitmap(void) 3543 { 3544 test_vmcs_page_reference(CPU_MSR_BITMAP, MSR_BITMAP, 3545 "MSR bitmap", "Use MSR bitmaps", false, 3546 true); 3547 } 3548 3549 /* 3550 * If the "use TPR shadow" VM-execution control is 1, the virtual-APIC 3551 * address must satisfy the following checks: 3552 * - Bits 11:0 of the address must be 0. 3553 * - The address should not set any bits beyond the processor's 3554 * physical-address width. 3555 * [Intel SDM] 3556 */ 3557 static void test_apic_virt_addr(void) 3558 { 3559 test_vmcs_page_reference(CPU_TPR_SHADOW, APIC_VIRT_ADDR, 3560 "virtual-APIC address", "Use TPR shadow", 3561 true, true); 3562 } 3563 3564 /* 3565 * If the "virtualize APIC-accesses" VM-execution control is 1, the 3566 * APIC-access address must satisfy the following checks: 3567 * - Bits 11:0 of the address must be 0. 3568 * - The address should not set any bits beyond the processor's 3569 * physical-address width. 3570 * [Intel SDM] 3571 */ 3572 static void test_apic_access_addr(void) 3573 { 3574 void *apic_access_page = alloc_page(); 3575 3576 vmcs_write(APIC_ACCS_ADDR, virt_to_phys(apic_access_page)); 3577 3578 test_vmcs_page_reference(CPU_VIRT_APIC_ACCESSES, APIC_ACCS_ADDR, 3579 "APIC-access address", 3580 "virtualize APIC-accesses", true, false); 3581 } 3582 3583 static void set_vtpr(unsigned vtpr) 3584 { 3585 *(u32 *)phys_to_virt(vmcs_read(APIC_VIRT_ADDR) + APIC_TASKPRI) = vtpr; 3586 } 3587 3588 static void try_tpr_threshold_and_vtpr(unsigned threshold, unsigned vtpr) 3589 { 3590 bool valid = true; 3591 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 3592 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 3593 3594 if ((primary & CPU_TPR_SHADOW) && 3595 (!(primary & CPU_SECONDARY) || 3596 !(secondary & (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)))) 3597 valid = (threshold & 0xf) <= ((vtpr >> 4) & 0xf); 3598 3599 set_vtpr(vtpr); 3600 report_prefix_pushf("TPR threshold 0x%x, VTPR.class 0x%x", 3601 threshold, (vtpr >> 4) & 0xf); 3602 test_vmx_controls(valid, false); 3603 report_prefix_pop(); 3604 } 3605 3606 /* 3607 * Test interesting vTPR values for a given TPR threshold. 3608 */ 3609 static void test_vtpr_values(unsigned threshold) 3610 { 3611 try_tpr_threshold_and_vtpr(threshold, threshold - 1); 3612 try_tpr_threshold_and_vtpr(threshold, threshold); 3613 try_tpr_threshold_and_vtpr(threshold, threshold + 1); 3614 } 3615 3616 static void try_tpr_threshold(unsigned threshold) 3617 { 3618 bool valid = true; 3619 3620 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 3621 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 3622 3623 if ((primary & CPU_TPR_SHADOW) && !((primary & CPU_SECONDARY) && 3624 (secondary & CPU_VINTD))) 3625 valid = !(threshold >> 4); 3626 3627 set_vtpr(-1); 3628 vmcs_write(TPR_THRESHOLD, threshold); 3629 report_prefix_pushf("TPR threshold 0x%x, VTPR.class 0xf", threshold); 3630 test_vmx_controls(valid, false); 3631 report_prefix_pop(); 3632 3633 if (valid) 3634 test_vtpr_values(threshold); 3635 } 3636 3637 /* 3638 * Test interesting TPR threshold values. 3639 */ 3640 static void test_tpr_threshold_values(void) 3641 { 3642 unsigned i; 3643 3644 for (i = 0; i < 0x10; i++) 3645 try_tpr_threshold(i); 3646 for (i = 4; i < 32; i++) 3647 try_tpr_threshold(1u << i); 3648 try_tpr_threshold(-1u); 3649 try_tpr_threshold(0x7fffffff); 3650 } 3651 3652 /* 3653 * This test covers the following two VM entry checks: 3654 * 3655 * i) If the "use TPR shadow" VM-execution control is 1 and the 3656 * "virtual-interrupt delivery" VM-execution control is 0, bits 3657 * 31:4 of the TPR threshold VM-execution control field must 3658 be 0. 3659 * [Intel SDM] 3660 * 3661 * ii) If the "use TPR shadow" VM-execution control is 1, the 3662 * "virtual-interrupt delivery" VM-execution control is 0 3663 * and the "virtualize APIC accesses" VM-execution control 3664 * is 0, the value of bits 3:0 of the TPR threshold VM-execution 3665 * control field must not be greater than the value of bits 3666 * 7:4 of VTPR. 3667 * [Intel SDM] 3668 */ 3669 static void test_tpr_threshold(void) 3670 { 3671 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 3672 void *virtual_apic_page; 3673 3674 if (!(ctrl_cpu_rev[0].clr & CPU_TPR_SHADOW)) 3675 return; 3676 3677 virtual_apic_page = alloc_page(); 3678 memset(virtual_apic_page, 0xff, PAGE_SIZE); 3679 vmcs_write(APIC_VIRT_ADDR, virt_to_phys(virtual_apic_page)); 3680 3681 vmcs_write(CPU_EXEC_CTRL0, primary & ~(CPU_TPR_SHADOW | CPU_SECONDARY)); 3682 report_prefix_pushf("Use TPR shadow disabled, secondary controls disabled"); 3683 test_tpr_threshold_values(); 3684 report_prefix_pop(); 3685 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | CPU_TPR_SHADOW); 3686 report_prefix_pushf("Use TPR shadow enabled"); 3687 test_tpr_threshold_values(); 3688 report_prefix_pop(); 3689 3690 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 3691 (ctrl_cpu_rev[1].clr & (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)))) 3692 return; 3693 3694 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 3695 3696 if (ctrl_cpu_rev[1].clr & CPU_VINTD) { 3697 vmcs_write(CPU_EXEC_CTRL1, CPU_VINTD); 3698 report_prefix_pushf("Use TPR shadow enabled; secondary controls disabled; virtual-interrupt delivery enabled; virtualize APIC accesses disabled"); 3699 test_tpr_threshold_values(); 3700 report_prefix_pop(); 3701 3702 vmcs_write(CPU_EXEC_CTRL0, 3703 vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 3704 report_prefix_pushf("Use TPR shadow enabled; secondary controls enabled; virtual-interrupt delivery enabled; virtualize APIC accesses disabled"); 3705 test_tpr_threshold_values(); 3706 report_prefix_pop(); 3707 } 3708 3709 if (ctrl_cpu_rev[1].clr & CPU_VIRT_APIC_ACCESSES) { 3710 vmcs_write(CPU_EXEC_CTRL0, 3711 vmcs_read(CPU_EXEC_CTRL0) & ~CPU_SECONDARY); 3712 vmcs_write(CPU_EXEC_CTRL1, CPU_VIRT_APIC_ACCESSES); 3713 report_prefix_pushf("Use TPR shadow enabled; secondary controls disabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 3714 test_tpr_threshold_values(); 3715 report_prefix_pop(); 3716 3717 vmcs_write(CPU_EXEC_CTRL0, 3718 vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 3719 report_prefix_pushf("Use TPR shadow enabled; secondary controls enabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 3720 test_tpr_threshold_values(); 3721 report_prefix_pop(); 3722 } 3723 3724 if ((ctrl_cpu_rev[1].clr & 3725 (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)) == 3726 (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)) { 3727 vmcs_write(CPU_EXEC_CTRL0, 3728 vmcs_read(CPU_EXEC_CTRL0) & ~CPU_SECONDARY); 3729 vmcs_write(CPU_EXEC_CTRL1, 3730 CPU_VINTD | CPU_VIRT_APIC_ACCESSES); 3731 report_prefix_pushf("Use TPR shadow enabled; secondary controls disabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 3732 test_tpr_threshold_values(); 3733 report_prefix_pop(); 3734 3735 vmcs_write(CPU_EXEC_CTRL0, 3736 vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 3737 report_prefix_pushf("Use TPR shadow enabled; secondary controls enabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 3738 test_tpr_threshold_values(); 3739 report_prefix_pop(); 3740 } 3741 3742 vmcs_write(CPU_EXEC_CTRL1, secondary); 3743 vmcs_write(CPU_EXEC_CTRL0, primary); 3744 } 3745 3746 /* 3747 * This test verifies the following two vmentry checks: 3748 * 3749 * If the "NMI exiting" VM-execution control is 0, "Virtual NMIs" 3750 * VM-execution control must be 0. 3751 * [Intel SDM] 3752 * 3753 * If the “virtual NMIs” VM-execution control is 0, the “NMI-window 3754 * exiting” VM-execution control must be 0. 3755 * [Intel SDM] 3756 */ 3757 static void test_nmi_ctrls(void) 3758 { 3759 u32 pin_ctrls, cpu_ctrls0, test_pin_ctrls, test_cpu_ctrls0; 3760 3761 if ((ctrl_pin_rev.clr & (PIN_NMI | PIN_VIRT_NMI)) != 3762 (PIN_NMI | PIN_VIRT_NMI)) { 3763 test_skip("NMI exiting and Virtual NMIs are not supported !"); 3764 return; 3765 } 3766 3767 /* Save the controls so that we can restore them after our tests */ 3768 pin_ctrls = vmcs_read(PIN_CONTROLS); 3769 cpu_ctrls0 = vmcs_read(CPU_EXEC_CTRL0); 3770 3771 test_pin_ctrls = pin_ctrls & ~(PIN_NMI | PIN_VIRT_NMI); 3772 test_cpu_ctrls0 = cpu_ctrls0 & ~CPU_NMI_WINDOW; 3773 3774 vmcs_write(PIN_CONTROLS, test_pin_ctrls); 3775 report_prefix_pushf("NMI-exiting disabled, virtual-NMIs disabled"); 3776 test_vmx_controls(true, false); 3777 report_prefix_pop(); 3778 3779 vmcs_write(PIN_CONTROLS, test_pin_ctrls | PIN_VIRT_NMI); 3780 report_prefix_pushf("NMI-exiting disabled, virtual-NMIs enabled"); 3781 test_vmx_controls(false, false); 3782 report_prefix_pop(); 3783 3784 vmcs_write(PIN_CONTROLS, test_pin_ctrls | (PIN_NMI | PIN_VIRT_NMI)); 3785 report_prefix_pushf("NMI-exiting enabled, virtual-NMIs enabled"); 3786 test_vmx_controls(true, false); 3787 report_prefix_pop(); 3788 3789 vmcs_write(PIN_CONTROLS, test_pin_ctrls | PIN_NMI); 3790 report_prefix_pushf("NMI-exiting enabled, virtual-NMIs disabled"); 3791 test_vmx_controls(true, false); 3792 report_prefix_pop(); 3793 3794 if (!(ctrl_cpu_rev[0].clr & CPU_NMI_WINDOW)) { 3795 report_info("NMI-window exiting is not supported, skipping..."); 3796 goto done; 3797 } 3798 3799 vmcs_write(PIN_CONTROLS, test_pin_ctrls); 3800 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0 | CPU_NMI_WINDOW); 3801 report_prefix_pushf("Virtual-NMIs disabled, NMI-window-exiting enabled"); 3802 test_vmx_controls(false, false); 3803 report_prefix_pop(); 3804 3805 vmcs_write(PIN_CONTROLS, test_pin_ctrls); 3806 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0); 3807 report_prefix_pushf("Virtual-NMIs disabled, NMI-window-exiting disabled"); 3808 test_vmx_controls(true, false); 3809 report_prefix_pop(); 3810 3811 vmcs_write(PIN_CONTROLS, test_pin_ctrls | (PIN_NMI | PIN_VIRT_NMI)); 3812 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0 | CPU_NMI_WINDOW); 3813 report_prefix_pushf("Virtual-NMIs enabled, NMI-window-exiting enabled"); 3814 test_vmx_controls(true, false); 3815 report_prefix_pop(); 3816 3817 vmcs_write(PIN_CONTROLS, test_pin_ctrls | (PIN_NMI | PIN_VIRT_NMI)); 3818 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0); 3819 report_prefix_pushf("Virtual-NMIs enabled, NMI-window-exiting disabled"); 3820 test_vmx_controls(true, false); 3821 report_prefix_pop(); 3822 3823 /* Restore the controls to their original values */ 3824 vmcs_write(CPU_EXEC_CTRL0, cpu_ctrls0); 3825 done: 3826 vmcs_write(PIN_CONTROLS, pin_ctrls); 3827 } 3828 3829 3830 /* 3831 * Check that the virtual CPU checks all of the VMX controls as 3832 * documented in the Intel SDM. 3833 */ 3834 static void vmx_controls_test(void) 3835 { 3836 /* 3837 * Bit 1 of the guest's RFLAGS must be 1, or VM-entry will 3838 * fail due to invalid guest state, should we make it that 3839 * far. 3840 */ 3841 vmcs_write(GUEST_RFLAGS, 0); 3842 3843 test_pin_based_ctls(); 3844 test_primary_processor_based_ctls(); 3845 test_secondary_processor_based_ctls(); 3846 test_cr3_targets(); 3847 test_io_bitmaps(); 3848 test_msr_bitmap(); 3849 test_apic_virt_addr(); 3850 test_apic_access_addr(); 3851 test_tpr_threshold(); 3852 test_nmi_ctrls(); 3853 } 3854 3855 static bool valid_vmcs_for_vmentry(void) 3856 { 3857 struct vmcs *current_vmcs = NULL; 3858 3859 if (vmcs_save(¤t_vmcs)) 3860 return false; 3861 3862 return current_vmcs && !(current_vmcs->revision_id >> 31); 3863 } 3864 3865 static void try_vmentry_in_movss_shadow(void) 3866 { 3867 u32 vm_inst_err; 3868 u32 flags; 3869 bool early_failure = false; 3870 u32 expected_flags = X86_EFLAGS_FIXED; 3871 bool valid_vmcs = valid_vmcs_for_vmentry(); 3872 3873 expected_flags |= valid_vmcs ? X86_EFLAGS_ZF : X86_EFLAGS_CF; 3874 3875 /* 3876 * Indirectly set VM_INST_ERR to 12 ("VMREAD/VMWRITE from/to 3877 * unsupported VMCS component"). 3878 */ 3879 vmcs_write(~0u, 0); 3880 3881 __asm__ __volatile__ ("mov %[host_rsp], %%edx;" 3882 "vmwrite %%rsp, %%rdx;" 3883 "mov 0f, %%rax;" 3884 "mov %[host_rip], %%edx;" 3885 "vmwrite %%rax, %%rdx;" 3886 "mov $-1, %%ah;" 3887 "sahf;" 3888 "mov %%ss, %%ax;" 3889 "mov %%ax, %%ss;" 3890 "vmlaunch;" 3891 "mov $1, %[early_failure];" 3892 "0: lahf;" 3893 "movzbl %%ah, %[flags]" 3894 : [early_failure] "+r" (early_failure), 3895 [flags] "=&a" (flags) 3896 : [host_rsp] "i" (HOST_RSP), 3897 [host_rip] "i" (HOST_RIP) 3898 : "rdx", "cc", "memory"); 3899 vm_inst_err = vmcs_read(VMX_INST_ERROR); 3900 3901 report("Early VM-entry failure", early_failure); 3902 report("RFLAGS[8:0] is %x (actual %x)", flags == expected_flags, 3903 expected_flags, flags); 3904 if (valid_vmcs) 3905 report("VM-instruction error is %d (actual %d)", 3906 vm_inst_err == VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS, 3907 VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS, vm_inst_err); 3908 } 3909 3910 static void vmentry_movss_shadow_test(void) 3911 { 3912 struct vmcs *orig_vmcs; 3913 3914 TEST_ASSERT(!vmcs_save(&orig_vmcs)); 3915 3916 /* 3917 * Set the launched flag on the current VMCS to verify the correct 3918 * error priority, below. 3919 */ 3920 test_set_guest(v2_null_test_guest); 3921 enter_guest(); 3922 3923 /* 3924 * With bit 1 of the guest's RFLAGS clear, VM-entry should 3925 * fail due to invalid guest state (if we make it that far). 3926 */ 3927 vmcs_write(GUEST_RFLAGS, 0); 3928 3929 /* 3930 * "VM entry with events blocked by MOV SS" takes precedence over 3931 * "VMLAUNCH with non-clear VMCS." 3932 */ 3933 report_prefix_push("valid current-VMCS"); 3934 try_vmentry_in_movss_shadow(); 3935 report_prefix_pop(); 3936 3937 /* 3938 * VMfailInvalid takes precedence over "VM entry with events 3939 * blocked by MOV SS." 3940 */ 3941 TEST_ASSERT(!vmcs_clear(orig_vmcs)); 3942 report_prefix_push("no current-VMCS"); 3943 try_vmentry_in_movss_shadow(); 3944 report_prefix_pop(); 3945 3946 TEST_ASSERT(!make_vmcs_current(orig_vmcs)); 3947 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED); 3948 } 3949 3950 #define X86_FEATURE_PCID (1 << 17) 3951 #define X86_FEATURE_MCE (1 << 7) 3952 3953 static int write_cr4_checking(unsigned long val) 3954 { 3955 asm volatile(ASM_TRY("1f") 3956 "mov %0, %%cr4\n\t" 3957 "1:": : "r" (val)); 3958 return exception_vector(); 3959 } 3960 3961 static void vmx_cr_load_test(void) 3962 { 3963 struct cpuid _cpuid = cpuid(1); 3964 unsigned long cr4 = read_cr4(), cr3 = read_cr3(); 3965 3966 if (!(_cpuid.c & X86_FEATURE_PCID)) { 3967 report_skip("PCID not detected"); 3968 return; 3969 } 3970 if (!(_cpuid.d & X86_FEATURE_MCE)) { 3971 report_skip("MCE not detected"); 3972 return; 3973 } 3974 3975 TEST_ASSERT(!(cr4 & (X86_CR4_PCIDE | X86_CR4_MCE))); 3976 TEST_ASSERT(!(cr3 & X86_CR3_PCID_MASK)); 3977 3978 /* Enable PCID for L1. */ 3979 cr4 |= X86_CR4_PCIDE; 3980 cr3 |= 0x1; 3981 TEST_ASSERT(!write_cr4_checking(cr4)); 3982 write_cr3(cr3); 3983 3984 test_set_guest(v2_null_test_guest); 3985 vmcs_write(HOST_CR4, cr4); 3986 vmcs_write(HOST_CR3, cr3); 3987 enter_guest(); 3988 3989 /* 3990 * No exception is expected. 3991 * 3992 * NB. KVM loads the last guest write to CR4 into CR4 read 3993 * shadow. In order to trigger an exit to KVM, we can set a 3994 * bit that was zero in the above CR4 write and is owned by 3995 * KVM. We choose to set CR4.MCE, which shall have no side 3996 * effect because normally no guest MCE (e.g., as the result 3997 * of bad memory) would happen during this test. 3998 */ 3999 TEST_ASSERT(!write_cr4_checking(cr4 | X86_CR4_MCE)); 4000 4001 /* Cleanup L1 state: disable PCID. */ 4002 write_cr3(cr3 & ~X86_CR3_PCID_MASK); 4003 TEST_ASSERT(!write_cr4_checking(cr4 & ~X86_CR4_PCIDE)); 4004 } 4005 4006 static bool cpu_has_apicv(void) 4007 { 4008 return ((ctrl_cpu_rev[1].clr & CPU_APIC_REG_VIRT) && 4009 (ctrl_cpu_rev[1].clr & CPU_VINTD) && 4010 (ctrl_pin_rev.clr & PIN_POST_INTR)); 4011 } 4012 4013 static void trigger_ioapic_scan_thread(void *data) 4014 { 4015 /* Wait until other CPU entered L2 */ 4016 while (vmx_get_test_stage() != 1) 4017 ; 4018 4019 /* Trigger ioapic scan */ 4020 ioapic_set_redir(0xf, 0x79, TRIGGER_LEVEL); 4021 vmx_set_test_stage(2); 4022 } 4023 4024 static void irq_79_handler_guest(isr_regs_t *regs) 4025 { 4026 eoi(); 4027 4028 /* L1 expects vmexit on VMX_VMCALL and not VMX_EOI_INDUCED */ 4029 vmcall(); 4030 } 4031 4032 /* 4033 * Constant for num of busy-loop iterations after which 4034 * a timer interrupt should have happened in host 4035 */ 4036 #define TIMER_INTERRUPT_DELAY 100000000 4037 4038 static void vmx_eoi_bitmap_ioapic_scan_test_guest(void) 4039 { 4040 handle_irq(0x79, irq_79_handler_guest); 4041 irq_enable(); 4042 4043 /* Signal to L1 CPU to trigger ioapic scan */ 4044 vmx_set_test_stage(1); 4045 /* Wait until L1 CPU to trigger ioapic scan */ 4046 while (vmx_get_test_stage() != 2) 4047 ; 4048 4049 /* 4050 * Wait for L0 timer interrupt to be raised while we run in L2 4051 * such that L0 will process the IOAPIC scan request before 4052 * resuming L2 4053 */ 4054 delay(TIMER_INTERRUPT_DELAY); 4055 4056 asm volatile ("int $0x79"); 4057 } 4058 4059 static void vmx_eoi_bitmap_ioapic_scan_test(void) 4060 { 4061 void *msr_bitmap; 4062 void *virtual_apic_page; 4063 4064 if (!cpu_has_apicv() || (cpu_count() < 2)) { 4065 report_skip(__func__); 4066 return; 4067 } 4068 4069 msr_bitmap = alloc_page(); 4070 virtual_apic_page = alloc_page(); 4071 4072 u64 cpu_ctrl_0 = CPU_SECONDARY | CPU_TPR_SHADOW | CPU_MSR_BITMAP; 4073 u64 cpu_ctrl_1 = CPU_VINTD | CPU_VIRT_X2APIC; 4074 4075 memset(msr_bitmap, 0x0, PAGE_SIZE); 4076 vmcs_write(MSR_BITMAP, (u64)msr_bitmap); 4077 4078 vmcs_write(APIC_VIRT_ADDR, (u64)virtual_apic_page); 4079 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) | PIN_EXTINT); 4080 4081 vmcs_write(EOI_EXIT_BITMAP0, 0x0); 4082 vmcs_write(EOI_EXIT_BITMAP1, 0x0); 4083 vmcs_write(EOI_EXIT_BITMAP2, 0x0); 4084 vmcs_write(EOI_EXIT_BITMAP3, 0x0); 4085 4086 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | cpu_ctrl_0); 4087 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | cpu_ctrl_1); 4088 4089 on_cpu_async(1, trigger_ioapic_scan_thread, NULL); 4090 test_set_guest(vmx_eoi_bitmap_ioapic_scan_test_guest); 4091 4092 /* 4093 * Launch L2. 4094 * We expect the exit reason to be VMX_VMCALL (and not EOI INDUCED). 4095 * In case the reason isn't VMX_VMCALL, the asserion inside 4096 * skip_exit_vmcall() will fail. 4097 */ 4098 enter_guest(); 4099 skip_exit_vmcall(); 4100 4101 /* Let L2 finish */ 4102 enter_guest(); 4103 report(__func__, 1); 4104 } 4105 4106 static void set_irq_line_thread(void *data) 4107 { 4108 /* Wait until other CPU entered L2 */ 4109 while (vmx_get_test_stage() != 1) 4110 ; 4111 4112 /* Set irq-line 0xf to raise vector 0x78 for vCPU 0 */ 4113 ioapic_set_redir(0xf, 0x78, TRIGGER_LEVEL); 4114 vmx_set_test_stage(2); 4115 } 4116 4117 static bool irq_78_handler_vmcall_before_eoi; 4118 static void irq_78_handler_guest(isr_regs_t *regs) 4119 { 4120 set_irq_line(0xf, 0); 4121 if (irq_78_handler_vmcall_before_eoi) 4122 vmcall(); 4123 eoi(); 4124 vmcall(); 4125 } 4126 4127 static void vmx_apic_passthrough_guest(void) 4128 { 4129 handle_irq(0x78, irq_78_handler_guest); 4130 irq_enable(); 4131 4132 /* If requested, wait for other CPU to trigger ioapic scan */ 4133 if (vmx_get_test_stage() < 1) { 4134 vmx_set_test_stage(1); 4135 while (vmx_get_test_stage() != 2) 4136 ; 4137 } 4138 4139 set_irq_line(0xf, 1); 4140 } 4141 4142 static void vmx_apic_passthrough(bool set_irq_line_from_thread) 4143 { 4144 void *msr_bitmap; 4145 4146 if (set_irq_line_from_thread && (cpu_count() < 2)) { 4147 report_skip(__func__); 4148 return; 4149 } 4150 4151 msr_bitmap = alloc_page(); 4152 4153 u64 cpu_ctrl_0 = CPU_SECONDARY | CPU_MSR_BITMAP; 4154 u64 cpu_ctrl_1 = 0; 4155 4156 memset(msr_bitmap, 0x0, PAGE_SIZE); 4157 vmcs_write(MSR_BITMAP, (u64)msr_bitmap); 4158 4159 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 4160 4161 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | cpu_ctrl_0); 4162 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | cpu_ctrl_1); 4163 4164 if (set_irq_line_from_thread) { 4165 irq_78_handler_vmcall_before_eoi = false; 4166 on_cpu_async(1, set_irq_line_thread, NULL); 4167 } else { 4168 irq_78_handler_vmcall_before_eoi = true; 4169 ioapic_set_redir(0xf, 0x78, TRIGGER_LEVEL); 4170 vmx_set_test_stage(2); 4171 } 4172 test_set_guest(vmx_apic_passthrough_guest); 4173 4174 if (irq_78_handler_vmcall_before_eoi) { 4175 /* Before EOI remote_irr should still be set */ 4176 enter_guest(); 4177 skip_exit_vmcall(); 4178 TEST_ASSERT_EQ_MSG(1, (int)ioapic_read_redir(0xf).remote_irr, 4179 "IOAPIC pass-through: remote_irr=1 before EOI"); 4180 } 4181 4182 /* After EOI remote_irr should be cleared */ 4183 enter_guest(); 4184 skip_exit_vmcall(); 4185 TEST_ASSERT_EQ_MSG(0, (int)ioapic_read_redir(0xf).remote_irr, 4186 "IOAPIC pass-through: remote_irr=0 after EOI"); 4187 4188 /* Let L2 finish */ 4189 enter_guest(); 4190 report(__func__, 1); 4191 } 4192 4193 static void vmx_apic_passthrough_test(void) 4194 { 4195 vmx_apic_passthrough(false); 4196 } 4197 4198 static void vmx_apic_passthrough_thread_test(void) 4199 { 4200 vmx_apic_passthrough(true); 4201 } 4202 4203 #define TEST(name) { #name, .v2 = name } 4204 4205 /* name/init/guest_main/exit_handler/syscall_handler/guest_regs */ 4206 struct vmx_test vmx_tests[] = { 4207 { "null", NULL, basic_guest_main, basic_exit_handler, NULL, {0} }, 4208 { "vmenter", NULL, vmenter_main, vmenter_exit_handler, NULL, {0} }, 4209 { "preemption timer", preemption_timer_init, preemption_timer_main, 4210 preemption_timer_exit_handler, NULL, {0} }, 4211 { "control field PAT", test_ctrl_pat_init, test_ctrl_pat_main, 4212 test_ctrl_pat_exit_handler, NULL, {0} }, 4213 { "control field EFER", test_ctrl_efer_init, test_ctrl_efer_main, 4214 test_ctrl_efer_exit_handler, NULL, {0} }, 4215 { "CR shadowing", NULL, cr_shadowing_main, 4216 cr_shadowing_exit_handler, NULL, {0} }, 4217 { "I/O bitmap", iobmp_init, iobmp_main, iobmp_exit_handler, 4218 NULL, {0} }, 4219 { "instruction intercept", insn_intercept_init, insn_intercept_main, 4220 insn_intercept_exit_handler, NULL, {0} }, 4221 { "EPT A/D disabled", ept_init, ept_main, ept_exit_handler, NULL, {0} }, 4222 { "EPT A/D enabled", eptad_init, eptad_main, eptad_exit_handler, NULL, {0} }, 4223 { "PML", pml_init, pml_main, pml_exit_handler, NULL, {0} }, 4224 { "VPID", vpid_init, vpid_main, vpid_exit_handler, NULL, {0} }, 4225 { "interrupt", interrupt_init, interrupt_main, 4226 interrupt_exit_handler, NULL, {0} }, 4227 { "debug controls", dbgctls_init, dbgctls_main, dbgctls_exit_handler, 4228 NULL, {0} }, 4229 { "MSR switch", msr_switch_init, msr_switch_main, 4230 msr_switch_exit_handler, NULL, {0}, msr_switch_entry_failure }, 4231 { "vmmcall", vmmcall_init, vmmcall_main, vmmcall_exit_handler, NULL, {0} }, 4232 { "disable RDTSCP", disable_rdtscp_init, disable_rdtscp_main, 4233 disable_rdtscp_exit_handler, NULL, {0} }, 4234 { "int3", int3_init, int3_guest_main, int3_exit_handler, NULL, {0} }, 4235 { "into", into_init, into_guest_main, into_exit_handler, NULL, {0} }, 4236 { "exit_monitor_from_l2_test", NULL, exit_monitor_from_l2_main, 4237 exit_monitor_from_l2_handler, NULL, {0} }, 4238 /* Basic V2 tests. */ 4239 TEST(v2_null_test), 4240 TEST(v2_multiple_entries_test), 4241 TEST(fixture_test_case1), 4242 TEST(fixture_test_case2), 4243 /* EPT access tests. */ 4244 TEST(ept_access_test_not_present), 4245 TEST(ept_access_test_read_only), 4246 TEST(ept_access_test_write_only), 4247 TEST(ept_access_test_read_write), 4248 TEST(ept_access_test_execute_only), 4249 TEST(ept_access_test_read_execute), 4250 TEST(ept_access_test_write_execute), 4251 TEST(ept_access_test_read_write_execute), 4252 TEST(ept_access_test_reserved_bits), 4253 TEST(ept_access_test_ignored_bits), 4254 TEST(ept_access_test_paddr_not_present_ad_disabled), 4255 TEST(ept_access_test_paddr_not_present_ad_enabled), 4256 TEST(ept_access_test_paddr_read_only_ad_disabled), 4257 TEST(ept_access_test_paddr_read_only_ad_enabled), 4258 TEST(ept_access_test_paddr_read_write), 4259 TEST(ept_access_test_paddr_read_write_execute), 4260 TEST(ept_access_test_paddr_read_execute_ad_disabled), 4261 TEST(ept_access_test_paddr_read_execute_ad_enabled), 4262 TEST(ept_access_test_paddr_not_present_page_fault), 4263 TEST(ept_access_test_force_2m_page), 4264 /* Opcode tests. */ 4265 TEST(invvpid_test_v2), 4266 /* VM-entry tests */ 4267 TEST(vmx_controls_test), 4268 TEST(vmentry_movss_shadow_test), 4269 /* APICv tests */ 4270 TEST(vmx_eoi_bitmap_ioapic_scan_test), 4271 /* APIC pass-through tests */ 4272 TEST(vmx_apic_passthrough_test), 4273 TEST(vmx_apic_passthrough_thread_test), 4274 /* Regression tests */ 4275 TEST(vmx_cr_load_test), 4276 { NULL, NULL, NULL, NULL, NULL, {0} }, 4277 }; 4278