lib: Use __ASSEMBLER__ instead of __ASSEMBLY__

Convert all non-x86 #ifdefs from __ASSEMBLY__ to __ASSEMBLER__, and remove
all manual __ASSEMBLY__ #defines. __ASSEMBLY_ was inherited blindly from
th

lib: Use __ASSEMBLER__ instead of __ASSEMBLY__

Convert all non-x86 #ifdefs from __ASSEMBLY__ to __ASSEMBLER__, and remove
all manual __ASSEMBLY__ #defines. __ASSEMBLY_ was inherited blindly from
the Linux kernel, and must be manually defined, e.g. through build rules
or with the aforementioned explicit #defines in assembly code.

__ASSEMBLER__ on the other hand is automatically defined by the compiler
when preprocessing assembly, i.e. doesn't require manually #defines for
the code to function correctly.

Ignore x86, as x86 doesn't actually rely on __ASSEMBLY__ at the moment,
and is undergoing a parallel cleanup.

Signed-off-by: Sean Christopherson <seanjc@google.com>
Reviewed-by: Andrew Jones <andrew.jones@linux.dev>
Message-ID: <20250222014526.2302653-1-seanjc@google.com>
[thuth: Fix three more occurances in libfdt.h and sbi-tests.h]
Signed-off-by: Thomas Huth <thuth@redhat.com>

show more ...

powerpc: add usermode support

The biggest difficulty for user mode is MMU support. Otherwise it is
a simple matter of setting and clearing MSR[PR] with rfid and sc
respectively.

Some common harness

powerpc: add usermode support

The biggest difficulty for user mode is MMU support. Otherwise it is
a simple matter of setting and clearing MSR[PR] with rfid and sc
respectively.

Some common harness operations will fail in usermode, so some workarounds
are reqiured (e.g., puts() can't be used directly).

A usermode privileged instruction interrupt test is added.

Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Message-ID: <20240612052322.218726-8-npiggin@gmail.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>

show more ...

powerpc: Add MMU support

Add support for radix MMU, 4kB and 64kB pages.

This also adds MMU interrupt test cases, and runs the interrupts
test entirely with MMU enabled if it is available (aside fro

powerpc: Add MMU support

Add support for radix MMU, 4kB and 64kB pages.

This also adds MMU interrupt test cases, and runs the interrupts
test entirely with MMU enabled if it is available (aside from
machine check tests).

Acked-by: Andrew Jones <andrew.jones@linux.dev> (configure changes)
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Message-ID: <20240612052322.218726-5-npiggin@gmail.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>

show more ...

powerpc: Add timebase tests

This has a known failure on QEMU TCG machines where the decrementer
interrupt is not lowered when the DEC wraps from -ve to +ve.

Signed-off-by: Nicholas Piggin <npiggin@

powerpc: Add timebase tests

This has a known failure on QEMU TCG machines where the decrementer
interrupt is not lowered when the DEC wraps from -ve to +ve.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Message-ID: <20240612052322.218726-4-npiggin@gmail.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>

show more ...

powerpc: Add facility to query TCG or KVM host

Use device tree properties to determine whether KVM or TCG is in
use.

Logically these are not the inverse of one another, because KVM can run
on a TCG

powerpc: Add facility to query TCG or KVM host

Use device tree properties to determine whether KVM or TCG is in
use.

Logically these are not the inverse of one another, because KVM can run
on a TCG processor (if TCG is emulating HV mode, or it is using the
nested hypervisor APIs in pseries / spapr). And kvm-unit-tests can run
on that KVM.

This can be a problem because some issues relate to TCG CPU emulation
some to the spapr hypervisor implementation, some to KVM, some to real
hardware, so the TCG test is best-effort for now and is set to the
opposite of KVM. The two independent variables are added because we may
be able to more accurately determine this in future.

Use this facility to restrict some of the known test failures to TCG.

Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Message-ID: <20240612052322.218726-2-npiggin@gmail.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>

show more ...

powerpc: add SMP and IPI support

powerpc SMP support is very primitive and does not set up a first-class
runtime environment for secondary CPUs.

This reworks SMP support, and provides a complete C

powerpc: add SMP and IPI support

powerpc SMP support is very primitive and does not set up a first-class
runtime environment for secondary CPUs.

This reworks SMP support, and provides a complete C and harness
environment for the secondaries, including interrupt handling, as well
as IPI support.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Message-ID: <20240504122841.1177683-17-npiggin@gmail.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>

show more ...

powerpc: Enable page alloc operations

These will be used for stack allocation for secondary CPUs.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Message-ID: <20240504122841.1177683-16-npiggin@g

powerpc: Enable page alloc operations

These will be used for stack allocation for secondary CPUs.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Message-ID: <20240504122841.1177683-16-npiggin@gmail.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>

show more ...

powerpc: Remove broken SMP exception stack setup

The exception stack setup does not work correctly for SMP, because
it is the boot processor that calls cpu_set() which sets SPRG2 to
the exception st

powerpc: Remove broken SMP exception stack setup

The exception stack setup does not work correctly for SMP, because
it is the boot processor that calls cpu_set() which sets SPRG2 to
the exception stack, not the target CPU itself. So secondaries
never got their SPRG2 set to a valid exception stack.

Remove the SMP code and just set an exception stack for the boot
processor. Make the stack 64kB while we're here, to match the
size of the regular stack.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Message-ID: <20240504122841.1177683-15-npiggin@gmail.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>

show more ...

powerpc: Add rtas stop-self support

In preparation for improved SMP support, add stop-self support to the
harness. This is non-trivial because it requires an unlocked rtas
call: a CPU can't be holdi

powerpc: Add rtas stop-self support

In preparation for improved SMP support, add stop-self support to the
harness. This is non-trivial because it requires an unlocked rtas
call: a CPU can't be holding a spin lock when it goes offline or it
will deadlock other CPUs. rtas permits stop-self to be called without
serialising all other rtas operations.

Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Message-ID: <20240504122841.1177683-14-npiggin@gmail.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>

show more ...

powerpc: general interrupt tests

Add basic testing of various kinds of interrupts, machine check,
page fault, illegal, decrementer, trace, syscall, etc.

This has a known failure on QEMU TCG pseries

powerpc: general interrupt tests

Add basic testing of various kinds of interrupts, machine check,
page fault, illegal, decrementer, trace, syscall, etc.

This has a known failure on QEMU TCG pseries machines where MSR[ME]
can be incorrectly set to 0.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Message-ID: <20240504122841.1177683-13-npiggin@gmail.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>

show more ...

powerpc: Fix emulator illegal instruction test for powernv

Illegal instructions cause 0xe40 (HEAI) interrupts rather
than program interrupts.

Acked-by: Thomas Huth <thuth@redhat.com>
Signed-off-by:

powerpc: Fix emulator illegal instruction test for powernv

Illegal instructions cause 0xe40 (HEAI) interrupts rather
than program interrupts.

Acked-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Message-ID: <20240504122841.1177683-11-npiggin@gmail.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>

show more ...

powerpc: Support powernv machine with QEMU TCG

Add support for QEMU's powernv machine. This uses standard firmware
(skiboot) rather than a minimal firmware shim.

Reviewed-by: Cédric Le Goater <clg@

powerpc: Support powernv machine with QEMU TCG

Add support for QEMU's powernv machine. This uses standard firmware
(skiboot) rather than a minimal firmware shim.

Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Message-ID: <20240504122841.1177683-10-npiggin@gmail.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>

show more ...

powerpc/sprs: Avoid taking PMU interrupts caused by register fuzzing

Storing certain values in MMCR0 can cause PMU interrupts when msleep
enables MSR[EE], and this crashes the test. Freeze the PMU c

powerpc/sprs: Avoid taking PMU interrupts caused by register fuzzing

Storing certain values in MMCR0 can cause PMU interrupts when msleep
enables MSR[EE], and this crashes the test. Freeze the PMU counters
and clear any PMU exception before calling msleep.

Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Message-ID: <20240504122841.1177683-7-npiggin@gmail.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>

show more ...

powerpc/sprs: Specify SPRs with data rather than code

A significant rework that builds an array of 'struct spr', where each
element describes an SPR. This makes various metadata about the SPR
like n

powerpc/sprs: Specify SPRs with data rather than code

A significant rework that builds an array of 'struct spr', where each
element describes an SPR. This makes various metadata about the SPR
like name and access type easier to carry and use.

Hypervisor privileged registers are described despite not being used
at the moment for completeness, but also the code might one day be
reused for a hypervisor-privileged test.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Message-ID: <20240504122841.1177683-6-npiggin@gmail.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>

show more ...

powerpc: interrupt stack backtracing

Add support for backtracing across interrupt stacks, and add
interrupt frame backtrace for unhandled interrupts.

This requires a back-chain created from initial

powerpc: interrupt stack backtracing

Add support for backtracing across interrupt stacks, and add
interrupt frame backtrace for unhandled interrupts.

This requires a back-chain created from initial interrupt stack
frame to the r1 value of the interrupted context. A label is
added at the return location of the exception handler call, so
the unwinder can recognize the initial interrupt frame.

The additional cstart entry-frame is no longer required because
the unwinder now looks for frame == 0 as well as address == 0.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Message-ID: <20240405083539.374995-11-npiggin@gmail.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>

show more ...

powerpc: Cleanup SPR and MSR definitions

Move SPR and MSR defines out of ppc_asm.h and processor.h and into a
new include, asm/reg.h.

Add a define for the PVR SPR and various processor versions, an

powerpc: Cleanup SPR and MSR definitions

Move SPR and MSR defines out of ppc_asm.h and processor.h and into a
new include, asm/reg.h.

Add a define for the PVR SPR and various processor versions, and replace
the open coded numbers in the sprs.c test case.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Message-ID: <20240226101218.1472843-6-npiggin@gmail.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>

show more ...

powerpc: add asm/time.h header with delay and get_clock_us/ms

This matches s390x clock and delay APIs, so common test code can start
using time facilities.

Signed-off-by: Nicholas Piggin <npiggin@g

powerpc: add asm/time.h header with delay and get_clock_us/ms

This matches s390x clock and delay APIs, so common test code can start
using time facilities.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Message-ID: <20240226093832.1468383-5-npiggin@gmail.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>

show more ...

powerpc: Fix pseries getchar return value

getchar() didn't get the shift value correct and never returned the
first character. This never really mattered since it was only ever
used for press-a-key-

powerpc: Fix pseries getchar return value

getchar() didn't get the shift value correct and never returned the
first character. This never really mattered since it was only ever
used for press-a-key-to-continue prompts. but it tripped me up when
debugging a QEMU console output problem.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Message-ID: <20240226101218.1472843-3-npiggin@gmail.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>

show more ...

powerpc: Add support for more interrupts including HV interrupts

Interrupt vectors were not being populated for all architected
interrupt types, which could lead to crashes rather than a message for

powerpc: Add support for more interrupts including HV interrupts

Interrupt vectors were not being populated for all architected
interrupt types, which could lead to crashes rather than a message for
unhandled interrupts.

0x20 sized vectors require some reworking of the code to fit. This
also adds support for HV / HSRR type interrupts which will be used in
a later change.

Acked-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Message-ID: <20231216134257.1743345-16-npiggin@gmail.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>

show more ...

powerpc: Make interrupt handler error more readable

Installing the same handler twice reports a shifted trap vector
address which is hard to decipher. Print the unshifted address.

Signed-off-by: Ni

powerpc: Make interrupt handler error more readable

Installing the same handler twice reports a shifted trap vector
address which is hard to decipher. Print the unshifted address.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Message-ID: <20231216134257.1743345-14-npiggin@gmail.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>

show more ...

powerpc: Expand exception handler vector granularity

Exception handlers are currently indexed in units of 0x100, but
powerpc can have vectors that are aligned to as little as 0x20
bytes. Increase gr

powerpc: Expand exception handler vector granularity

Exception handlers are currently indexed in units of 0x100, but
powerpc can have vectors that are aligned to as little as 0x20
bytes. Increase granularity of the handler functions before
adding support for those vectors.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Message-ID: <20231216134257.1743345-15-npiggin@gmail.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>

show more ...

powerpc: Fix interrupt stack alignment

ppc64 requires the stack to be 16-byte aligned but the interrupt
stack frame has 8-byte aligned size. Add padding to fix.

Signed-off-by: Nicholas Piggin <npig

powerpc: Fix interrupt stack alignment

ppc64 requires the stack to be 16-byte aligned but the interrupt
stack frame has 8-byte aligned size. Add padding to fix.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Message-ID: <20231216134257.1743345-10-npiggin@gmail.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>

show more ...

powerpc/spapr_vpa: Add basic VPA tests

The VPA is an optional memory structure shared between the hypervisor
and operating system, defined by PAPR. This test defines the structure
and adds registrat

powerpc/spapr_vpa: Add basic VPA tests

The VPA is an optional memory structure shared between the hypervisor
and operating system, defined by PAPR. This test defines the structure
and adds registration, deregistration, and a few simple sanity tests.

[Thanks to Thomas Huth for suggesting many of the test cases.]

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20230608075826.86217-8-npiggin@gmail.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>

show more ...

powerpc: Extract some common helpers and defines to headers

Move some common helpers and defines to processor.h.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Message-Id: <20230608075826.86217

powerpc: Extract some common helpers and defines to headers

Move some common helpers and defines to processor.h.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Message-Id: <20230608075826.86217-6-npiggin@gmail.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>

show more ...

powerpc: Abstract H_CEDE calls into a sleep functions

This consolidates several implementations, and it no longer leaves
MSR[EE] enabled after the decrementer interrupt is handled, but
rather disabl

powerpc: Abstract H_CEDE calls into a sleep functions

This consolidates several implementations, and it no longer leaves
MSR[EE] enabled after the decrementer interrupt is handled, but
rather disables it on return.

The handler no longer allows a continuous ticking, but rather dec
has to be re-armed and EE re-enabled (e.g., via H_CEDE hcall) each
time.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Message-Id: <20230608075826.86217-4-npiggin@gmail.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>

show more ...