Merge branch 'arm/queue' into 'master'

arm/arm64: EFI support, arm64 backtrace support, PMU test improvements, and more

See merge request kvm-unit-tests/kvm-unit-tests!43

arm64: Add support for gic initialization through ACPI

In systems with ACPI support and when a DT is not provided, we can use
the MADTs to figure out if it implements a GICv2 or a GICv3 and
discover

arm64: Add support for gic initialization through ACPI

In systems with ACPI support and when a DT is not provided, we can use
the MADTs to figure out if it implements a GICv2 or a GICv3 and
discover the GIC parameters. This change implements this but retains
the default behavior; we check if a valid DT is provided, if not, we
try to discover the cores in the system using ACPI.

Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Signed-off-by: Andrew Jones <andrew.jones@linux.dev>

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Merge branch 'arm/queue' into 'master'

arm cleanups

See merge request kvm-unit-tests/kvm-unit-tests!41

arm: gic: Write one bit per time in gic_irq_set_clr_enable()

When use gic_irq_set_clr_enable() to disable an interrupt, it will
disable all interrupt since it first read from Interrupt Clear-Enable

arm: gic: Write one bit per time in gic_irq_set_clr_enable()

When use gic_irq_set_clr_enable() to disable an interrupt, it will
disable all interrupt since it first read from Interrupt Clear-Enable
Registers where '1' indicates that forwarding of the corresponding
interrupt is enabled and then write this value with a mask into
Interrupt Clear-Enable Registers where '1' indicates disable the
forwarding of the corresponding interrupt.

So directly write one bit per time to enable or disable interrupt.

Fixes: cb573c2 ("arm: gic: Introduce gic_irq_set_clr_enable() helper")
Signed-off-by: Shaoqin Huang <shahuang@redhat.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Zenghui Yu <yuzenghui@huawei.com>
Signed-off-by: Andrew Jones <andrew.jones@linux.dev>

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arm/arm64: ITS: Introspection tests

Detect the presence of an ITS as part of the GICv3 init
routine, initialize its base address and read few registers
the IIDR, the TYPER to store its dimensioning

arm/arm64: ITS: Introspection tests

Detect the presence of an ITS as part of the GICv3 init
routine, initialize its base address and read few registers
the IIDR, the TYPER to store its dimensioning parameters.
Parse the BASER registers. As part of the init sequence we
also init all the requested tables.

This is our first ITS test, belonging to a new "its" group.

Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Zenghui Yu <yuzenghui@huawei.com>
Signed-off-by: Andrew Jones <drjones@redhat.com>

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arm: gic: Introduce gic_irq_set_clr_enable() helper

Allows to set or clear the enable state of a PPI/SGI/SPI.

Signed-off-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Andrew Jones <drjones@

arm: gic: Introduce gic_irq_set_clr_enable() helper

Allows to set or clear the enable state of a PPI/SGI/SPI.

Signed-off-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Andrew Jones <drjones@redhat.com>

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arm64: timer: Speed up gic-timer-state check

Let's bail out of the wait loop if we see the expected state
to save over six seconds of run time. Make sure we wait a bit
before reading the registers a

arm64: timer: Speed up gic-timer-state check

Let's bail out of the wait loop if we see the expected state
to save over six seconds of run time. Make sure we wait a bit
before reading the registers and double check again after,
though, to somewhat mitigate the chance of seeing the expected
state by accident.

We also take this opportunity to push more IRQ state code to
the library.

Cc: Zenghui Yu <yuzenghui@huawei.com>
Reviewed-by: Zenghui Yu <yuzenghui@huawei.com>
Tested-by: Zenghui Yu <yuzenghui@huawei.com>
Reviewed-by: Alexandru Elisei <alexandru.elisei@arm.com>
Signed-off-by: Andrew Jones <drjones@redhat.com>

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arm/arm64: gicv3: support up to 8 redistributor regions

We need to support at least two redistributor regions in order to
support more than 123 vcpus (we select 8 because that should be
plenty). Als

arm/arm64: gicv3: support up to 8 redistributor regions

We need to support at least two redistributor regions in order to
support more than 123 vcpus (we select 8 because that should be
plenty). Also bump NR_CPUS to 512, since that's what KVM currently
supports.

Signed-off-by: Andrew Jones <drjones@redhat.com>
Tested-by: Christoffer Dall <christoffer.dall@arm.com>
Reviewed-by: Christoffer Dall <christoffer.dall@arm.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

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lib/arm/gic: gic_version cleanup

Remove version from ops as it's not an op, nor necessary.

Signed-off-by: Andrew Jones <drjones@redhat.com>
Message-Id: <20170525102849.22754-2-drjones@redhat.com>
S

lib/arm/gic: gic_version cleanup

Remove version from ops as it's not an op, nor necessary.

Signed-off-by: Andrew Jones <drjones@redhat.com>
Message-Id: <20170525102849.22754-2-drjones@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

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Merge tag 'for-master' of https://github.com/rhdrjones/kvm-unit-tests into HEAD

arm/arm64 patches ready for master

arm/arm64: gicv3: add an IPI test

Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andrew Jones <drjones@redhat.com>

arm/arm64: add initial gicv3 support

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Andrew Jones <drjones@redhat.com>

arm/arm64: add initial gicv2 support

Add some gicv2 support. This just adds init and enable
functions, allowing unit tests to start messing with it.

Reviewed-by: Andre Przywara <andre.przywara@arm.

arm/arm64: add initial gicv2 support

Add some gicv2 support. This just adds init and enable
functions, allowing unit tests to start messing with it.

Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Andrew Jones <drjones@redhat.com>

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