arm64: gic-v3: Avoid NULL dereferences

LPI allocation requires that the redistributors are configured first.
It's unlikely that offline cpus have had their redistributors
configured, so filter them

arm64: gic-v3: Avoid NULL dereferences

LPI allocation requires that the redistributors are configured first.
It's unlikely that offline cpus have had their redistributors
configured, so filter them out right away. Also, assert on any cpu,
not just the calling cpu, in gicv3_lpi_alloc_tables() when we detect
a unit test failed to follow instructions. Improve the assert with a
hint message while we're at it.

Cc: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-Id: <20211011160420.26785-1-drjones@redhat.com>
Signed-off-by: Andrew Jones <drjones@redhat.com>

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Merge branch 'arm/queue' into 'master'

arm/arm64: Fixes, improvements, and prep for target-efi

See merge request kvm-unit-tests/kvm-unit-tests!6

lib: arm/arm64: gicv3: Add missing barrier when sending IPIs

One common usage for IPIs is for one CPU to write to a shared memory
location, send the IPI to kick another CPU, and the receiver to read

lib: arm/arm64: gicv3: Add missing barrier when sending IPIs

One common usage for IPIs is for one CPU to write to a shared memory
location, send the IPI to kick another CPU, and the receiver to read from
the same location. Proper synchronization is needed to make sure that the
IPI receiver reads the most recent value and not stale data (for example,
the write from the sender CPU might still be in a store buffer).

For GICv3, IPIs are generated with a write to the ICC_SGI1R_EL1 register.
To make sure the memory stores are observable by other CPUs, we need a
wmb() barrier (DSB ST), which waits for stores to complete.

From the definition of DSB from ARM DDI 0487F.b, page B2-139:

"In addition, no instruction that appears in program order after the DSB
instruction can alter any state of the system or perform any part of its
functionality until the DSB completes other than:

- Being fetched from memory and decoded.
- Reading the general-purpose, SIMD and floating-point, Special-purpose, or
System registers that are directly or indirectly read without causing
side-effects."

Similar definition for armv7 (ARM DDI 0406C.d, page A3-150).

The DSB instruction is enough to prevent reordering of the GIC register
write which comes in program order after the memory access.

This also matches what the Linux GICv3 irqchip driver does (commit
21ec30c0ef52 ("irqchip/gic-v3: Use wmb() instead of smb_wmb() in
gic_raise_softirq()")).

Reviewed-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Alexandru Elisei <alexandru.elisei@arm.com>
Signed-off-by: Andrew Jones <drjones@redhat.com>

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arm/arm64: ITS: its_enable_defaults

its_enable_defaults() enable LPIs at redistributor level
and ITS level.

gicv3_enable_defaults must be called before.

Signed-off-by: Eric Auger <eric.auger@redha

arm/arm64: ITS: its_enable_defaults

its_enable_defaults() enable LPIs at redistributor level
and ITS level.

gicv3_enable_defaults must be called before.

Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Zenghui Yu <yuzenghui@huawei.com>
Signed-off-by: Andrew Jones <drjones@redhat.com>

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arm/arm64: gicv3: Set the LPI config and pending tables

Allocate the LPI configuration and per re-distributor pending table.
Set redistributor's PROPBASER and PENDBASER. The LPIs are enabled
by defa

arm/arm64: gicv3: Set the LPI config and pending tables

Allocate the LPI configuration and per re-distributor pending table.
Set redistributor's PROPBASER and PENDBASER. The LPIs are enabled
by default in the config table.

Also introduce a helper routine that allows to set the pending
table bit for a given LPI and macros to set/get its configuration.

Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Zenghui Yu <yuzenghui@huawei.com>
Signed-off-by: Andrew Jones <drjones@redhat.com>

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arm/arm64: gicv3: support up to 8 redistributor regions

We need to support at least two redistributor regions in order to
support more than 123 vcpus (we select 8 because that should be
plenty). Als

arm/arm64: gicv3: support up to 8 redistributor regions

We need to support at least two redistributor regions in order to
support more than 123 vcpus (we select 8 because that should be
plenty). Also bump NR_CPUS to 512, since that's what KVM currently
supports.

Signed-off-by: Andrew Jones <drjones@redhat.com>
Tested-by: Christoffer Dall <christoffer.dall@arm.com>
Reviewed-by: Christoffer Dall <christoffer.dall@arm.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

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Merge tag 'for-master' of https://github.com/rhdrjones/kvm-unit-tests into HEAD

arm/arm64 patches ready for master

arm/arm64: gicv3: add an IPI test

Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andrew Jones <drjones@redhat.com>

arm/arm64: add initial gicv3 support

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Andrew Jones <drjones@redhat.com>