build: Bump vfio and all the dependent crates to latest version

Recently vfio crates have moved to crates.io, thus we should start
consuming the crate from crates.io instead git url.

This results i

build: Bump vfio and all the dependent crates to latest version

Recently vfio crates have moved to crates.io, thus we should start
consuming the crate from crates.io instead git url.

This results in better versioning instead of tracking some git commit
sha.

Signed-off-by: Jinank Jain <jinankjain@microsoft.com>

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hypervisor: Basic implementation of setup_regs for MSHV ARM64 guests

As part of this configure the program counter, pstate and X0 registers.
Program counter will point to the start address of the ke

hypervisor: Basic implementation of setup_regs for MSHV ARM64 guests

As part of this configure the program counter, pstate and X0 registers.
Program counter will point to the start address of the kernel/firmware
in the guest memory. X0 will point to start of the FDT.

Signed-off-by: Jinank Jain <jinankjain@microsoft.com>

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hypervisor: Refactor common PSTATE register definition

Initial PSTATE value would be same for both KVM and MSHV. Thus, move it
to common register definition pool.

Signed-off-by: Jinank Jain <jinank

hypervisor: Refactor common PSTATE register definition

Initial PSTATE value would be same for both KVM and MSHV. Thus, move it
to common register definition pool.

Signed-off-by: Jinank Jain <jinankjain@microsoft.com>

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hypervisor: Avoid leaking KVM GIC state into common GIC state

KVM supports GICv3-ITS emulation and the current GicState is modelled
around the KVM implementation. We should refactor this to accomoda

hypervisor: Avoid leaking KVM GIC state into common GIC state

KVM supports GICv3-ITS emulation and the current GicState is modelled
around the KVM implementation. We should refactor this to accomodate
other hypervisor requirements. For example, MSHV only support GICv2M
emulation for guests for delivering MSI interrupts instead of GICv3-ITS.

Signed-off-by: Jinank Jain <jinankjain@microsoft.com>

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hypervisor: Simplify riscv64 set_regs implementation

Use `riscv64_set_one_reg_from_vcpu!` macro to simplify `set_regs` for
riscv64.

Signed-off-by: Ruoqing He <heruoqing@iscas.ac.cn>

hypervisor: Introduce riscv64_set_one_reg_to_vcpu macro

`riscv64_set_one_reg_to_vcpu` macro is used to set value of specific
RISC-V `$reg_name` stored in `state` to KVM Vcpu.

Signed-off-by: Ruoqing

hypervisor: Introduce riscv64_set_one_reg_to_vcpu macro

`riscv64_set_one_reg_to_vcpu` macro is used to set value of specific
RISC-V `$reg_name` stored in `state` to KVM Vcpu.

Signed-off-by: Ruoqing He <heruoqing@iscas.ac.cn>

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hypervisor: Simplify riscv64 get_regs implementation

Use `riscv64_get_one_reg_from_vcpu!` macro to simplify `get_regs` for
riscv64.

Signed-off-by: Ruoqing He <heruoqing@iscas.ac.cn>

hypervisor: Introduce riscv64_get_one_reg_from_vcpu macro

`riscv64_get_one_reg_from_vcpu` macro is used to extract RISC-V register
data from KVM Vcpu according to `$reg_name` provided to `state`.

S

hypervisor: Introduce riscv64_get_one_reg_from_vcpu macro

`riscv64_get_one_reg_from_vcpu` macro is used to extract RISC-V register
data from KVM Vcpu according to `$reg_name` provided to `state`.

Signed-off-by: Ruoqing He <heruoqing@iscas.ac.cn>

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hypervisor, vmm: Avoid leaking hypervisor specific data structure

Currently a bunch of KVM specific interfaces are leaked into the vmm
crate which should ideally does not contain any hypervisor spec

hypervisor, vmm: Avoid leaking hypervisor specific data structure

Currently a bunch of KVM specific interfaces are leaked into the vmm
crate which should ideally does not contain any hypervisor specific data
structures.

Signed-off-by: Jinank Jain <jinankjain@microsoft.com>

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hypervisor: Implement hypervisor agnostic variant of VcpuInit

This will help in fixing the build issue for MSHV on ARM64.

Signed-off-by: Jinank Jain <jinankjain@microsoft.com>

hypervisor: Implement hypervisor agnostic variant of RegList

This helps in unification of RegList across different platforms.

Signed-off-by: Jinank Jain <jinankjain@microsoft.com>

hypervisor: Implement hypervisor agnostic Register interface

This will help in fixing the build issue for MSHV on ARM64.

Signed-off-by: Jinank Jain <jinankjain@microsoft.com>

hypervisor: Automatically fix operator precedence clippy warning

Signed-off-by: Rob Bradford <rbradford@rivosinc.com>

hypervisor: use memory size during VM creation

For SEV-SNP VM on MSHV we need to request page access during
IO, we want to avoid such request for the page that have already
been requested. In order

hypervisor: use memory size during VM creation

For SEV-SNP VM on MSHV we need to request page access during
IO, we want to avoid such request for the page that have already
been requested. In order to maintain the bitmap we need the memory size
during bitmap creation.

Signed-off-by: Muminul Islam <muislam@microsoft.com>

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hypervisor: Set pc and a1 for all vcpu

It turns out we need to setup `a0`, `pc` and `a1` for all vcpus before
we run them, remove predicates used to set `pc` and `a1` for `vcpu0`.

Signed-off-by: Ru

hypervisor: Set pc and a1 for all vcpu

It turns out we need to setup `a0`, `pc` and `a1` for all vcpus before
we run them, remove predicates used to set `pc` and `a1` for `vcpu0`.

Signed-off-by: Ruoqing He <heruoqing@iscas.ac.cn>

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hypervisor: kvm: Add g/set_regs unit-test on riscv64

Add unit-test to make sure get_regs and set_regs on riscv64 architecture
work as expected, effectively avoiding typos in register names.

Signed-

hypervisor: kvm: Add g/set_regs unit-test on riscv64

Add unit-test to make sure get_regs and set_regs on riscv64 architecture
work as expected, effectively avoiding typos in register names.

Signed-off-by: Ruoqing He <heruoqing@iscas.ac.cn>

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hypervisor: kvm: Complement `create_standard_regs`

Complement `create_standard_regs` implementation on RISC-V platform to
work with `From` trait of `kvm_riscv_core`.

Signed-off-by: Ruoqing He <heru

hypervisor: kvm: Complement `create_standard_regs`

Complement `create_standard_regs` implementation on RISC-V platform to
work with `From` trait of `kvm_riscv_core`.

Signed-off-by: Ruoqing He <heruoqing@iscas.ac.cn>

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hypervisor: kvm: Integrate riscv64 regs & AIA

Incorporates riscv64 register interaction and AIA creation to kvm
module. Complete `Vcpu` trait on RISC-V platform.

Signed-off-by: Ruoqing He <heruoqin

hypervisor: kvm: Integrate riscv64 regs & AIA

Incorporates riscv64 register interaction and AIA creation to kvm
module. Complete `Vcpu` trait on RISC-V platform.

Signed-off-by: Ruoqing He <heruoqing@iscas.ac.cn>

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hypervisor: kvm: Introduce riscv64 register g/set

Implement macros to calculate register ID on riscv64, definition of
RISC-V `VcpuKvmState`.

Signed-off-by: Ruoqing He <heruoqing@iscas.ac.cn>

hypervisor: kvm: Expose create_standard_regs() for all architectures

The aarch64 unit tests make use of this.

Fixes commit 3645654c392f395a80f7cac329df204c6a9c94e2

Signed-off-by: Rob Bradford <rbr

hypervisor: kvm: Expose create_standard_regs() for all architectures

The aarch64 unit tests make use of this.

Fixes commit 3645654c392f395a80f7cac329df204c6a9c94e2

Signed-off-by: Rob Bradford <rbradford@rivosinc.com>

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misc: Further improve imports styling

By introducing `imports_granularity="Module"` format strategy,
effectively groups imports from the same module into one line or block,
improving maintainability

misc: Further improve imports styling

By introducing `imports_granularity="Module"` format strategy,
effectively groups imports from the same module into one line or block,
improving maintainability and readability.

Signed-off-by: Ruoqing He <heruoqing@iscas.ac.cn>

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misc: Adapt consistent import style formatting

Historically the Cloud Hypervisor coding style has been to ensure that
all imports are ordered and placed in a single group. Unfortunately
cargo fmt ha

misc: Adapt consistent import style formatting

Historically the Cloud Hypervisor coding style has been to ensure that
all imports are ordered and placed in a single group. Unfortunately
cargo fmt has no support for ensuring that all imports are in a single
group so if whitespace lines were added as part of the import statements
then they would only be odered correctly in the group.

By adopting "group_imports="StdExternalCrate" we can enforce a style
where imports are placed in at most three groups for std, external
crates and the crate itself. Choosing a style enforceable by the tooling
reduces the reviewer burden.

Signed-off-by: Rob Bradford <rbradford@rivosinc.com>

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hypervisor: cpu: Expand `Set/GetCoreRegisters` variant

Since RISC-V has its own definition of `CoreRegister`, expand the Aarch
variant to avoid collision of `HypervisorCpuError`.

Signed-off-by: Ruo

hypervisor: cpu: Expand `Set/GetCoreRegisters` variant

Since RISC-V has its own definition of `CoreRegister`, expand the Aarch
variant to avoid collision of `HypervisorCpuError`.

Signed-off-by: Ruoqing He <heruoqing@iscas.ac.cn>

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vmm: Add support for enabling SVE in vm guests

This change enables SVE automatically if the host support SVE/SVE2.

Signed-off-by: Wenyu Huang <huangwenyuu@outlook.com>

hypervisor: vmm: Switch to common StandardRegisters implementation

Use the StandardRegisters defined in the hypervisor crate instead of
re-defining it from MSHV/KVM crate.

Signed-off-by: Jinank Jai

hypervisor: vmm: Switch to common StandardRegisters implementation

Use the StandardRegisters defined in the hypervisor crate instead of
re-defining it from MSHV/KVM crate.

Signed-off-by: Jinank Jain <jinankjain@microsoft.com>

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