hypervisor: Set destination vCPU TSC frequency to source

Include the TSC frequency as part of the KVM state so that it will be
restored at the destination.

This ensures migration works correctly be

hypervisor: Set destination vCPU TSC frequency to source

Include the TSC frequency as part of the KVM state so that it will be
restored at the destination.

This ensures migration works correctly between hosts that have a
different TSC frequency if the guest is running with TSC as the source
of timekeeping.

Fixes: #5786

Signed-off-by: Rob Bradford <rbradford@rivosinc.com>

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misc: Fix various spelling errors using typos

This fixes all typos found by the typos utility with respect to the config file.

Signed-off-by: Philipp Schuster <philipp.schuster@cyberus-technology.d

misc: Fix various spelling errors using typos

This fixes all typos found by the typos utility with respect to the config file.

Signed-off-by: Philipp Schuster <philipp.schuster@cyberus-technology.de>

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hyperivsor: Add infrastructure to determine CPU vendor

Signed-off-by: Anatol Belski <anbelski@linux.microsoft.com>

arch, hypervisor: Populate CPUID leaf 0x4000_0010 (TSC frequency)

This hypervisor leaf includes details of the TSC frequency if that is
available from KVM. This can be used to efficiently calculate

arch, hypervisor: Populate CPUID leaf 0x4000_0010 (TSC frequency)

This hypervisor leaf includes details of the TSC frequency if that is
available from KVM. This can be used to efficiently calculate time
passed when there is an invariant TSC.

TEST=Run `cpuid` in the guest and observe the frequency populated.

Fixes: #5178

Signed-off-by: Rob Bradford <robert.bradford@intel.com>

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hypervisor: Fix a typo in error message

Signed-off-by: Jinank Jain <jinankjain@microsoft.com>

hypervisor: Support compiling "tdx" and "mshv" feature together

TDX functionality is not currently available on MSHV but we should not
preclude building a binary that can run on both.

Fixes: #4677

hypervisor: Support compiling "tdx" and "mshv" feature together

TDX functionality is not currently available on MSHV but we should not
preclude building a binary that can run on both.

Fixes: #4677

Signed-off-by: Rob Bradford <robert.bradford@intel.com>

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hypervisor: Enable gdb HW breakpoint on AArch64

Signed-off-by: Michael Zhao <michael.zhao@arm.com>

hypervisor: Remove `Vcpu::read_mpidr()` on AArch64

Replaced `read_mpidr()` with `get_sys_reg()`.

Signed-off-by: Michael Zhao <michael.zhao@arm.com>

hypervisor: Add `Vcpu::get_sys_reg()` on AArch64

Added function `Vcpu::get_sys_reg()` to get single system register.

Signed-off-by: Michael Zhao <michael.zhao@arm.com>

hypervisor: Remove `get/set_reg()` on AArch64

`Vcpu::get/set_reg()` were only invoked in Vcpu itself.

Signed-off-by: Michael Zhao <michael.zhao@arm.com>

hypervisor: Remove `get/set_sys_regs()` on AArch64

`hypervisor::Vcpu::get/set_sys_regs()` are only used in Vcpu internally.

Signed-off-by: Michael Zhao <michael.zhao@arm.com>

hypervisor: drop kvm guard from some Vcpu trait functions

And provide default implementations.

Signed-off-by: Wei Liu <liuwe@microsoft.com>

hypervisor: aarch64: drop set/has_vcpu_attr

This avoids the need for exposing DeviceAttr.

Signed-off-by: Wei Liu <liuwe@microsoft.com>

hypervisor, vmm: introduce trait functions for aarch64 PMU

The original code uses kvm_device_attr directly outside of the
hyeprvisor crate. That leaks hypervisor details.

No functional change inten

hypervisor, vmm: introduce trait functions for aarch64 PMU

The original code uses kvm_device_attr directly outside of the
hyeprvisor crate. That leaks hypervisor details.

No functional change intended.

Signed-off-by: Wei Liu <liuwe@microsoft.com>

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hypervisor: x86: provide a generic MsrEntry structure

Signed-off-by: Wei Liu <liuwe@microsoft.com>

hypervisor: move away from MsrEntries type

It is a flexible array. Switch to vector and slice instead.

No functional change intended.

Signed-off-by: Wei Liu <liuwe@microsoft.com>

hypervisor x86: provide a generic LapicState structure

This requires making get/set_lapic_reg part of the type.

For the moment we cannot provide a default variant for the new type,
because picking

hypervisor x86: provide a generic LapicState structure

This requires making get/set_lapic_reg part of the type.

For the moment we cannot provide a default variant for the new type,
because picking one will be wrong for the other hypervisor, so I just
drop the test cases that requires LapicState::default().

Signed-off-by: Wei Liu <liuwe@microsoft.com>

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hypervisor: x86: drop get/set VcpuEvents from vcpu trait

Signed-off-by: Wei Liu <liuwe@microsoft.com>

hypervisor: x86: drop get/set Xcrs from Vcpu trait

Signed-off-by: Wei Liu <liuwe@microsoft.com>

hypervisor: x86: drop get/set Xsave from Vcpu trait

They are only needed internally within the hypervisor crate.

Signed-off-by: Wei Liu <liuwe@microsoft.com>

hypervisor: provide a generic FpuState structure

Signed-off-by: Wei Liu <liuwe@microsoft.com>

hypervisor: provide a generic CpudIdEntry structure

Signed-off-by: Wei Liu <liuwe@microsoft.com>

hypervisor, vmm: move away from CpuId type

CpuId is an alias type for the flexible array structure type over
CpuIdEntry. The type itself and the type of the element in the array
portion are tied to

hypervisor, vmm: move away from CpuId type

CpuId is an alias type for the flexible array structure type over
CpuIdEntry. The type itself and the type of the element in the array
portion are tied to the underlying hypervisor.

Switch to using CpuIdEntry slice or vector directly. The construction of
CpuId type is left to hypervisors.

This allows us to decouple CpuIdEntry from hypervisors more easily.

No functional change intended.

Signed-off-by: Wei Liu <liuwe@microsoft.com>

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hypervisor: mshv: drop get_suspend_regs

It is not used (yet).

Signed-off-by: Wei Liu <liuwe@microsoft.com>

hypervisor: x86: provide a generic SpecialRegisters structure

Signed-off-by: Wei Liu <liuwe@microsoft.com>