misc: hypervisor: streamline error Display::fmt()

The changes were mostly automatically applied using the Python
script mentioned in the first commit of this series.

Signed-off-by: Philipp Schuster

misc: hypervisor: streamline error Display::fmt()

The changes were mostly automatically applied using the Python
script mentioned in the first commit of this series.

Signed-off-by: Philipp Schuster <philipp.schuster@cyberus-technology.de>
On-behalf-of: SAP philipp.schuster@sap.com

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vmm: hypervisor: Add a new interface to setup GICR for vcpus

For MSHV arm64 guest, there is an in-hypervisor GICv2M emulation and for
that to work, it needs to be enlightened with the base address o

vmm: hypervisor: Add a new interface to setup GICR for vcpus

For MSHV arm64 guest, there is an in-hypervisor GICv2M emulation and for
that to work, it needs to be enlightened with the base address of GIC
redistributor exposed to guest via FDT.

Signed-off-by: Jinank Jain <jinankjain@microsoft.com>

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hypervisor: Implement support for fetching sys regs on MSHV

ARM64 system register constants are not 1:1 mapped to MSHV definition of
those registers so we need a small helper function to translate t

hypervisor: Implement support for fetching sys regs on MSHV

ARM64 system register constants are not 1:1 mapped to MSHV definition of
those registers so we need a small helper function to translate that
mapping before retrieving those system registers.

Signed-off-by: Jinank Jain <jinankjain@microsoft.com>

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hypervisor, vmm: Avoid leaking hypervisor specific data structure

Currently a bunch of KVM specific interfaces are leaked into the vmm
crate which should ideally does not contain any hypervisor spec

hypervisor, vmm: Avoid leaking hypervisor specific data structure

Currently a bunch of KVM specific interfaces are leaked into the vmm
crate which should ideally does not contain any hypervisor specific data
structures.

Signed-off-by: Jinank Jain <jinankjain@microsoft.com>

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hypervisor: Implement hypervisor agnostic variant of VcpuInit

This will help in fixing the build issue for MSHV on ARM64.

Signed-off-by: Jinank Jain <jinankjain@microsoft.com>

hypervisor: Implement hypervisor agnostic variant of RegList

This helps in unification of RegList across different platforms.

Signed-off-by: Jinank Jain <jinankjain@microsoft.com>

hypervisor: cpu: Introduce RISC-V Vcpu trait

Add RISC-V specific Vcpu trait. Disable `set_guest_debug` on RISC-V
platform.

Signed-off-by: Ruoqing He <heruoqing@iscas.ac.cn>

hypervisor: cpu: Introduce RISC-V specific error

Add error variants specific to RISC-V architecture.

Signed-off-by: Ruoqing He <heruoqing@iscas.ac.cn>

misc: Further improve imports styling

By introducing `imports_granularity="Module"` format strategy,
effectively groups imports from the same module into one line or block,
improving maintainability

misc: Further improve imports styling

By introducing `imports_granularity="Module"` format strategy,
effectively groups imports from the same module into one line or block,
improving maintainability and readability.

Signed-off-by: Ruoqing He <heruoqing@iscas.ac.cn>

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misc: Adapt consistent import style formatting

Historically the Cloud Hypervisor coding style has been to ensure that
all imports are ordered and placed in a single group. Unfortunately
cargo fmt ha

misc: Adapt consistent import style formatting

Historically the Cloud Hypervisor coding style has been to ensure that
all imports are ordered and placed in a single group. Unfortunately
cargo fmt has no support for ensuring that all imports are in a single
group so if whitespace lines were added as part of the import statements
then they would only be odered correctly in the group.

By adopting "group_imports="StdExternalCrate" we can enforce a style
where imports are placed in at most three groups for std, external
crates and the crate itself. Choosing a style enforceable by the tooling
reduces the reviewer burden.

Signed-off-by: Rob Bradford <rbradford@rivosinc.com>

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hypervisor: cpu: Fix `GetRegList` comment

`GetRegList` variant will be referenced on both Aarch and RISC-V. Fixed
comment to generalize this error variant.

Signed-off-by: Ruoqing He <heruoqing@isca

hypervisor: cpu: Fix `GetRegList` comment

`GetRegList` variant will be referenced on both Aarch and RISC-V. Fixed
comment to generalize this error variant.

Signed-off-by: Ruoqing He <heruoqing@iscas.ac.cn>

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hypervisor: cpu: Expand `Set/GetCoreRegisters` variant

Since RISC-V has its own definition of `CoreRegister`, expand the Aarch
variant to avoid collision of `HypervisorCpuError`.

Signed-off-by: Ruo

hypervisor: cpu: Expand `Set/GetCoreRegisters` variant

Since RISC-V has its own definition of `CoreRegister`, expand the Aarch
variant to avoid collision of `HypervisorCpuError`.

Signed-off-by: Ruoqing He <heruoqing@iscas.ac.cn>

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hypervisor: cpu: Fix get/set one reg error message

The error message of `SetRegister` and `GetRegister` fail to describe
the reason as the error variant suggests. Fixed error message
accordingly.

S

hypervisor: cpu: Fix get/set one reg error message

The error message of `SetRegister` and `GetRegister` fail to describe
the reason as the error variant suggests. Fixed error message
accordingly.

Signed-off-by: Ruoqing He <heruoqing@iscas.ac.cn>

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vmm: Add support for enabling SVE in vm guests

This change enables SVE automatically if the host support SVE/SVE2.

Signed-off-by: Wenyu Huang <huangwenyuu@outlook.com>

hypervisor: vmm: Switch to common StandardRegisters implementation

Use the StandardRegisters defined in the hypervisor crate instead of
re-defining it from MSHV/KVM crate.

Signed-off-by: Jinank Jai

hypervisor: vmm: Switch to common StandardRegisters implementation

Use the StandardRegisters defined in the hypervisor crate instead of
re-defining it from MSHV/KVM crate.

Signed-off-by: Jinank Jain <jinankjain@microsoft.com>

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hypervisor: Switch to use the new StandardRegisters

With this we are removing the CloudHypervisor definition of
StandardRegisters instead using an enum which contains different
variants of StandardR

hypervisor: Switch to use the new StandardRegisters

With this we are removing the CloudHypervisor definition of
StandardRegisters instead using an enum which contains different
variants of StandardRegisters coming from their bindigs crate.

Signed-off-by: Jinank Jain <jinankjain@microsoft.com>

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hypervisor: Add an API to create default StandardRegisters

This will be used to create StandardRegisters for a given vcpu in
future.

Signed-off-by: Jinank Jain <jinankjain@microsoft.com>

hypervisor: Remove unused VmExit enum members

The members for {Io, Mmio}{Read, Write} are unused as instead exits of
those types are handled through the VmOps interface. Removing these is
also a pre

hypervisor: Remove unused VmExit enum members

The members for {Io, Mmio}{Read, Write} are unused as instead exits of
those types are handled through the VmOps interface. Removing these is
also a prerequisite due to changes in the mutability of the
VcpuFd::run() method.

Signed-off-by: Rob Bradford <rbradford@rivosinc.com>

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hypervisor: rework VP state components

On Microsoft Hypervisor, we need to save/restore five
VP state components which are as follows:
1. Local APIC
2. Xsave
3. Synthetic Message Page

hypervisor: rework VP state components

On Microsoft Hypervisor, we need to save/restore five
VP state components which are as follows:
1. Local APIC
2. Xsave
3. Synthetic Message Page
4. Synthetic Event Flags Page
5. Synthetic Timers

In the MSHV crate we created a single struct for all the
components and API to get/set the states.

Signed-off-by: Muminul Islam <muislam@microsoft.com>

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vmm: hypervisor: Add support for injecting NMI for MSHV guest

Currently, we only support injecting NMI for KVM guests but we can do
the same for MSHV guests as well to have feature parity.

Signed-o

vmm: hypervisor: Add support for injecting NMI for MSHV guest

Currently, we only support injecting NMI for KVM guests but we can do
the same for MSHV guests as well to have feature parity.

Signed-off-by: Jinank Jain <jinankjain@microsoft.com>

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vmm: support injecting NMI

Inject NMI interrupt when needed, by call ioctl KVM_NMI.

Signed-off-by: Yi Wang <foxywang@tencent.com>

hypervisor: Add api to set sev control register

This register configures the SEV feature control
state on a virtual processor.

Signed-off-by: Jinank Jain <jinankjain@microsoft.com>
Signed-off-by: M

hypervisor: Add api to set sev control register

This register configures the SEV feature control
state on a virtual processor.

Signed-off-by: Jinank Jain <jinankjain@microsoft.com>
Signed-off-by: Muminul Islam <muislam@microsoft.com>

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hypervisor: fix few typos and cosmetic issues

This patch adds missing new lines after functions,
fixes few typos in the comments, adds few missing
comments to SNP related functions.

Signed-off-by:

hypervisor: fix few typos and cosmetic issues

This patch adds missing new lines after functions,
fixes few typos in the comments, adds few missing
comments to SNP related functions.

Signed-off-by: Muminul Islam <muislam@microsoft.com>

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hypervisor: Add api to retrieve CPUID leaf

Add necessary API to retrieve cpuid leaf on MSHV.
This API is used to update cpuid information
during the parsing of the igvm file.

Microsoft hypervisor d

hypervisor: Add api to retrieve CPUID leaf

Add necessary API to retrieve cpuid leaf on MSHV.
This API is used to update cpuid information
during the parsing of the igvm file.

Microsoft hypervisor does not provide common
CpuID like KVM. That's why we need to call this API
during the IGVM parsing.

Signed-off-by: Muminul Islam <muislam@microsoft.com>

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hypervisor: Add support for handling #HV Doorbell Page

As part of this handling there are 4 different operations:

1. Getting the hypervisor preffered doorbell page GPA.
2. Informing hypervisor abou

hypervisor: Add support for handling #HV Doorbell Page

As part of this handling there are 4 different operations:

1. Getting the hypervisor preffered doorbell page GPA.
2. Informing hypervisor about the doorbell page chosen by the guest
3. Querying the GPA of the doorbell page
4. Clearing the GPA of the doorbell page from hypervisor

Signed-off-by: Jinank Jain <jinankjain@microsoft.com>
Signed-off-by: Muminul Islam <muislam@microsoft.com>

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