build: Bump vfio and all the dependent crates to latest version

Recently vfio crates have moved to crates.io, thus we should start
consuming the crate from crates.io instead git url.

This results i

build: Bump vfio and all the dependent crates to latest version

Recently vfio crates have moved to crates.io, thus we should start
consuming the crate from crates.io instead git url.

This results in better versioning instead of tracking some git commit
sha.

Signed-off-by: Jinank Jain <jinankjain@microsoft.com>

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misc: hypervisor: streamline error Display::fmt()

The changes were mostly automatically applied using the Python
script mentioned in the first commit of this series.

Signed-off-by: Philipp Schuster

misc: hypervisor: streamline error Display::fmt()

The changes were mostly automatically applied using the Python
script mentioned in the first commit of this series.

Signed-off-by: Philipp Schuster <philipp.schuster@cyberus-technology.de>
On-behalf-of: SAP philipp.schuster@sap.com

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misc: Fix missing lifetime syntax clippy warning

This was caught by the nightly compiler during cargo fuzz build.

error: lifetime flowing from input to output with different syntax can be confusing

misc: Fix missing lifetime syntax clippy warning

This was caught by the nightly compiler during cargo fuzz build.

error: lifetime flowing from input to output with different syntax can be confusing
--> /home/runner/work/cloud-hypervisor/cloud-hypervisor/hypervisor/src/arch/x86/emulator/mod.rs:493:26
|
493 | pub fn new(platform: &mut dyn PlatformEmulator<CpuState = T>) -> Emulator<T> {
| ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ----------- the lifetime gets resolved as `'_`
| |
| this lifetime flows to the output
|
= note: `-D mismatched-lifetime-syntaxes` implied by `-D warnings`
= help: to override `-D warnings` add `#[allow(mismatched_lifetime_syntaxes)]`
help: one option is to remove the lifetime for references and use the anonymous lifetime for paths
|
493 | pub fn new(platform: &mut dyn PlatformEmulator<CpuState = T>) -> Emulator<'_, T> {

Signed-off-by: Jinank Jain <jinankjain@microsoft.com>

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hypervisor: mshv: fix advance_rip_update_rax() helper

The dirty bit for the GP registers must be set for the hypervisor to
update them.

Signed-off-by: Nuno Das Neves <nunodasneves@linux.microsoft.c

hypervisor: mshv: fix advance_rip_update_rax() helper

The dirty bit for the GP registers must be set for the hypervisor to
update them.

Signed-off-by: Nuno Das Neves <nunodasneves@linux.microsoft.com>

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hypervisor: Fix issues with nightly compilers

cargo fuzz build complaints about some un-used function in the
instruction emultator. Silence the warning by allowing dead code
generation.

Signed-off-

hypervisor: Fix issues with nightly compilers

cargo fuzz build complaints about some un-used function in the
instruction emultator. Silence the warning by allowing dead code
generation.

Signed-off-by: Jinank Jain <jinankjain@microsoft.com>

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misc: Move zerocopy to workspace dependencies

Since it is used by multiple components at this point, it is better to
move it to workspace level dependency.

Signed-off-by: Jinank Jain <jinankjain@mi

misc: Move zerocopy to workspace dependencies

Since it is used by multiple components at this point, it is better to
move it to workspace level dependency.

Signed-off-by: Jinank Jain <jinankjain@microsoft.com>

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misc: streamline thiserror cargo dep

As almost every sub crate depends on thiserror, lets upgrade it to a
workspace dependency.

Signed-off-by: Philipp Schuster <philipp.schuster@cyberus-technology.

misc: streamline thiserror cargo dep

As almost every sub crate depends on thiserror, lets upgrade it to a
workspace dependency.

Signed-off-by: Philipp Schuster <philipp.schuster@cyberus-technology.de>
On-behalf-of: SAP philipp.schuster@sap.com

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misc: hypervisor: streamline #[source] and Error

This streamlines the code base to follow best practices for
error handling in Rust: Each error struct implements
std::error::Error (most due via this

misc: hypervisor: streamline #[source] and Error

This streamlines the code base to follow best practices for
error handling in Rust: Each error struct implements
std::error::Error (most due via thiserror::Error derive macro)
and sets its source accordingly.

This allows future work that nicely prints the error chains,
for example.

So far, the convention is that each error prints its
sub error as part of its Display::fmt() impl.

Signed-off-by: Philipp Schuster <philipp.schuster@cyberus-technology.de>
On-behalf-of: SAP philipp.schuster@sap.com

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misc: Fix beta clippy issues

Fixing the following clippy issue using `cargo clippy --fix`:

error: variables can be used directly in the `format!` string
--> build.rs:25:27
|
25 | versi

misc: Fix beta clippy issues

Fixing the following clippy issue using `cargo clippy --fix`:

error: variables can be used directly in the `format!` string
--> build.rs:25:27
|
25 | version.push_str(&format!("-{}", extra_version));
| ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
= help: for further information visit https://rust-lang.github.io/rust-clippy/master/index.html#uninlined_format_args

Signed-off-by: Bo Chen <bchen@crusoe.ai>

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hypervisor: mshv: Add missing implementation

Currently a lot of functions are stubbed out with unimplemented feature
tag. Add the missing implementation to successfully boot ARM64 guests on
MSHV.

S

hypervisor: mshv: Add missing implementation

Currently a lot of functions are stubbed out with unimplemented feature
tag. Add the missing implementation to successfully boot ARM64 guests on
MSHV.

Signed-off-by: Jinank Jain <jinankjain@microsoft.com>

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hypervisor: Set additional partition property for MSHV guest

For ARM64 guests we need to set three important partition property:

1) PPI interrupt ID for timer interrupt
2) PPI interrupt ID for PMU

hypervisor: Set additional partition property for MSHV guest

For ARM64 guests we need to set three important partition property:

1) PPI interrupt ID for timer interrupt
2) PPI interrupt ID for PMU interrupts.
3) Hiding LPI support from the guest because MSHV does emulate ITS for
the guest.

Signed-off-by: Jinank Jain <jinankjain@microsoft.com>

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hypervisor: arch: Move PMU IRQ definition from arch to hypervisor crate

Since this would be used in other places inside the hypervisor and
hypervisor crate cannot take a dependency on arch crate, as

hypervisor: arch: Move PMU IRQ definition from arch to hypervisor crate

Since this would be used in other places inside the hypervisor and
hypervisor crate cannot take a dependency on arch crate, as that creates
cyclic dependency.

Signed-off-by: Jinank Jain <jinankjain@microsoft.com>

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arch: hypervisor: Define PPI constants for ARM arch timer

Currently PPI interrupt ID are hardcoded as numbers, it would be ideal
to define them as constants and could be reused in other parts of the

arch: hypervisor: Define PPI constants for ARM arch timer

Currently PPI interrupt ID are hardcoded as numbers, it would be ideal
to define them as constants and could be reused in other parts of the
hypervisor crate.

Signed-off-by: Jinank Jain <jinankjain@microsoft.com>

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build: Bump mshv crates from 0.4.0 to 0.5.0

Along with also bump the vfio-bindings crates to use the latest
mshv-bindings.

There is a breaking change in the new mshv crate which requires an
additio

build: Bump mshv crates from 0.4.0 to 0.5.0

Along with also bump the vfio-bindings crates to use the latest
mshv-bindings.

There is a breaking change in the new mshv crate which requires an
additional step to initialize vm after creating it.

Signed-off-by: Jinank Jain <jinankjain@microsoft.com>

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hypervisor: Extend interrupt handling for legacy IRQ

On x86 MSHV guests only used to support MSI based interrupts via IOAPIC
but ARM64 guests uses legacy interrupt for its functioning. Thus, extend

hypervisor: Extend interrupt handling for legacy IRQ

On x86 MSHV guests only used to support MSI based interrupts via IOAPIC
but ARM64 guests uses legacy interrupt for its functioning. Thus, extend
the logic to create routing entry to support legacy interrupts for ARM64
guests on MSHV.

Signed-off-by: Jinank Jain <jinankjain@microsoft.com>

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vmm: hypervisor: Add a new interface to setup GICR for vcpus

For MSHV arm64 guest, there is an in-hypervisor GICv2M emulation and for
that to work, it needs to be enlightened with the base address o

vmm: hypervisor: Add a new interface to setup GICR for vcpus

For MSHV arm64 guest, there is an in-hypervisor GICv2M emulation and for
that to work, it needs to be enlightened with the base address of GIC
redistributor exposed to guest via FDT.

Signed-off-by: Jinank Jain <jinankjain@microsoft.com>

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hypervisor: Implement support for fetching sys regs on MSHV

ARM64 system register constants are not 1:1 mapped to MSHV definition of
those registers so we need a small helper function to translate t

hypervisor: Implement support for fetching sys regs on MSHV

ARM64 system register constants are not 1:1 mapped to MSHV definition of
those registers so we need a small helper function to translate that
mapping before retrieving those system registers.

Signed-off-by: Jinank Jain <jinankjain@microsoft.com>

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hypervisor: arch: Move common regs from arch to hypervisor crate

There are other potential users of these registers definitions in the
hypervisor crate. And hypervisor crate cannot use definitions f

hypervisor: arch: Move common regs from arch to hypervisor crate

There are other potential users of these registers definitions in the
hypervisor crate. And hypervisor crate cannot use definitions from arch
crate because it creates cyclic dependency.

Signed-off-by: Jinank Jain <jinankjain@microsoft.com>

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hypervisor: mshv: advance_rip_rax after port handle

Call function to advance RIP and RAX after handling the
port.

Signed-off-by: Muminul Islam <muislam@microsoft.com>

hypervisor: mshv: function to advance RIP and RAX

A separate function to advance RIP and RAX based on
register page.

Signed-off-by: Muminul Islam <muislam@microsoft.com>

hypervisor: mshv: get_msr_list return vector instead fam-wrapper

New MSHV version updates the get_msr_list output as
vector instead of fam-wrapper. It avoids unnecessary
conversions.

Signed-off-by:

hypervisor: mshv: get_msr_list return vector instead fam-wrapper

New MSHV version updates the get_msr_list output as
vector instead of fam-wrapper. It avoids unnecessary
conversions.

Signed-off-by: Muminul Islam <muislam@microsoft.com>

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hypervisor: mshv: fix clippy warnings for latest mshv crates

Signed-off-by: Muminul Islam <muislam@microsoft.com>

hypervisor: mshv: use mapped register page for port handling

MSHV allows VMM to map the VP register page into root.
This feature helps VMM to faster process most of the frequent
used registers. This

hypervisor: mshv: use mapped register page for port handling

MSHV allows VMM to map the VP register page into root.
This feature helps VMM to faster process most of the frequent
used registers. This patch uses the VP register page for port
handling in CPU run method.

Signed-off-by: Muminul Islam <muislam@microsoft.com>

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hypervisor: Basic implementation of setup_regs for MSHV ARM64 guests

As part of this configure the program counter, pstate and X0 registers.
Program counter will point to the start address of the ke

hypervisor: Basic implementation of setup_regs for MSHV ARM64 guests

As part of this configure the program counter, pstate and X0 registers.
Program counter will point to the start address of the kernel/firmware
in the guest memory. X0 will point to start of the FDT.

Signed-off-by: Jinank Jain <jinankjain@microsoft.com>

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hypervisor: Configure VGIC for MSHV guests

As part of this configuration, two things are being done:

1. Setting up the base address of GIC Distributor
2. Setting up the base address of GIC Interrup

hypervisor: Configure VGIC for MSHV guests

As part of this configuration, two things are being done:

1. Setting up the base address of GIC Distributor
2. Setting up the base address of GIC Interrupt Translator

Signed-off-by: Jinank Jain <jinankjain@microsoft.com>

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