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1b91aa8e |
| 21-May-2025 |
Philipp Schuster <philipp.schuster@cyberus-technology.de> |
misc: devices: streamline error Display::fmt()
The changes were mostly automatically applied using the Python script mentioned in the first commit of this series.
Signed-off-by: Philipp Schuster <p
misc: devices: streamline error Display::fmt()
The changes were mostly automatically applied using the Python script mentioned in the first commit of this series.
Signed-off-by: Philipp Schuster <philipp.schuster@cyberus-technology.de> On-behalf-of: SAP philipp.schuster@sap.com
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ab575a54 |
| 21-May-2025 |
Philipp Schuster <philipp.schuster@cyberus-technology.de> |
misc: devices: streamline #[source] and Error impl
This streamlines the Error implementation in the Cloud Hypervisor code base to match the remaining parts so that everything follows the agreed conv
misc: devices: streamline #[source] and Error impl
This streamlines the Error implementation in the Cloud Hypervisor code base to match the remaining parts so that everything follows the agreed conventions. These are leftovers missed in the previous commits.
Signed-off-by: Philipp Schuster <philipp.schuster@cyberus-technology.de> On-behalf-of: SAP philipp.schuster@sap.com
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93b599e5 |
| 19-May-2025 |
Philipp Schuster <philipp.schuster@cyberus-technology.de> |
misc: devices: streamline #[source] and Error
This streamlines the code base to follow best practices for error handling in Rust: Each error struct implements std::error::Error (most due via thiserr
misc: devices: streamline #[source] and Error
This streamlines the code base to follow best practices for error handling in Rust: Each error struct implements std::error::Error (most due via thiserror::Error derive macro) and sets its source accordingly.
This allows future work that nicely prints the error chains, for example.
So far, the convention is that each error prints its sub error as part of its Display::fmt() impl.
Signed-off-by: Philipp Schuster <philipp.schuster@cyberus-technology.de> On-behalf-of: SAP philipp.schuster@sap.com
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e8c330e2 |
| 04-Dec-2024 |
Ruoqing He <heruoqing@iscas.ac.cn> |
devices: Introduce RISC-V AIA interrupt device
Introduce definitions, implementations and error variants of RISC-V AIA (Advance Interrupt Architecture) interrupt controller.
Signed-off-by: Ruoqing
devices: Introduce RISC-V AIA interrupt device
Introduce definitions, implementations and error variants of RISC-V AIA (Advance Interrupt Architecture) interrupt controller.
Signed-off-by: Ruoqing He <heruoqing@iscas.ac.cn>
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61e57e1c |
| 29-Sep-2024 |
Ruoqing He <heruoqing@iscas.ac.cn> |
misc: Further improve imports styling
By introducing `imports_granularity="Module"` format strategy, effectively groups imports from the same module into one line or block, improving maintainability
misc: Further improve imports styling
By introducing `imports_granularity="Module"` format strategy, effectively groups imports from the same module into one line or block, improving maintainability and readability.
Signed-off-by: Ruoqing He <heruoqing@iscas.ac.cn>
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88a9f799 |
| 29-Sep-2024 |
Rob Bradford <rbradford@rivosinc.com> |
misc: Adapt consistent import style formatting
Historically the Cloud Hypervisor coding style has been to ensure that all imports are ordered and placed in a single group. Unfortunately cargo fmt ha
misc: Adapt consistent import style formatting
Historically the Cloud Hypervisor coding style has been to ensure that all imports are ordered and placed in a single group. Unfortunately cargo fmt has no support for ensuring that all imports are in a single group so if whitespace lines were added as part of the import statements then they would only be odered correctly in the group.
By adopting "group_imports="StdExternalCrate" we can enforce a style where imports are placed in at most three groups for std, external crates and the crate itself. Choosing a style enforceable by the tooling reduces the reviewer burden.
Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
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89b429c7 |
| 03-May-2024 |
SamrutGadde <samrut.gadde@gmail.com> |
devices: Use thiserror for errors
Updated error enums in device package to use thiserror crate
Signed-off-by: SamrutGadde <samrut.gadde@gmail.com>
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b173f6f6 |
| 29-Nov-2022 |
Michael Zhao <michael.zhao@arm.com> |
vmm,devices: Change Gic snapshot and restore path
The snapshot and restore of AArch64 Gic was done in Vm. Now it is moved to DeviceManager.
The benefit is that the restore can be done while the Gic
vmm,devices: Change Gic snapshot and restore path
The snapshot and restore of AArch64 Gic was done in Vm. Now it is moved to DeviceManager.
The benefit is that the restore can be done while the Gic is created in DeviceManager.
While the moving of state data from Vm snapshot to DeviceManager snapshot breaks the compatability of migration from older versions.
Signed-off-by: Michael Zhao <michael.zhao@arm.com>
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7d16c740 |
| 06-Nov-2022 |
Michael Zhao <michael.zhao@arm.com> |
vmm: Refactor AArch64 GIC initialization process
In the new process, `device::Gic::new()` covers additional actions: 1. Creating `hypervisor::vGic` 2. Initializing interrupt routings
The change mak
vmm: Refactor AArch64 GIC initialization process
In the new process, `device::Gic::new()` covers additional actions: 1. Creating `hypervisor::vGic` 2. Initializing interrupt routings
The change makes the vGic device ready in the beginning of `DeviceManager::create_devices()`. This can unblock the GIC related devices initialization in the `DeviceManager`.
Signed-off-by: Michael Zhao <michael.zhao@arm.com>
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957d3a74 |
| 01-Jun-2022 |
Michael Zhao <michael.zhao@arm.com> |
aarch64: Simplify GIC related structs definition
Combined the `GicDevice` struct in `arch` crate and the `Gic` struct in `devices` crate.
After moving the KVM specific code for GIC in `arch`, a ver
aarch64: Simplify GIC related structs definition
Combined the `GicDevice` struct in `arch` crate and the `Gic` struct in `devices` crate.
After moving the KVM specific code for GIC in `arch`, a very thin wapper layer `GicDevice` was left in `arch` crate. It is easy to combine it with the `Gic` in `devices` crate.
Signed-off-by: Michael Zhao <michael.zhao@arm.com>
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3bd47ffd |
| 09-Feb-2021 |
Sebastien Boeuf <sebastien.boeuf@intel.com> |
interrupt: Add a notifier method to the InterruptController
Both GIC and IOAPIC must implement a new method notifier() in order to provide the caller with an EventFd corresponding to the IRQ it refe
interrupt: Add a notifier method to the InterruptController
Both GIC and IOAPIC must implement a new method notifier() in order to provide the caller with an EventFd corresponding to the IRQ it refers to.
This is needed in anticipation for supporting INTx with VFIO PCI devices.
Signed-off-by: Sebastien Boeuf <sebastien.boeuf@intel.com>
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9dffc5da |
| 01-Oct-2020 |
Sebastien Boeuf <sebastien.boeuf@intel.com> |
devices: ioapic: Always retrieve destination field on 8 bits
When the destination mode is physical, the destination field should only be defined through bits 56-59, as defined in the IOAPIC spec. Bu
devices: ioapic: Always retrieve destination field on 8 bits
When the destination mode is physical, the destination field should only be defined through bits 56-59, as defined in the IOAPIC spec. But from the APIC specification, the APIC ID is always defined on 8 bits no matter which destination mode is selected. That's why we always retrieve the destination field based on bits 56-63.
Signed-off-by: Sebastien Boeuf <sebastien.boeuf@intel.com>
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8f1f9d9e |
| 25-May-2020 |
Michael Zhao <michael.zhao@arm.com> |
devices: Implement InterruptController on AArch64
This commit only implements the InterruptController crate on AArch64. The device specific part for GIC is to be added.
Signed-off-by: Michael Zhao
devices: Implement InterruptController on AArch64
This commit only implements the InterruptController crate on AArch64. The device specific part for GIC is to be added.
Signed-off-by: Michael Zhao <michael.zhao@arm.com>
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b32d3025 |
| 25-May-2020 |
Michael Zhao <michael.zhao@arm.com> |
devices: Refactor IOAPIC to cover other architectures
IOAPIC, a X86 specific interrupt controller, is referenced by device manager and CPU manager. To work with more architectures, a common type for
devices: Refactor IOAPIC to cover other architectures
IOAPIC, a X86 specific interrupt controller, is referenced by device manager and CPU manager. To work with more architectures, a common type for all architectures is needed. This commit introduces trait InterruptController to provide architecture agnostic functions. Device manager and CPU manager can use it without caring what the underlying device is.
Signed-off-by: Michael Zhao <michael.zhao@arm.com>
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