xref: /src/sys/dev/rge/if_rgevar.h (revision bc531a96c9b28b1cabcd5deb0c9f8f6d815cfebc)
1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause
3  *
4  * Copyright (c) 2019, 2020, 2025 Kevin Lo <kevlo@openbsd.org>
5  *
6  * Permission to use, copy, modify, and distribute this software for any
7  * purpose with or without fee is hereby granted, provided that the above
8  * copyright notice and this permission notice appear in all copies.
9  *
10  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17  */
18 
19 /*	$OpenBSD: if_rgereg.h,v 1.15 2025/09/19 00:41:14 kevlo Exp $	*/
20 
21 #ifndef	__IF_RGEVAR_H__
22 #define	__IF_RGEVAR_H__
23 
24 #define	RGE_LOCK(sc)		(mtx_lock(&sc->sc_mtx))
25 #define	RGE_UNLOCK(sc)		(mtx_unlock(&sc->sc_mtx))
26 #define	RGE_ASSERT_LOCKED(sc)	(mtx_assert(&sc->sc_mtx, MA_OWNED))
27 #define	RGE_ASSERT_UNLOCKED(sc)	(mtx_assert(&sc->sc_mtx, MA_NOTOWNED))
28 
29 enum rge_mac_type {
30 	MAC_UNKNOWN = 1,
31 	MAC_R25,
32 	MAC_R25B,
33 	MAC_R25D_1,
34 	MAC_R25D_2,
35 	MAC_R26_1,
36 	MAC_R26_2,
37 	MAC_R27
38 };
39 
40 struct rge_drv_stats {
41 	/* How many times if_transmit() was called */
42 	uint64_t		transmit_call_cnt;
43 	/* Transmitted frame failed because the interface was stopped */
44 	uint64_t		transmit_stopped_cnt;
45 	/* Transmitted frame failed because the TX queue is full */
46 	uint64_t		transmit_full_cnt;
47 	/* How many transmit frames were queued for transmit */
48 	uint64_t		transmit_queued_cnt;
49 
50 	/* How many times the interrupt routine was called */
51 	uint64_t		intr_cnt;
52 	/* How many times SYSTEM_ERR was set, requiring a hardware reset */
53 	uint64_t		intr_system_err_cnt;
54 	/* How many times rge_rxeof was called */
55 	uint64_t		rxeof_cnt;
56 	/* How many times rge_txeof was called */
57 	uint64_t		txeof_cnt;
58 
59 	/* How many times the link state changed */
60 	uint64_t		link_state_change_cnt;
61 
62 	/* How many times tx_task was run */
63 	uint64_t		tx_task_cnt;
64 
65 	/* Count of frames passed up into if_input() */
66 	uint64_t		recv_input_cnt;
67 
68 	/*
69 	 * For now - driver doesn't support multi descriptor
70 	 * RX frames; so count if it happens so it'll be noticed.
71 	 */
72 	uint64_t		rx_desc_err_multidesc;
73 
74 	/*
75 	 * Number of TX watchdog timeouts.
76 	 */
77 	uint64_t		tx_watchdog_timeout_cnt;
78 
79 	uint64_t		tx_encap_cnt;
80 	uint64_t		tx_encap_refrag_cnt;
81 	uint64_t		tx_encap_err_toofrag;
82 	uint64_t		tx_offload_ip_csum_set;
83 	uint64_t		tx_offload_tcp_csum_set;
84 	uint64_t		tx_offload_udp_csum_set;
85 	uint64_t		tx_offload_vlan_tag_set;
86 
87 	uint64_t		rx_ether_csum_err;
88 	uint64_t		rx_desc_jumbo_frag;
89 	uint64_t		rx_offload_vlan_tag;
90 	uint64_t		rx_offload_csum_ipv4_exists;
91 	uint64_t		rx_offload_csum_ipv4_valid;
92 
93 	uint64_t		rx_offload_csum_tcp_exists;
94 	uint64_t		rx_offload_csum_tcp_valid;
95 
96 	uint64_t		rx_offload_csum_udp_exists;
97 	uint64_t		rx_offload_csum_udp_valid;
98 };
99 
100 struct rge_txq {
101 	struct mbuf		*txq_mbuf;
102 	bus_dmamap_t		txq_dmamap;
103 	int			txq_descidx;
104 };
105 
106 struct rge_rxq {
107 	struct mbuf		*rxq_mbuf;
108 	bus_dmamap_t		rxq_dmamap;
109 };
110 
111 struct rge_tx {
112 	struct rge_txq		rge_txq[RGE_TX_LIST_CNT];
113 	int			rge_txq_prodidx;
114 	int			rge_txq_considx;
115 
116 	bus_addr_t		rge_tx_list_paddr;
117 	bus_dmamap_t		rge_tx_list_map;
118 	struct rge_tx_desc	*rge_tx_list;
119 };
120 
121 struct rge_rx {
122 	struct rge_rxq		rge_rxq[RGE_RX_LIST_CNT];
123 	int			rge_rxq_prodidx;
124 	int			rge_rxq_considx;
125 
126 //	struct if_rxring	rge_rx_ring;
127 	bus_addr_t		rge_rx_list_paddr;
128 	bus_dmamap_t		rge_rx_list_map;
129 	struct rge_rx_desc	*rge_rx_list;
130 
131 	struct mbuf		*rge_head;
132 	struct mbuf		**rge_tail;
133 };
134 
135 struct rge_queues {
136 	struct rge_softc	*q_sc;
137 	void			*q_ihc;
138 	int			q_index;
139 	char			q_name[16];
140 //	pci_intr_handle_t	q_ih;
141 	struct rge_tx		q_tx;
142 	struct rge_rx		q_rx;
143 };
144 
145 struct rge_mac_stats {
146 	bus_addr_t		paddr;
147 	bus_dmamap_t		map;
148 	/* NIC dma buffer, NIC order */
149 	struct rge_hw_mac_stats	*stats;
150 
151 	/* Local copy for retrieval, host order */
152 	struct rge_hw_mac_stats	lcl_stats;
153 };
154 
155 struct rge_softc {
156 	device_t		sc_dev;
157 	if_t			sc_ifp;		/* Ethernet common data */
158 	bool			sc_ether_attached;
159 	struct mtx		sc_mtx;
160 	struct resource		*sc_irq[RGE_MSI_MESSAGES];
161 	void			*sc_ih[RGE_MSI_MESSAGES];
162 	uint32_t		sc_expcap;	/* PCe exp cap */
163 	struct resource		*sc_bres;	/* bus space MMIO/IOPORT resource */
164 	bus_space_handle_t	rge_bhandle;	/* bus space handle */
165 	bus_space_tag_t		rge_btag;	/* bus space tag */
166 	bus_size_t		rge_bsize;
167 	bus_dma_tag_t		sc_dmat;
168 	bus_dma_tag_t		sc_dmat_tx_desc;
169 	bus_dma_tag_t		sc_dmat_tx_buf;
170 	bus_dma_tag_t		sc_dmat_rx_desc;
171 	bus_dma_tag_t		sc_dmat_rx_buf;
172 	bus_dma_tag_t		sc_dmat_stats_buf;
173 
174 //	pci_chipset_tag_t	sc_pc;
175 //	pcitag_t		sc_tag;
176 	struct ifmedia		sc_media;	/* media info */
177 	enum rge_mac_type	rge_type;
178 
179 	struct rge_queues	*sc_queues;
180 	unsigned int		sc_nqueues;
181 
182 	bool			sc_detaching;
183 	bool			sc_stopped;
184 	bool			sc_suspended;
185 
186 	/* Note: these likely should be per-TXQ */
187 	struct mbufq		sc_txq;
188 	struct taskqueue *	sc_tq;
189 	char			sc_tq_name[32];
190 	char			sc_tq_thr_name[32];
191 	struct task		sc_tx_task;
192 
193 	struct callout		sc_timeout;	/* 1 second tick */
194 
195 	uint64_t		rge_mcodever;
196 	uint16_t		rge_rcodever;
197 	uint32_t		rge_flags;
198 #define RGE_FLAG_MSI		0x00000001
199 #define RGE_FLAG_PCIE		0x00000002
200 
201 	uint32_t		rge_intrs;
202 	int			rge_timerintr;
203 #define RGE_IMTYPE_NONE		0
204 #define RGE_IMTYPE_SIM		1
205 	int			sc_watchdog;
206 
207 	uint32_t		sc_debug;
208 
209 	struct rge_drv_stats	sc_drv_stats;
210 
211 	struct rge_mac_stats	sc_mac_stats;
212 };
213 
214 /*
215  * Register space access macros.
216  */
217 #define RGE_WRITE_4(sc, reg, val)	\
218 	bus_space_write_4(sc->rge_btag, sc->rge_bhandle, reg, val)
219 #define RGE_WRITE_2(sc, reg, val)	\
220 	bus_space_write_2(sc->rge_btag, sc->rge_bhandle, reg, val)
221 #define RGE_WRITE_1(sc, reg, val)	\
222 	bus_space_write_1(sc->rge_btag, sc->rge_bhandle, reg, val)
223 
224 #define	RGE_WRITE_BARRIER_4(sc, reg)					\
225 	bus_space_barrier(sc->rge_btag, sc->rge_bhandle, reg, 4,	\
226 	    BUS_SPACE_BARRIER_WRITE)
227 #define	RGE_READ_BARRIER_4(sc, reg)					\
228 	bus_space_barrier(sc->rge_btag, sc->rge_bhandle, reg, 4,	\
229 	    BUS_SPACE_BARRIER_READ)
230 
231 
232 #define RGE_READ_4(sc, reg)		\
233 	bus_space_read_4(sc->rge_btag, sc->rge_bhandle, reg)
234 #define RGE_READ_2(sc, reg)		\
235 	bus_space_read_2(sc->rge_btag, sc->rge_bhandle, reg)
236 #define RGE_READ_1(sc, reg)		\
237 	bus_space_read_1(sc->rge_btag, sc->rge_bhandle, reg)
238 
239 #define RGE_SETBIT_4(sc, reg, val)	\
240 	RGE_WRITE_4(sc, reg, RGE_READ_4(sc, reg) | (val))
241 #define RGE_SETBIT_2(sc, reg, val)	\
242 	RGE_WRITE_2(sc, reg, RGE_READ_2(sc, reg) | (val))
243 #define RGE_SETBIT_1(sc, reg, val)	\
244 	RGE_WRITE_1(sc, reg, RGE_READ_1(sc, reg) | (val))
245 
246 #define RGE_CLRBIT_4(sc, reg, val)	\
247 	RGE_WRITE_4(sc, reg, RGE_READ_4(sc, reg) & ~(val))
248 #define RGE_CLRBIT_2(sc, reg, val)	\
249 	RGE_WRITE_2(sc, reg, RGE_READ_2(sc, reg) & ~(val))
250 #define RGE_CLRBIT_1(sc, reg, val)	\
251 	RGE_WRITE_1(sc, reg, RGE_READ_1(sc, reg) & ~(val))
252 
253 #define RGE_EPHY_SETBIT(sc, reg, val)	\
254 	rge_write_ephy(sc, reg, rge_read_ephy(sc, reg) | (val))
255 
256 #define RGE_EPHY_CLRBIT(sc, reg, val)	\
257 	rge_write_ephy(sc, reg, rge_read_ephy(sc, reg) & ~(val))
258 
259 #define RGE_PHY_SETBIT(sc, reg, val)	\
260 	rge_write_phy_ocp(sc, reg, rge_read_phy_ocp(sc, reg) | (val))
261 
262 #define RGE_PHY_CLRBIT(sc, reg, val)	\
263 	rge_write_phy_ocp(sc, reg, rge_read_phy_ocp(sc, reg) & ~(val))
264 
265 #define RGE_MAC_SETBIT(sc, reg, val)	\
266 	rge_write_mac_ocp(sc, reg, rge_read_mac_ocp(sc, reg) | (val))
267 
268 #define RGE_MAC_CLRBIT(sc, reg, val)	\
269 	rge_write_mac_ocp(sc, reg, rge_read_mac_ocp(sc, reg) & ~(val))
270 
271 #endif	/* __IF_RGEVAR_H__ */
272