1 /****************************************************************************** 2 3 Copyright (c) 2001-2009, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 /* 36 * 82562G 10/100 Network Connection 37 * 82562G-2 10/100 Network Connection 38 * 82562GT 10/100 Network Connection 39 * 82562GT-2 10/100 Network Connection 40 * 82562V 10/100 Network Connection 41 * 82562V-2 10/100 Network Connection 42 * 82566DC-2 Gigabit Network Connection 43 * 82566DC Gigabit Network Connection 44 * 82566DM-2 Gigabit Network Connection 45 * 82566DM Gigabit Network Connection 46 * 82566MC Gigabit Network Connection 47 * 82566MM Gigabit Network Connection 48 * 82567LM Gigabit Network Connection 49 * 82567LF Gigabit Network Connection 50 * 82567V Gigabit Network Connection 51 * 82567LM-2 Gigabit Network Connection 52 * 82567LF-2 Gigabit Network Connection 53 * 82567V-2 Gigabit Network Connection 54 * 82567LF-3 Gigabit Network Connection 55 * 82567LM-3 Gigabit Network Connection 56 * 82567LM-4 Gigabit Network Connection 57 */ 58 59 #include "e1000_api.h" 60 61 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw); 62 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw); 63 static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw); 64 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw); 65 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw); 66 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw); 67 static s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw); 68 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw); 69 static s32 e1000_phy_force_speed_duplex_ich8lan(struct e1000_hw *hw); 70 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw); 71 static s32 e1000_get_phy_info_ich8lan(struct e1000_hw *hw); 72 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, 73 bool active); 74 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, 75 bool active); 76 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, 77 u16 words, u16 *data); 78 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, 79 u16 words, u16 *data); 80 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw); 81 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw); 82 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, 83 u16 *data); 84 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw); 85 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw); 86 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw); 87 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw); 88 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw); 89 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, 90 u16 *speed, u16 *duplex); 91 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw); 92 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw); 93 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw); 94 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw); 95 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank); 96 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout); 97 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw); 98 static s32 e1000_get_phy_info_ife_ich8lan(struct e1000_hw *hw); 99 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw); 100 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw); 101 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, 102 u32 offset, u8 *data); 103 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 104 u8 size, u16 *data); 105 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, 106 u32 offset, u16 *data); 107 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, 108 u32 offset, u8 byte); 109 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, 110 u32 offset, u8 data); 111 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 112 u8 size, u16 data); 113 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw); 114 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw); 115 116 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */ 117 /* Offset 04h HSFSTS */ 118 union ich8_hws_flash_status { 119 struct ich8_hsfsts { 120 u16 flcdone :1; /* bit 0 Flash Cycle Done */ 121 u16 flcerr :1; /* bit 1 Flash Cycle Error */ 122 u16 dael :1; /* bit 2 Direct Access error Log */ 123 u16 berasesz :2; /* bit 4:3 Sector Erase Size */ 124 u16 flcinprog :1; /* bit 5 flash cycle in Progress */ 125 u16 reserved1 :2; /* bit 13:6 Reserved */ 126 u16 reserved2 :6; /* bit 13:6 Reserved */ 127 u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */ 128 u16 flockdn :1; /* bit 15 Flash Config Lock-Down */ 129 } hsf_status; 130 u16 regval; 131 }; 132 133 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */ 134 /* Offset 06h FLCTL */ 135 union ich8_hws_flash_ctrl { 136 struct ich8_hsflctl { 137 u16 flcgo :1; /* 0 Flash Cycle Go */ 138 u16 flcycle :2; /* 2:1 Flash Cycle */ 139 u16 reserved :5; /* 7:3 Reserved */ 140 u16 fldbcount :2; /* 9:8 Flash Data Byte Count */ 141 u16 flockdn :6; /* 15:10 Reserved */ 142 } hsf_ctrl; 143 u16 regval; 144 }; 145 146 /* ICH Flash Region Access Permissions */ 147 union ich8_hws_flash_regacc { 148 struct ich8_flracc { 149 u32 grra :8; /* 0:7 GbE region Read Access */ 150 u32 grwa :8; /* 8:15 GbE region Write Access */ 151 u32 gmrag :8; /* 23:16 GbE Master Read Access Grant */ 152 u32 gmwag :8; /* 31:24 GbE Master Write Access Grant */ 153 } hsf_flregacc; 154 u16 regval; 155 }; 156 157 /** 158 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers 159 * @hw: pointer to the HW structure 160 * 161 * Initialize family-specific PHY parameters and function pointers. 162 **/ 163 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw) 164 { 165 struct e1000_phy_info *phy = &hw->phy; 166 s32 ret_val = E1000_SUCCESS; 167 u16 i = 0; 168 169 DEBUGFUNC("e1000_init_phy_params_ich8lan"); 170 171 phy->addr = 1; 172 phy->reset_delay_us = 100; 173 174 phy->ops.acquire = e1000_acquire_swflag_ich8lan; 175 phy->ops.check_polarity = e1000_check_polarity_ife_ich8lan; 176 phy->ops.check_reset_block = e1000_check_reset_block_ich8lan; 177 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ich8lan; 178 phy->ops.get_cable_length = e1000_get_cable_length_igp_2; 179 phy->ops.get_cfg_done = e1000_get_cfg_done_ich8lan; 180 phy->ops.get_info = e1000_get_phy_info_ich8lan; 181 phy->ops.read_reg = e1000_read_phy_reg_igp; 182 phy->ops.release = e1000_release_swflag_ich8lan; 183 phy->ops.reset = e1000_phy_hw_reset_ich8lan; 184 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan; 185 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan; 186 phy->ops.write_reg = e1000_write_phy_reg_igp; 187 phy->ops.power_up = e1000_power_up_phy_copper; 188 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan; 189 190 /* 191 * We may need to do this twice - once for IGP and if that fails, 192 * we'll set BM func pointers and try again 193 */ 194 ret_val = e1000_determine_phy_address(hw); 195 if (ret_val) { 196 phy->ops.write_reg = e1000_write_phy_reg_bm; 197 phy->ops.read_reg = e1000_read_phy_reg_bm; 198 ret_val = e1000_determine_phy_address(hw); 199 if (ret_val) { 200 DEBUGOUT("Cannot determine PHY addr. Erroring out\n"); 201 goto out; 202 } 203 } 204 205 phy->id = 0; 206 while ((e1000_phy_unknown == e1000_get_phy_type_from_id(phy->id)) && 207 (i++ < 100)) { 208 msec_delay(1); 209 ret_val = e1000_get_phy_id(hw); 210 if (ret_val) 211 goto out; 212 } 213 214 /* Verify phy id */ 215 switch (phy->id) { 216 case IGP03E1000_E_PHY_ID: 217 phy->type = e1000_phy_igp_3; 218 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 219 break; 220 case IFE_E_PHY_ID: 221 case IFE_PLUS_E_PHY_ID: 222 case IFE_C_E_PHY_ID: 223 phy->type = e1000_phy_ife; 224 phy->autoneg_mask = E1000_ALL_NOT_GIG; 225 break; 226 case BME1000_E_PHY_ID: 227 phy->type = e1000_phy_bm; 228 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 229 phy->ops.read_reg = e1000_read_phy_reg_bm; 230 phy->ops.write_reg = e1000_write_phy_reg_bm; 231 phy->ops.commit = e1000_phy_sw_reset_generic; 232 break; 233 default: 234 ret_val = -E1000_ERR_PHY; 235 goto out; 236 } 237 238 out: 239 return ret_val; 240 } 241 242 /** 243 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers 244 * @hw: pointer to the HW structure 245 * 246 * Initialize family-specific NVM parameters and function 247 * pointers. 248 **/ 249 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw) 250 { 251 struct e1000_nvm_info *nvm = &hw->nvm; 252 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 253 u32 gfpreg, sector_base_addr, sector_end_addr; 254 s32 ret_val = E1000_SUCCESS; 255 u16 i; 256 257 DEBUGFUNC("e1000_init_nvm_params_ich8lan"); 258 259 /* Can't read flash registers if the register set isn't mapped. */ 260 if (!hw->flash_address) { 261 DEBUGOUT("ERROR: Flash registers not mapped\n"); 262 ret_val = -E1000_ERR_CONFIG; 263 goto out; 264 } 265 266 nvm->type = e1000_nvm_flash_sw; 267 268 gfpreg = E1000_READ_FLASH_REG(hw, ICH_FLASH_GFPREG); 269 270 /* 271 * sector_X_addr is a "sector"-aligned address (4096 bytes) 272 * Add 1 to sector_end_addr since this sector is included in 273 * the overall size. 274 */ 275 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK; 276 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1; 277 278 /* flash_base_addr is byte-aligned */ 279 nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT; 280 281 /* 282 * find total size of the NVM, then cut in half since the total 283 * size represents two separate NVM banks. 284 */ 285 nvm->flash_bank_size = (sector_end_addr - sector_base_addr) 286 << FLASH_SECTOR_ADDR_SHIFT; 287 nvm->flash_bank_size /= 2; 288 /* Adjust to word count */ 289 nvm->flash_bank_size /= sizeof(u16); 290 291 nvm->word_size = E1000_SHADOW_RAM_WORDS; 292 293 /* Clear shadow ram */ 294 for (i = 0; i < nvm->word_size; i++) { 295 dev_spec->shadow_ram[i].modified = FALSE; 296 dev_spec->shadow_ram[i].value = 0xFFFF; 297 } 298 299 /* Function Pointers */ 300 nvm->ops.acquire = e1000_acquire_swflag_ich8lan; 301 nvm->ops.read = e1000_read_nvm_ich8lan; 302 nvm->ops.release = e1000_release_swflag_ich8lan; 303 nvm->ops.update = e1000_update_nvm_checksum_ich8lan; 304 nvm->ops.valid_led_default = e1000_valid_led_default_ich8lan; 305 nvm->ops.validate = e1000_validate_nvm_checksum_ich8lan; 306 nvm->ops.write = e1000_write_nvm_ich8lan; 307 308 out: 309 return ret_val; 310 } 311 312 /** 313 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers 314 * @hw: pointer to the HW structure 315 * 316 * Initialize family-specific MAC parameters and function 317 * pointers. 318 **/ 319 static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw) 320 { 321 struct e1000_mac_info *mac = &hw->mac; 322 #if defined(NAHUM4) && !defined(NO_PCH_A_SUPPORT) 323 u16 pci_cfg; 324 #endif 325 326 DEBUGFUNC("e1000_init_mac_params_ich8lan"); 327 328 /* Set media type function pointer */ 329 hw->phy.media_type = e1000_media_type_copper; 330 331 /* Set mta register count */ 332 mac->mta_reg_count = 32; 333 /* Set rar entry count */ 334 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES; 335 if (mac->type == e1000_ich8lan) 336 mac->rar_entry_count--; 337 /* Set if part includes ASF firmware */ 338 mac->asf_firmware_present = TRUE; 339 /* Set if manageability features are enabled. */ 340 mac->arc_subsystem_valid = TRUE; 341 342 /* Function pointers */ 343 344 /* bus type/speed/width */ 345 mac->ops.get_bus_info = e1000_get_bus_info_ich8lan; 346 /* function id */ 347 mac->ops.set_lan_id = e1000_set_lan_id_single_port; 348 /* reset */ 349 mac->ops.reset_hw = e1000_reset_hw_ich8lan; 350 /* hw initialization */ 351 mac->ops.init_hw = e1000_init_hw_ich8lan; 352 /* link setup */ 353 mac->ops.setup_link = e1000_setup_link_ich8lan; 354 /* physical interface setup */ 355 mac->ops.setup_physical_interface = e1000_setup_copper_link_ich8lan; 356 /* check for link */ 357 mac->ops.check_for_link = e1000_check_for_copper_link_generic; 358 /* check management mode */ 359 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan; 360 /* link info */ 361 mac->ops.get_link_up_info = e1000_get_link_up_info_ich8lan; 362 /* multicast address update */ 363 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic; 364 /* setting MTA */ 365 mac->ops.mta_set = e1000_mta_set_generic; 366 /* clear hardware counters */ 367 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan; 368 369 /* LED operations */ 370 switch (mac->type) { 371 case e1000_ich8lan: 372 case e1000_ich9lan: 373 case e1000_ich10lan: 374 /* ID LED init */ 375 mac->ops.id_led_init = e1000_id_led_init_generic; 376 /* blink LED */ 377 mac->ops.blink_led = e1000_blink_led_generic; 378 /* setup LED */ 379 mac->ops.setup_led = e1000_setup_led_generic; 380 /* cleanup LED */ 381 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan; 382 /* turn on/off LED */ 383 mac->ops.led_on = e1000_led_on_ich8lan; 384 mac->ops.led_off = e1000_led_off_ich8lan; 385 break; 386 default: 387 break; 388 } 389 390 /* Enable PCS Lock-loss workaround for ICH8 */ 391 if (mac->type == e1000_ich8lan) 392 e1000_set_kmrn_lock_loss_workaround_ich8lan(hw, TRUE); 393 394 395 return E1000_SUCCESS; 396 } 397 398 /** 399 * e1000_init_function_pointers_ich8lan - Initialize ICH8 function pointers 400 * @hw: pointer to the HW structure 401 * 402 * Initialize family-specific function pointers for PHY, MAC, and NVM. 403 **/ 404 void e1000_init_function_pointers_ich8lan(struct e1000_hw *hw) 405 { 406 DEBUGFUNC("e1000_init_function_pointers_ich8lan"); 407 408 hw->mac.ops.init_params = e1000_init_mac_params_ich8lan; 409 hw->nvm.ops.init_params = e1000_init_nvm_params_ich8lan; 410 hw->phy.ops.init_params = e1000_init_phy_params_ich8lan; 411 } 412 413 /** 414 * e1000_acquire_swflag_ich8lan - Acquire software control flag 415 * @hw: pointer to the HW structure 416 * 417 * Acquires the software control flag for performing NVM and PHY 418 * operations. This is a function pointer entry point only called by 419 * read/write routines for the PHY and NVM parts. 420 **/ 421 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw) 422 { 423 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT; 424 s32 ret_val = E1000_SUCCESS; 425 426 DEBUGFUNC("e1000_acquire_swflag_ich8lan"); 427 428 while (timeout) { 429 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 430 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG; 431 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); 432 433 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 434 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) 435 break; 436 msec_delay_irq(1); 437 timeout--; 438 } 439 440 if (!timeout) { 441 DEBUGOUT("FW or HW has locked the resource for too long.\n"); 442 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; 443 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); 444 ret_val = -E1000_ERR_CONFIG; 445 goto out; 446 } 447 448 out: 449 return ret_val; 450 } 451 452 /** 453 * e1000_release_swflag_ich8lan - Release software control flag 454 * @hw: pointer to the HW structure 455 * 456 * Releases the software control flag for performing NVM and PHY operations. 457 * This is a function pointer entry point only called by read/write 458 * routines for the PHY and NVM parts. 459 **/ 460 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw) 461 { 462 u32 extcnf_ctrl; 463 464 DEBUGFUNC("e1000_release_swflag_ich8lan"); 465 466 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 467 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; 468 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); 469 470 return; 471 } 472 473 /** 474 * e1000_check_mng_mode_ich8lan - Checks management mode 475 * @hw: pointer to the HW structure 476 * 477 * This checks if the adapter has manageability enabled. 478 * This is a function pointer entry point only called by read/write 479 * routines for the PHY and NVM parts. 480 **/ 481 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw) 482 { 483 u32 fwsm; 484 485 DEBUGFUNC("e1000_check_mng_mode_ich8lan"); 486 487 fwsm = E1000_READ_REG(hw, E1000_FWSM); 488 489 return (fwsm & E1000_FWSM_MODE_MASK) == 490 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT); 491 } 492 493 /** 494 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked 495 * @hw: pointer to the HW structure 496 * 497 * Checks if firmware is blocking the reset of the PHY. 498 * This is a function pointer entry point only called by 499 * reset routines. 500 **/ 501 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw) 502 { 503 u32 fwsm; 504 505 DEBUGFUNC("e1000_check_reset_block_ich8lan"); 506 507 fwsm = E1000_READ_REG(hw, E1000_FWSM); 508 509 return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? E1000_SUCCESS 510 : E1000_BLK_PHY_RESET; 511 } 512 513 /** 514 * e1000_phy_force_speed_duplex_ich8lan - Force PHY speed & duplex 515 * @hw: pointer to the HW structure 516 * 517 * Forces the speed and duplex settings of the PHY. 518 * This is a function pointer entry point only called by 519 * PHY setup routines. 520 **/ 521 static s32 e1000_phy_force_speed_duplex_ich8lan(struct e1000_hw *hw) 522 { 523 struct e1000_phy_info *phy = &hw->phy; 524 s32 ret_val; 525 u16 data; 526 bool link; 527 528 DEBUGFUNC("e1000_phy_force_speed_duplex_ich8lan"); 529 530 if (phy->type != e1000_phy_ife) { 531 ret_val = e1000_phy_force_speed_duplex_igp(hw); 532 goto out; 533 } 534 535 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &data); 536 if (ret_val) 537 goto out; 538 539 e1000_phy_force_speed_duplex_setup(hw, &data); 540 541 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, data); 542 if (ret_val) 543 goto out; 544 545 /* Disable MDI-X support for 10/100 */ 546 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data); 547 if (ret_val) 548 goto out; 549 550 data &= ~IFE_PMC_AUTO_MDIX; 551 data &= ~IFE_PMC_FORCE_MDIX; 552 553 ret_val = phy->ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, data); 554 if (ret_val) 555 goto out; 556 557 DEBUGOUT1("IFE PMC: %X\n", data); 558 559 usec_delay(1); 560 561 if (phy->autoneg_wait_to_complete) { 562 DEBUGOUT("Waiting for forced speed/duplex link on IFE phy.\n"); 563 564 ret_val = e1000_phy_has_link_generic(hw, 565 PHY_FORCE_LIMIT, 566 100000, 567 &link); 568 if (ret_val) 569 goto out; 570 571 if (!link) 572 DEBUGOUT("Link taking longer than expected.\n"); 573 574 /* Try once more */ 575 ret_val = e1000_phy_has_link_generic(hw, 576 PHY_FORCE_LIMIT, 577 100000, 578 &link); 579 if (ret_val) 580 goto out; 581 } 582 583 out: 584 return ret_val; 585 } 586 587 /** 588 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset 589 * @hw: pointer to the HW structure 590 * 591 * Resets the PHY 592 * This is a function pointer entry point called by drivers 593 * or other shared routines. 594 **/ 595 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw) 596 { 597 struct e1000_phy_info *phy = &hw->phy; 598 u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask; 599 s32 ret_val; 600 u16 loop = E1000_ICH8_LAN_INIT_TIMEOUT; 601 u16 word_addr, reg_data, reg_addr, phy_page = 0; 602 603 DEBUGFUNC("e1000_phy_hw_reset_ich8lan"); 604 605 ret_val = e1000_phy_hw_reset_generic(hw); 606 if (ret_val) 607 goto out; 608 609 /* 610 * Initialize the PHY from the NVM on ICH platforms. This 611 * is needed due to an issue where the NVM configuration is 612 * not properly autoloaded after power transitions. 613 * Therefore, after each PHY reset, we will load the 614 * configuration data out of the NVM manually. 615 */ 616 if (hw->mac.type == e1000_ich8lan && phy->type == e1000_phy_igp_3) { 617 /* Check if SW needs configure the PHY */ 618 if ((hw->device_id == E1000_DEV_ID_ICH8_IGP_M_AMT) || 619 (hw->device_id == E1000_DEV_ID_ICH8_IGP_M)) 620 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M; 621 else 622 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG; 623 624 data = E1000_READ_REG(hw, E1000_FEXTNVM); 625 if (!(data & sw_cfg_mask)) 626 goto out; 627 628 /* Wait for basic configuration completes before proceeding*/ 629 do { 630 data = E1000_READ_REG(hw, E1000_STATUS); 631 data &= E1000_STATUS_LAN_INIT_DONE; 632 usec_delay(100); 633 } while ((!data) && --loop); 634 635 /* 636 * If basic configuration is incomplete before the above loop 637 * count reaches 0, loading the configuration from NVM will 638 * leave the PHY in a bad state possibly resulting in no link. 639 */ 640 if (loop == 0) 641 DEBUGOUT("LAN_INIT_DONE not set, increase timeout\n"); 642 643 /* Clear the Init Done bit for the next init event */ 644 data = E1000_READ_REG(hw, E1000_STATUS); 645 data &= ~E1000_STATUS_LAN_INIT_DONE; 646 E1000_WRITE_REG(hw, E1000_STATUS, data); 647 648 /* 649 * Make sure HW does not configure LCD from PHY 650 * extended configuration before SW configuration 651 */ 652 data = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 653 if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE) 654 goto out; 655 656 cnf_size = E1000_READ_REG(hw, E1000_EXTCNF_SIZE); 657 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK; 658 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT; 659 if (!cnf_size) 660 goto out; 661 662 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK; 663 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT; 664 665 /* Configure LCD from extended configuration region. */ 666 667 /* cnf_base_addr is in DWORD */ 668 word_addr = (u16)(cnf_base_addr << 1); 669 670 for (i = 0; i < cnf_size; i++) { 671 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2), 1, 672 ®_data); 673 if (ret_val) 674 goto out; 675 676 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2 + 1), 677 1, ®_addr); 678 if (ret_val) 679 goto out; 680 681 /* Save off the PHY page for future writes. */ 682 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) { 683 phy_page = reg_data; 684 continue; 685 } 686 687 reg_addr |= phy_page; 688 689 ret_val = phy->ops.write_reg(hw, (u32)reg_addr, reg_data); 690 if (ret_val) 691 goto out; 692 } 693 } 694 695 out: 696 return ret_val; 697 } 698 699 /** 700 * e1000_get_phy_info_ich8lan - Calls appropriate PHY type get_phy_info 701 * @hw: pointer to the HW structure 702 * 703 * Wrapper for calling the get_phy_info routines for the appropriate phy type. 704 **/ 705 static s32 e1000_get_phy_info_ich8lan(struct e1000_hw *hw) 706 { 707 s32 ret_val = -E1000_ERR_PHY_TYPE; 708 709 DEBUGFUNC("e1000_get_phy_info_ich8lan"); 710 711 switch (hw->phy.type) { 712 case e1000_phy_ife: 713 ret_val = e1000_get_phy_info_ife_ich8lan(hw); 714 break; 715 case e1000_phy_igp_3: 716 case e1000_phy_bm: 717 ret_val = e1000_get_phy_info_igp(hw); 718 break; 719 default: 720 break; 721 } 722 723 return ret_val; 724 } 725 726 /** 727 * e1000_get_phy_info_ife_ich8lan - Retrieves various IFE PHY states 728 * @hw: pointer to the HW structure 729 * 730 * Populates "phy" structure with various feature states. 731 * This function is only called by other family-specific 732 * routines. 733 **/ 734 static s32 e1000_get_phy_info_ife_ich8lan(struct e1000_hw *hw) 735 { 736 struct e1000_phy_info *phy = &hw->phy; 737 s32 ret_val; 738 u16 data; 739 bool link; 740 741 DEBUGFUNC("e1000_get_phy_info_ife_ich8lan"); 742 743 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 744 if (ret_val) 745 goto out; 746 747 if (!link) { 748 DEBUGOUT("Phy info is only valid if link is up\n"); 749 ret_val = -E1000_ERR_CONFIG; 750 goto out; 751 } 752 753 ret_val = phy->ops.read_reg(hw, IFE_PHY_SPECIAL_CONTROL, &data); 754 if (ret_val) 755 goto out; 756 phy->polarity_correction = (data & IFE_PSC_AUTO_POLARITY_DISABLE) 757 ? FALSE : TRUE; 758 759 if (phy->polarity_correction) { 760 ret_val = e1000_check_polarity_ife_ich8lan(hw); 761 if (ret_val) 762 goto out; 763 } else { 764 /* Polarity is forced */ 765 phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY) 766 ? e1000_rev_polarity_reversed 767 : e1000_rev_polarity_normal; 768 } 769 770 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data); 771 if (ret_val) 772 goto out; 773 774 phy->is_mdix = (data & IFE_PMC_MDIX_STATUS) ? TRUE : FALSE; 775 776 /* The following parameters are undefined for 10/100 operation. */ 777 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 778 phy->local_rx = e1000_1000t_rx_status_undefined; 779 phy->remote_rx = e1000_1000t_rx_status_undefined; 780 781 out: 782 return ret_val; 783 } 784 785 /** 786 * e1000_check_polarity_ife_ich8lan - Check cable polarity for IFE PHY 787 * @hw: pointer to the HW structure 788 * 789 * Polarity is determined on the polarity reversal feature being enabled. 790 * This function is only called by other family-specific 791 * routines. 792 **/ 793 static s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw) 794 { 795 struct e1000_phy_info *phy = &hw->phy; 796 s32 ret_val; 797 u16 phy_data, offset, mask; 798 799 DEBUGFUNC("e1000_check_polarity_ife_ich8lan"); 800 801 /* 802 * Polarity is determined based on the reversal feature being enabled. 803 */ 804 if (phy->polarity_correction) { 805 offset = IFE_PHY_EXTENDED_STATUS_CONTROL; 806 mask = IFE_PESC_POLARITY_REVERSED; 807 } else { 808 offset = IFE_PHY_SPECIAL_CONTROL; 809 mask = IFE_PSC_FORCE_POLARITY; 810 } 811 812 ret_val = phy->ops.read_reg(hw, offset, &phy_data); 813 814 if (!ret_val) 815 phy->cable_polarity = (phy_data & mask) 816 ? e1000_rev_polarity_reversed 817 : e1000_rev_polarity_normal; 818 819 return ret_val; 820 } 821 822 /** 823 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state 824 * @hw: pointer to the HW structure 825 * @active: TRUE to enable LPLU, FALSE to disable 826 * 827 * Sets the LPLU D0 state according to the active flag. When 828 * activating LPLU this function also disables smart speed 829 * and vice versa. LPLU will not be activated unless the 830 * device autonegotiation advertisement meets standards of 831 * either 10 or 10/100 or 10/100/1000 at all duplexes. 832 * This is a function pointer entry point only called by 833 * PHY setup routines. 834 **/ 835 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active) 836 { 837 struct e1000_phy_info *phy = &hw->phy; 838 u32 phy_ctrl; 839 s32 ret_val = E1000_SUCCESS; 840 u16 data; 841 842 DEBUGFUNC("e1000_set_d0_lplu_state_ich8lan"); 843 844 if (phy->type == e1000_phy_ife) 845 goto out; 846 847 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL); 848 849 if (active) { 850 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; 851 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 852 853 /* 854 * Call gig speed drop workaround on LPLU before accessing 855 * any PHY registers 856 */ 857 if ((hw->mac.type == e1000_ich8lan) && 858 (hw->phy.type == e1000_phy_igp_3)) 859 e1000_gig_downshift_workaround_ich8lan(hw); 860 861 /* When LPLU is enabled, we should disable SmartSpeed */ 862 ret_val = phy->ops.read_reg(hw, 863 IGP01E1000_PHY_PORT_CONFIG, 864 &data); 865 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 866 ret_val = phy->ops.write_reg(hw, 867 IGP01E1000_PHY_PORT_CONFIG, 868 data); 869 if (ret_val) 870 goto out; 871 } else { 872 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; 873 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 874 875 /* 876 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 877 * during Dx states where the power conservation is most 878 * important. During driver activity we should enable 879 * SmartSpeed, so performance is maintained. 880 */ 881 if (phy->smart_speed == e1000_smart_speed_on) { 882 ret_val = phy->ops.read_reg(hw, 883 IGP01E1000_PHY_PORT_CONFIG, 884 &data); 885 if (ret_val) 886 goto out; 887 888 data |= IGP01E1000_PSCFR_SMART_SPEED; 889 ret_val = phy->ops.write_reg(hw, 890 IGP01E1000_PHY_PORT_CONFIG, 891 data); 892 if (ret_val) 893 goto out; 894 } else if (phy->smart_speed == e1000_smart_speed_off) { 895 ret_val = phy->ops.read_reg(hw, 896 IGP01E1000_PHY_PORT_CONFIG, 897 &data); 898 if (ret_val) 899 goto out; 900 901 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 902 ret_val = phy->ops.write_reg(hw, 903 IGP01E1000_PHY_PORT_CONFIG, 904 data); 905 if (ret_val) 906 goto out; 907 } 908 } 909 910 out: 911 return ret_val; 912 } 913 914 /** 915 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state 916 * @hw: pointer to the HW structure 917 * @active: TRUE to enable LPLU, FALSE to disable 918 * 919 * Sets the LPLU D3 state according to the active flag. When 920 * activating LPLU this function also disables smart speed 921 * and vice versa. LPLU will not be activated unless the 922 * device autonegotiation advertisement meets standards of 923 * either 10 or 10/100 or 10/100/1000 at all duplexes. 924 * This is a function pointer entry point only called by 925 * PHY setup routines. 926 **/ 927 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active) 928 { 929 struct e1000_phy_info *phy = &hw->phy; 930 u32 phy_ctrl; 931 s32 ret_val = E1000_SUCCESS; 932 u16 data; 933 934 DEBUGFUNC("e1000_set_d3_lplu_state_ich8lan"); 935 936 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL); 937 938 if (!active) { 939 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU; 940 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 941 /* 942 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 943 * during Dx states where the power conservation is most 944 * important. During driver activity we should enable 945 * SmartSpeed, so performance is maintained. 946 */ 947 if (phy->smart_speed == e1000_smart_speed_on) { 948 ret_val = phy->ops.read_reg(hw, 949 IGP01E1000_PHY_PORT_CONFIG, 950 &data); 951 if (ret_val) 952 goto out; 953 954 data |= IGP01E1000_PSCFR_SMART_SPEED; 955 ret_val = phy->ops.write_reg(hw, 956 IGP01E1000_PHY_PORT_CONFIG, 957 data); 958 if (ret_val) 959 goto out; 960 } else if (phy->smart_speed == e1000_smart_speed_off) { 961 ret_val = phy->ops.read_reg(hw, 962 IGP01E1000_PHY_PORT_CONFIG, 963 &data); 964 if (ret_val) 965 goto out; 966 967 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 968 ret_val = phy->ops.write_reg(hw, 969 IGP01E1000_PHY_PORT_CONFIG, 970 data); 971 if (ret_val) 972 goto out; 973 } 974 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 975 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 976 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 977 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; 978 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 979 980 /* 981 * Call gig speed drop workaround on LPLU before accessing 982 * any PHY registers 983 */ 984 if ((hw->mac.type == e1000_ich8lan) && 985 (hw->phy.type == e1000_phy_igp_3)) 986 e1000_gig_downshift_workaround_ich8lan(hw); 987 988 /* When LPLU is enabled, we should disable SmartSpeed */ 989 ret_val = phy->ops.read_reg(hw, 990 IGP01E1000_PHY_PORT_CONFIG, 991 &data); 992 if (ret_val) 993 goto out; 994 995 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 996 ret_val = phy->ops.write_reg(hw, 997 IGP01E1000_PHY_PORT_CONFIG, 998 data); 999 } 1000 1001 out: 1002 return ret_val; 1003 } 1004 1005 /** 1006 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1 1007 * @hw: pointer to the HW structure 1008 * @bank: pointer to the variable that returns the active bank 1009 * 1010 * Reads signature byte from the NVM using the flash access registers. 1011 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank. 1012 **/ 1013 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank) 1014 { 1015 u32 eecd; 1016 struct e1000_nvm_info *nvm = &hw->nvm; 1017 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16); 1018 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1; 1019 u8 sig_byte = 0; 1020 s32 ret_val = E1000_SUCCESS; 1021 1022 switch (hw->mac.type) { 1023 case e1000_ich8lan: 1024 case e1000_ich9lan: 1025 eecd = E1000_READ_REG(hw, E1000_EECD); 1026 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) == 1027 E1000_EECD_SEC1VAL_VALID_MASK) { 1028 if (eecd & E1000_EECD_SEC1VAL) 1029 *bank = 1; 1030 else 1031 *bank = 0; 1032 1033 goto out; 1034 } 1035 DEBUGOUT("Unable to determine valid NVM bank via EEC - " 1036 "reading flash signature\n"); 1037 /* fall-thru */ 1038 default: 1039 /* set bank to 0 in case flash read fails */ 1040 *bank = 0; 1041 1042 /* Check bank 0 */ 1043 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset, 1044 &sig_byte); 1045 if (ret_val) 1046 goto out; 1047 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 1048 E1000_ICH_NVM_SIG_VALUE) { 1049 *bank = 0; 1050 goto out; 1051 } 1052 1053 /* Check bank 1 */ 1054 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset + 1055 bank1_offset, 1056 &sig_byte); 1057 if (ret_val) 1058 goto out; 1059 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 1060 E1000_ICH_NVM_SIG_VALUE) { 1061 *bank = 1; 1062 goto out; 1063 } 1064 1065 DEBUGOUT("ERROR: No valid NVM bank present\n"); 1066 ret_val = -E1000_ERR_NVM; 1067 break; 1068 } 1069 out: 1070 return ret_val; 1071 } 1072 1073 /** 1074 * e1000_read_nvm_ich8lan - Read word(s) from the NVM 1075 * @hw: pointer to the HW structure 1076 * @offset: The offset (in bytes) of the word(s) to read. 1077 * @words: Size of data to read in words 1078 * @data: Pointer to the word(s) to read at offset. 1079 * 1080 * Reads a word(s) from the NVM using the flash access registers. 1081 **/ 1082 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, 1083 u16 *data) 1084 { 1085 struct e1000_nvm_info *nvm = &hw->nvm; 1086 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 1087 u32 act_offset; 1088 s32 ret_val = E1000_SUCCESS; 1089 u32 bank = 0; 1090 u16 i, word; 1091 1092 DEBUGFUNC("e1000_read_nvm_ich8lan"); 1093 1094 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || 1095 (words == 0)) { 1096 DEBUGOUT("nvm parameter(s) out of bounds\n"); 1097 ret_val = -E1000_ERR_NVM; 1098 goto out; 1099 } 1100 1101 ret_val = nvm->ops.acquire(hw); 1102 if (ret_val) 1103 goto out; 1104 1105 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 1106 if (ret_val != E1000_SUCCESS) 1107 goto release; 1108 1109 act_offset = (bank) ? nvm->flash_bank_size : 0; 1110 act_offset += offset; 1111 1112 for (i = 0; i < words; i++) { 1113 if ((dev_spec->shadow_ram) && 1114 (dev_spec->shadow_ram[offset+i].modified)) { 1115 data[i] = dev_spec->shadow_ram[offset+i].value; 1116 } else { 1117 ret_val = e1000_read_flash_word_ich8lan(hw, 1118 act_offset + i, 1119 &word); 1120 if (ret_val) 1121 break; 1122 data[i] = word; 1123 } 1124 } 1125 1126 release: 1127 nvm->ops.release(hw); 1128 1129 out: 1130 if (ret_val) 1131 DEBUGOUT1("NVM read error: %d\n", ret_val); 1132 1133 return ret_val; 1134 } 1135 1136 /** 1137 * e1000_flash_cycle_init_ich8lan - Initialize flash 1138 * @hw: pointer to the HW structure 1139 * 1140 * This function does initial flash setup so that a new read/write/erase cycle 1141 * can be started. 1142 **/ 1143 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw) 1144 { 1145 union ich8_hws_flash_status hsfsts; 1146 s32 ret_val = -E1000_ERR_NVM; 1147 s32 i = 0; 1148 1149 DEBUGFUNC("e1000_flash_cycle_init_ich8lan"); 1150 1151 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 1152 1153 /* Check if the flash descriptor is valid */ 1154 if (hsfsts.hsf_status.fldesvalid == 0) { 1155 DEBUGOUT("Flash descriptor invalid. " 1156 "SW Sequencing must be used."); 1157 goto out; 1158 } 1159 1160 /* Clear FCERR and DAEL in hw status by writing 1 */ 1161 hsfsts.hsf_status.flcerr = 1; 1162 hsfsts.hsf_status.dael = 1; 1163 1164 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval); 1165 1166 /* 1167 * Either we should have a hardware SPI cycle in progress 1168 * bit to check against, in order to start a new cycle or 1169 * FDONE bit should be changed in the hardware so that it 1170 * is 1 after hardware reset, which can then be used as an 1171 * indication whether a cycle is in progress or has been 1172 * completed. 1173 */ 1174 1175 if (hsfsts.hsf_status.flcinprog == 0) { 1176 /* 1177 * There is no cycle running at present, 1178 * so we can start a cycle. 1179 * Begin by setting Flash Cycle Done. 1180 */ 1181 hsfsts.hsf_status.flcdone = 1; 1182 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval); 1183 ret_val = E1000_SUCCESS; 1184 } else { 1185 /* 1186 * Otherwise poll for sometime so the current 1187 * cycle has a chance to end before giving up. 1188 */ 1189 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) { 1190 hsfsts.regval = E1000_READ_FLASH_REG16(hw, 1191 ICH_FLASH_HSFSTS); 1192 if (hsfsts.hsf_status.flcinprog == 0) { 1193 ret_val = E1000_SUCCESS; 1194 break; 1195 } 1196 usec_delay(1); 1197 } 1198 if (ret_val == E1000_SUCCESS) { 1199 /* 1200 * Successful in waiting for previous cycle to timeout, 1201 * now set the Flash Cycle Done. 1202 */ 1203 hsfsts.hsf_status.flcdone = 1; 1204 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, 1205 hsfsts.regval); 1206 } else { 1207 DEBUGOUT("Flash controller busy, cannot get access"); 1208 } 1209 } 1210 1211 out: 1212 return ret_val; 1213 } 1214 1215 /** 1216 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase) 1217 * @hw: pointer to the HW structure 1218 * @timeout: maximum time to wait for completion 1219 * 1220 * This function starts a flash cycle and waits for its completion. 1221 **/ 1222 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout) 1223 { 1224 union ich8_hws_flash_ctrl hsflctl; 1225 union ich8_hws_flash_status hsfsts; 1226 s32 ret_val = -E1000_ERR_NVM; 1227 u32 i = 0; 1228 1229 DEBUGFUNC("e1000_flash_cycle_ich8lan"); 1230 1231 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */ 1232 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL); 1233 hsflctl.hsf_ctrl.flcgo = 1; 1234 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); 1235 1236 /* wait till FDONE bit is set to 1 */ 1237 do { 1238 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 1239 if (hsfsts.hsf_status.flcdone == 1) 1240 break; 1241 usec_delay(1); 1242 } while (i++ < timeout); 1243 1244 if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0) 1245 ret_val = E1000_SUCCESS; 1246 1247 return ret_val; 1248 } 1249 1250 /** 1251 * e1000_read_flash_word_ich8lan - Read word from flash 1252 * @hw: pointer to the HW structure 1253 * @offset: offset to data location 1254 * @data: pointer to the location for storing the data 1255 * 1256 * Reads the flash word at offset into data. Offset is converted 1257 * to bytes before read. 1258 **/ 1259 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset, 1260 u16 *data) 1261 { 1262 s32 ret_val; 1263 1264 DEBUGFUNC("e1000_read_flash_word_ich8lan"); 1265 1266 if (!data) { 1267 ret_val = -E1000_ERR_NVM; 1268 goto out; 1269 } 1270 1271 /* Must convert offset into bytes. */ 1272 offset <<= 1; 1273 1274 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 2, data); 1275 1276 out: 1277 return ret_val; 1278 } 1279 1280 /** 1281 * e1000_read_flash_byte_ich8lan - Read byte from flash 1282 * @hw: pointer to the HW structure 1283 * @offset: The offset of the byte to read. 1284 * @data: Pointer to a byte to store the value read. 1285 * 1286 * Reads a single byte from the NVM using the flash access registers. 1287 **/ 1288 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, 1289 u8 *data) 1290 { 1291 s32 ret_val = E1000_SUCCESS; 1292 u16 word = 0; 1293 1294 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word); 1295 if (ret_val) 1296 goto out; 1297 1298 *data = (u8)word; 1299 1300 out: 1301 return ret_val; 1302 } 1303 1304 /** 1305 * e1000_read_flash_data_ich8lan - Read byte or word from NVM 1306 * @hw: pointer to the HW structure 1307 * @offset: The offset (in bytes) of the byte or word to read. 1308 * @size: Size of data to read, 1=byte 2=word 1309 * @data: Pointer to the word to store the value read. 1310 * 1311 * Reads a byte or word from the NVM using the flash access registers. 1312 **/ 1313 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 1314 u8 size, u16 *data) 1315 { 1316 union ich8_hws_flash_status hsfsts; 1317 union ich8_hws_flash_ctrl hsflctl; 1318 u32 flash_linear_addr; 1319 u32 flash_data = 0; 1320 s32 ret_val = -E1000_ERR_NVM; 1321 u8 count = 0; 1322 1323 DEBUGFUNC("e1000_read_flash_data_ich8lan"); 1324 1325 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK) 1326 goto out; 1327 1328 flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) + 1329 hw->nvm.flash_base_addr; 1330 1331 do { 1332 usec_delay(1); 1333 /* Steps */ 1334 ret_val = e1000_flash_cycle_init_ich8lan(hw); 1335 if (ret_val != E1000_SUCCESS) 1336 break; 1337 1338 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL); 1339 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 1340 hsflctl.hsf_ctrl.fldbcount = size - 1; 1341 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ; 1342 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); 1343 1344 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr); 1345 1346 ret_val = e1000_flash_cycle_ich8lan(hw, 1347 ICH_FLASH_READ_COMMAND_TIMEOUT); 1348 1349 /* 1350 * Check if FCERR is set to 1, if set to 1, clear it 1351 * and try the whole sequence a few more times, else 1352 * read in (shift in) the Flash Data0, the order is 1353 * least significant byte first msb to lsb 1354 */ 1355 if (ret_val == E1000_SUCCESS) { 1356 flash_data = E1000_READ_FLASH_REG(hw, ICH_FLASH_FDATA0); 1357 if (size == 1) 1358 *data = (u8)(flash_data & 0x000000FF); 1359 else if (size == 2) 1360 *data = (u16)(flash_data & 0x0000FFFF); 1361 break; 1362 } else { 1363 /* 1364 * If we've gotten here, then things are probably 1365 * completely hosed, but if the error condition is 1366 * detected, it won't hurt to give it another try... 1367 * ICH_FLASH_CYCLE_REPEAT_COUNT times. 1368 */ 1369 hsfsts.regval = E1000_READ_FLASH_REG16(hw, 1370 ICH_FLASH_HSFSTS); 1371 if (hsfsts.hsf_status.flcerr == 1) { 1372 /* Repeat for some time before giving up. */ 1373 continue; 1374 } else if (hsfsts.hsf_status.flcdone == 0) { 1375 DEBUGOUT("Timeout error - flash cycle " 1376 "did not complete."); 1377 break; 1378 } 1379 } 1380 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 1381 1382 out: 1383 return ret_val; 1384 } 1385 1386 /** 1387 * e1000_write_nvm_ich8lan - Write word(s) to the NVM 1388 * @hw: pointer to the HW structure 1389 * @offset: The offset (in bytes) of the word(s) to write. 1390 * @words: Size of data to write in words 1391 * @data: Pointer to the word(s) to write at offset. 1392 * 1393 * Writes a byte or word to the NVM using the flash access registers. 1394 **/ 1395 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, 1396 u16 *data) 1397 { 1398 struct e1000_nvm_info *nvm = &hw->nvm; 1399 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 1400 s32 ret_val = E1000_SUCCESS; 1401 u16 i; 1402 1403 DEBUGFUNC("e1000_write_nvm_ich8lan"); 1404 1405 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || 1406 (words == 0)) { 1407 DEBUGOUT("nvm parameter(s) out of bounds\n"); 1408 ret_val = -E1000_ERR_NVM; 1409 goto out; 1410 } 1411 1412 ret_val = nvm->ops.acquire(hw); 1413 if (ret_val) 1414 goto out; 1415 1416 for (i = 0; i < words; i++) { 1417 dev_spec->shadow_ram[offset+i].modified = TRUE; 1418 dev_spec->shadow_ram[offset+i].value = data[i]; 1419 } 1420 1421 nvm->ops.release(hw); 1422 1423 out: 1424 return ret_val; 1425 } 1426 1427 /** 1428 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM 1429 * @hw: pointer to the HW structure 1430 * 1431 * The NVM checksum is updated by calling the generic update_nvm_checksum, 1432 * which writes the checksum to the shadow ram. The changes in the shadow 1433 * ram are then committed to the EEPROM by processing each bank at a time 1434 * checking for the modified bit and writing only the pending changes. 1435 * After a successful commit, the shadow ram is cleared and is ready for 1436 * future writes. 1437 **/ 1438 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw) 1439 { 1440 struct e1000_nvm_info *nvm = &hw->nvm; 1441 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 1442 u32 i, act_offset, new_bank_offset, old_bank_offset, bank; 1443 s32 ret_val; 1444 u16 data; 1445 1446 DEBUGFUNC("e1000_update_nvm_checksum_ich8lan"); 1447 1448 ret_val = e1000_update_nvm_checksum_generic(hw); 1449 if (ret_val) 1450 goto out; 1451 1452 if (nvm->type != e1000_nvm_flash_sw) 1453 goto out; 1454 1455 ret_val = nvm->ops.acquire(hw); 1456 if (ret_val) 1457 goto out; 1458 1459 /* 1460 * We're writing to the opposite bank so if we're on bank 1, 1461 * write to bank 0 etc. We also need to erase the segment that 1462 * is going to be written 1463 */ 1464 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 1465 if (ret_val != E1000_SUCCESS) { 1466 nvm->ops.release(hw); 1467 goto out; 1468 } 1469 1470 if (bank == 0) { 1471 new_bank_offset = nvm->flash_bank_size; 1472 old_bank_offset = 0; 1473 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1); 1474 if (ret_val) { 1475 nvm->ops.release(hw); 1476 goto out; 1477 } 1478 } else { 1479 old_bank_offset = nvm->flash_bank_size; 1480 new_bank_offset = 0; 1481 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0); 1482 if (ret_val) { 1483 nvm->ops.release(hw); 1484 goto out; 1485 } 1486 } 1487 1488 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 1489 /* 1490 * Determine whether to write the value stored 1491 * in the other NVM bank or a modified value stored 1492 * in the shadow RAM 1493 */ 1494 if (dev_spec->shadow_ram[i].modified) { 1495 data = dev_spec->shadow_ram[i].value; 1496 } else { 1497 ret_val = e1000_read_flash_word_ich8lan(hw, i + 1498 old_bank_offset, 1499 &data); 1500 if (ret_val) 1501 break; 1502 } 1503 1504 /* 1505 * If the word is 0x13, then make sure the signature bits 1506 * (15:14) are 11b until the commit has completed. 1507 * This will allow us to write 10b which indicates the 1508 * signature is valid. We want to do this after the write 1509 * has completed so that we don't mark the segment valid 1510 * while the write is still in progress 1511 */ 1512 if (i == E1000_ICH_NVM_SIG_WORD) 1513 data |= E1000_ICH_NVM_SIG_MASK; 1514 1515 /* Convert offset to bytes. */ 1516 act_offset = (i + new_bank_offset) << 1; 1517 1518 usec_delay(100); 1519 /* Write the bytes to the new bank. */ 1520 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, 1521 act_offset, 1522 (u8)data); 1523 if (ret_val) 1524 break; 1525 1526 usec_delay(100); 1527 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, 1528 act_offset + 1, 1529 (u8)(data >> 8)); 1530 if (ret_val) 1531 break; 1532 } 1533 1534 /* 1535 * Don't bother writing the segment valid bits if sector 1536 * programming failed. 1537 */ 1538 if (ret_val) { 1539 DEBUGOUT("Flash commit failed.\n"); 1540 nvm->ops.release(hw); 1541 goto out; 1542 } 1543 1544 /* 1545 * Finally validate the new segment by setting bit 15:14 1546 * to 10b in word 0x13 , this can be done without an 1547 * erase as well since these bits are 11 to start with 1548 * and we need to change bit 14 to 0b 1549 */ 1550 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD; 1551 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data); 1552 if (ret_val) { 1553 nvm->ops.release(hw); 1554 goto out; 1555 } 1556 data &= 0xBFFF; 1557 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, 1558 act_offset * 2 + 1, 1559 (u8)(data >> 8)); 1560 if (ret_val) { 1561 nvm->ops.release(hw); 1562 goto out; 1563 } 1564 1565 /* 1566 * And invalidate the previously valid segment by setting 1567 * its signature word (0x13) high_byte to 0b. This can be 1568 * done without an erase because flash erase sets all bits 1569 * to 1's. We can write 1's to 0's without an erase 1570 */ 1571 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1; 1572 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0); 1573 if (ret_val) { 1574 nvm->ops.release(hw); 1575 goto out; 1576 } 1577 1578 /* Great! Everything worked, we can now clear the cached entries. */ 1579 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 1580 dev_spec->shadow_ram[i].modified = FALSE; 1581 dev_spec->shadow_ram[i].value = 0xFFFF; 1582 } 1583 1584 nvm->ops.release(hw); 1585 1586 /* 1587 * Reload the EEPROM, or else modifications will not appear 1588 * until after the next adapter reset. 1589 */ 1590 nvm->ops.reload(hw); 1591 msec_delay(10); 1592 1593 out: 1594 if (ret_val) 1595 DEBUGOUT1("NVM update error: %d\n", ret_val); 1596 1597 return ret_val; 1598 } 1599 1600 /** 1601 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum 1602 * @hw: pointer to the HW structure 1603 * 1604 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19. 1605 * If the bit is 0, that the EEPROM had been modified, but the checksum was not 1606 * calculated, in which case we need to calculate the checksum and set bit 6. 1607 **/ 1608 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw) 1609 { 1610 s32 ret_val = E1000_SUCCESS; 1611 u16 data; 1612 1613 DEBUGFUNC("e1000_validate_nvm_checksum_ich8lan"); 1614 1615 /* 1616 * Read 0x19 and check bit 6. If this bit is 0, the checksum 1617 * needs to be fixed. This bit is an indication that the NVM 1618 * was prepared by OEM software and did not calculate the 1619 * checksum...a likely scenario. 1620 */ 1621 ret_val = hw->nvm.ops.read(hw, 0x19, 1, &data); 1622 if (ret_val) 1623 goto out; 1624 1625 if ((data & 0x40) == 0) { 1626 data |= 0x40; 1627 ret_val = hw->nvm.ops.write(hw, 0x19, 1, &data); 1628 if (ret_val) 1629 goto out; 1630 ret_val = hw->nvm.ops.update(hw); 1631 if (ret_val) 1632 goto out; 1633 } 1634 1635 ret_val = e1000_validate_nvm_checksum_generic(hw); 1636 1637 out: 1638 return ret_val; 1639 } 1640 1641 /** 1642 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM 1643 * @hw: pointer to the HW structure 1644 * @offset: The offset (in bytes) of the byte/word to read. 1645 * @size: Size of data to read, 1=byte 2=word 1646 * @data: The byte(s) to write to the NVM. 1647 * 1648 * Writes one/two bytes to the NVM using the flash access registers. 1649 **/ 1650 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 1651 u8 size, u16 data) 1652 { 1653 union ich8_hws_flash_status hsfsts; 1654 union ich8_hws_flash_ctrl hsflctl; 1655 u32 flash_linear_addr; 1656 u32 flash_data = 0; 1657 s32 ret_val = -E1000_ERR_NVM; 1658 u8 count = 0; 1659 1660 DEBUGFUNC("e1000_write_ich8_data"); 1661 1662 if (size < 1 || size > 2 || data > size * 0xff || 1663 offset > ICH_FLASH_LINEAR_ADDR_MASK) 1664 goto out; 1665 1666 flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) + 1667 hw->nvm.flash_base_addr; 1668 1669 do { 1670 usec_delay(1); 1671 /* Steps */ 1672 ret_val = e1000_flash_cycle_init_ich8lan(hw); 1673 if (ret_val != E1000_SUCCESS) 1674 break; 1675 1676 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL); 1677 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 1678 hsflctl.hsf_ctrl.fldbcount = size - 1; 1679 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE; 1680 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); 1681 1682 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr); 1683 1684 if (size == 1) 1685 flash_data = (u32)data & 0x00FF; 1686 else 1687 flash_data = (u32)data; 1688 1689 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data); 1690 1691 /* 1692 * check if FCERR is set to 1 , if set to 1, clear it 1693 * and try the whole sequence a few more times else done 1694 */ 1695 ret_val = e1000_flash_cycle_ich8lan(hw, 1696 ICH_FLASH_WRITE_COMMAND_TIMEOUT); 1697 if (ret_val == E1000_SUCCESS) 1698 break; 1699 1700 /* 1701 * If we're here, then things are most likely 1702 * completely hosed, but if the error condition 1703 * is detected, it won't hurt to give it another 1704 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. 1705 */ 1706 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 1707 if (hsfsts.hsf_status.flcerr == 1) { 1708 /* Repeat for some time before giving up. */ 1709 continue; 1710 } else if (hsfsts.hsf_status.flcdone == 0) { 1711 DEBUGOUT("Timeout error - flash cycle " 1712 "did not complete."); 1713 break; 1714 } 1715 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 1716 1717 out: 1718 return ret_val; 1719 } 1720 1721 /** 1722 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM 1723 * @hw: pointer to the HW structure 1724 * @offset: The index of the byte to read. 1725 * @data: The byte to write to the NVM. 1726 * 1727 * Writes a single byte to the NVM using the flash access registers. 1728 **/ 1729 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, 1730 u8 data) 1731 { 1732 u16 word = (u16)data; 1733 1734 DEBUGFUNC("e1000_write_flash_byte_ich8lan"); 1735 1736 return e1000_write_flash_data_ich8lan(hw, offset, 1, word); 1737 } 1738 1739 /** 1740 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM 1741 * @hw: pointer to the HW structure 1742 * @offset: The offset of the byte to write. 1743 * @byte: The byte to write to the NVM. 1744 * 1745 * Writes a single byte to the NVM using the flash access registers. 1746 * Goes through a retry algorithm before giving up. 1747 **/ 1748 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, 1749 u32 offset, u8 byte) 1750 { 1751 s32 ret_val; 1752 u16 program_retries; 1753 1754 DEBUGFUNC("e1000_retry_write_flash_byte_ich8lan"); 1755 1756 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); 1757 if (ret_val == E1000_SUCCESS) 1758 goto out; 1759 1760 for (program_retries = 0; program_retries < 100; program_retries++) { 1761 DEBUGOUT2("Retrying Byte %2.2X at offset %u\n", byte, offset); 1762 usec_delay(100); 1763 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); 1764 if (ret_val == E1000_SUCCESS) 1765 break; 1766 } 1767 if (program_retries == 100) { 1768 ret_val = -E1000_ERR_NVM; 1769 goto out; 1770 } 1771 1772 out: 1773 return ret_val; 1774 } 1775 1776 /** 1777 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM 1778 * @hw: pointer to the HW structure 1779 * @bank: 0 for first bank, 1 for second bank, etc. 1780 * 1781 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based. 1782 * bank N is 4096 * N + flash_reg_addr. 1783 **/ 1784 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank) 1785 { 1786 struct e1000_nvm_info *nvm = &hw->nvm; 1787 union ich8_hws_flash_status hsfsts; 1788 union ich8_hws_flash_ctrl hsflctl; 1789 u32 flash_linear_addr; 1790 /* bank size is in 16bit words - adjust to bytes */ 1791 u32 flash_bank_size = nvm->flash_bank_size * 2; 1792 s32 ret_val = E1000_SUCCESS; 1793 s32 count = 0; 1794 s32 j, iteration, sector_size; 1795 1796 DEBUGFUNC("e1000_erase_flash_bank_ich8lan"); 1797 1798 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 1799 1800 /* 1801 * Determine HW Sector size: Read BERASE bits of hw flash status 1802 * register 1803 * 00: The Hw sector is 256 bytes, hence we need to erase 16 1804 * consecutive sectors. The start index for the nth Hw sector 1805 * can be calculated as = bank * 4096 + n * 256 1806 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector. 1807 * The start index for the nth Hw sector can be calculated 1808 * as = bank * 4096 1809 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192 1810 * (ich9 only, otherwise error condition) 1811 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536 1812 */ 1813 switch (hsfsts.hsf_status.berasesz) { 1814 case 0: 1815 /* Hw sector size 256 */ 1816 sector_size = ICH_FLASH_SEG_SIZE_256; 1817 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256; 1818 break; 1819 case 1: 1820 sector_size = ICH_FLASH_SEG_SIZE_4K; 1821 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_4K; 1822 break; 1823 case 2: 1824 if (hw->mac.type == e1000_ich9lan) { 1825 sector_size = ICH_FLASH_SEG_SIZE_8K; 1826 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_8K; 1827 } else { 1828 ret_val = -E1000_ERR_NVM; 1829 goto out; 1830 } 1831 break; 1832 case 3: 1833 sector_size = ICH_FLASH_SEG_SIZE_64K; 1834 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_64K; 1835 break; 1836 default: 1837 ret_val = -E1000_ERR_NVM; 1838 goto out; 1839 } 1840 1841 /* Start with the base address, then add the sector offset. */ 1842 flash_linear_addr = hw->nvm.flash_base_addr; 1843 flash_linear_addr += (bank) ? (sector_size * iteration) : 0; 1844 1845 for (j = 0; j < iteration ; j++) { 1846 do { 1847 /* Steps */ 1848 ret_val = e1000_flash_cycle_init_ich8lan(hw); 1849 if (ret_val) 1850 goto out; 1851 1852 /* 1853 * Write a value 11 (block Erase) in Flash 1854 * Cycle field in hw flash control 1855 */ 1856 hsflctl.regval = E1000_READ_FLASH_REG16(hw, 1857 ICH_FLASH_HSFCTL); 1858 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE; 1859 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, 1860 hsflctl.regval); 1861 1862 /* 1863 * Write the last 24 bits of an index within the 1864 * block into Flash Linear address field in Flash 1865 * Address. 1866 */ 1867 flash_linear_addr += (j * sector_size); 1868 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, 1869 flash_linear_addr); 1870 1871 ret_val = e1000_flash_cycle_ich8lan(hw, 1872 ICH_FLASH_ERASE_COMMAND_TIMEOUT); 1873 if (ret_val == E1000_SUCCESS) 1874 break; 1875 1876 /* 1877 * Check if FCERR is set to 1. If 1, 1878 * clear it and try the whole sequence 1879 * a few more times else Done 1880 */ 1881 hsfsts.regval = E1000_READ_FLASH_REG16(hw, 1882 ICH_FLASH_HSFSTS); 1883 if (hsfsts.hsf_status.flcerr == 1) 1884 /* repeat for some time before giving up */ 1885 continue; 1886 else if (hsfsts.hsf_status.flcdone == 0) 1887 goto out; 1888 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT); 1889 } 1890 1891 out: 1892 return ret_val; 1893 } 1894 1895 /** 1896 * e1000_valid_led_default_ich8lan - Set the default LED settings 1897 * @hw: pointer to the HW structure 1898 * @data: Pointer to the LED settings 1899 * 1900 * Reads the LED default settings from the NVM to data. If the NVM LED 1901 * settings is all 0's or F's, set the LED default to a valid LED default 1902 * setting. 1903 **/ 1904 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data) 1905 { 1906 s32 ret_val; 1907 1908 DEBUGFUNC("e1000_valid_led_default_ich8lan"); 1909 1910 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); 1911 if (ret_val) { 1912 DEBUGOUT("NVM Read Error\n"); 1913 goto out; 1914 } 1915 1916 if (*data == ID_LED_RESERVED_0000 || 1917 *data == ID_LED_RESERVED_FFFF) 1918 *data = ID_LED_DEFAULT_ICH8LAN; 1919 1920 out: 1921 return ret_val; 1922 } 1923 1924 /** 1925 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width 1926 * @hw: pointer to the HW structure 1927 * 1928 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability 1929 * register, so the the bus width is hard coded. 1930 **/ 1931 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw) 1932 { 1933 struct e1000_bus_info *bus = &hw->bus; 1934 s32 ret_val; 1935 1936 DEBUGFUNC("e1000_get_bus_info_ich8lan"); 1937 1938 ret_val = e1000_get_bus_info_pcie_generic(hw); 1939 1940 /* 1941 * ICH devices are "PCI Express"-ish. They have 1942 * a configuration space, but do not contain 1943 * PCI Express Capability registers, so bus width 1944 * must be hardcoded. 1945 */ 1946 if (bus->width == e1000_bus_width_unknown) 1947 bus->width = e1000_bus_width_pcie_x1; 1948 1949 return ret_val; 1950 } 1951 1952 /** 1953 * e1000_reset_hw_ich8lan - Reset the hardware 1954 * @hw: pointer to the HW structure 1955 * 1956 * Does a full reset of the hardware which includes a reset of the PHY and 1957 * MAC. 1958 **/ 1959 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw) 1960 { 1961 u32 ctrl, icr, kab; 1962 s32 ret_val; 1963 1964 DEBUGFUNC("e1000_reset_hw_ich8lan"); 1965 1966 /* 1967 * Prevent the PCI-E bus from sticking if there is no TLP connection 1968 * on the last TLP read/write transaction when MAC is reset. 1969 */ 1970 ret_val = e1000_disable_pcie_master_generic(hw); 1971 if (ret_val) 1972 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 1973 1974 DEBUGOUT("Masking off all interrupts\n"); 1975 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 1976 1977 /* 1978 * Disable the Transmit and Receive units. Then delay to allow 1979 * any pending transactions to complete before we hit the MAC 1980 * with the global reset. 1981 */ 1982 E1000_WRITE_REG(hw, E1000_RCTL, 0); 1983 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 1984 E1000_WRITE_FLUSH(hw); 1985 1986 msec_delay(10); 1987 1988 /* Workaround for ICH8 bit corruption issue in FIFO memory */ 1989 if (hw->mac.type == e1000_ich8lan) { 1990 /* Set Tx and Rx buffer allocation to 8k apiece. */ 1991 E1000_WRITE_REG(hw, E1000_PBA, E1000_PBA_8K); 1992 /* Set Packet Buffer Size to 16k. */ 1993 E1000_WRITE_REG(hw, E1000_PBS, E1000_PBS_16K); 1994 } 1995 1996 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1997 1998 if (!hw->phy.ops.check_reset_block(hw) && !hw->phy.reset_disable) { 1999 /* 2000 * PHY HW reset requires MAC CORE reset at the same 2001 * time to make sure the interface between MAC and the 2002 * external PHY is reset. 2003 */ 2004 ctrl |= E1000_CTRL_PHY_RST; 2005 } 2006 ret_val = e1000_acquire_swflag_ich8lan(hw); 2007 DEBUGOUT("Issuing a global reset to ich8lan\n"); 2008 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_RST)); 2009 msec_delay(20); 2010 2011 ret_val = e1000_get_auto_rd_done_generic(hw); 2012 if (ret_val) { 2013 /* 2014 * When auto config read does not complete, do not 2015 * return with an error. This can happen in situations 2016 * where there is no eeprom and prevents getting link. 2017 */ 2018 DEBUGOUT("Auto Read Done did not complete\n"); 2019 } 2020 2021 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 2022 icr = E1000_READ_REG(hw, E1000_ICR); 2023 2024 kab = E1000_READ_REG(hw, E1000_KABGTXD); 2025 kab |= E1000_KABGTXD_BGSQLBIAS; 2026 E1000_WRITE_REG(hw, E1000_KABGTXD, kab); 2027 2028 return ret_val; 2029 } 2030 2031 /** 2032 * e1000_init_hw_ich8lan - Initialize the hardware 2033 * @hw: pointer to the HW structure 2034 * 2035 * Prepares the hardware for transmit and receive by doing the following: 2036 * - initialize hardware bits 2037 * - initialize LED identification 2038 * - setup receive address registers 2039 * - setup flow control 2040 * - setup transmit descriptors 2041 * - clear statistics 2042 **/ 2043 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw) 2044 { 2045 struct e1000_mac_info *mac = &hw->mac; 2046 u32 ctrl_ext, txdctl, snoop; 2047 s32 ret_val; 2048 u16 i; 2049 2050 DEBUGFUNC("e1000_init_hw_ich8lan"); 2051 2052 e1000_initialize_hw_bits_ich8lan(hw); 2053 2054 /* Initialize identification LED */ 2055 ret_val = mac->ops.id_led_init(hw); 2056 if (ret_val) 2057 /* This is not fatal and we should not stop init due to this */ 2058 DEBUGOUT("Error initializing identification LED\n"); 2059 2060 /* Setup the receive address. */ 2061 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count); 2062 2063 /* Zero out the Multicast HASH table */ 2064 DEBUGOUT("Zeroing the MTA\n"); 2065 for (i = 0; i < mac->mta_reg_count; i++) 2066 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 2067 2068 /* Setup link and flow control */ 2069 ret_val = mac->ops.setup_link(hw); 2070 2071 /* Set the transmit descriptor write-back policy for both queues */ 2072 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0)); 2073 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) | 2074 E1000_TXDCTL_FULL_TX_DESC_WB; 2075 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) | 2076 E1000_TXDCTL_MAX_TX_DESC_PREFETCH; 2077 E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl); 2078 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(1)); 2079 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) | 2080 E1000_TXDCTL_FULL_TX_DESC_WB; 2081 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) | 2082 E1000_TXDCTL_MAX_TX_DESC_PREFETCH; 2083 E1000_WRITE_REG(hw, E1000_TXDCTL(1), txdctl); 2084 2085 /* 2086 * ICH8 has opposite polarity of no_snoop bits. 2087 * By default, we should use snoop behavior. 2088 */ 2089 if (mac->type == e1000_ich8lan) 2090 snoop = PCIE_ICH8_SNOOP_ALL; 2091 else 2092 snoop = (u32)~(PCIE_NO_SNOOP_ALL); 2093 e1000_set_pcie_no_snoop_generic(hw, snoop); 2094 2095 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 2096 ctrl_ext |= E1000_CTRL_EXT_RO_DIS; 2097 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 2098 2099 /* 2100 * Clear all of the statistics registers (clear on read). It is 2101 * important that we do this after we have tried to establish link 2102 * because the symbol error count will increment wildly if there 2103 * is no link. 2104 */ 2105 e1000_clear_hw_cntrs_ich8lan(hw); 2106 2107 return ret_val; 2108 } 2109 /** 2110 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits 2111 * @hw: pointer to the HW structure 2112 * 2113 * Sets/Clears required hardware bits necessary for correctly setting up the 2114 * hardware for transmit and receive. 2115 **/ 2116 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw) 2117 { 2118 u32 reg; 2119 2120 DEBUGFUNC("e1000_initialize_hw_bits_ich8lan"); 2121 2122 /* Extended Device Control */ 2123 reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 2124 reg |= (1 << 22); 2125 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 2126 2127 /* Transmit Descriptor Control 0 */ 2128 reg = E1000_READ_REG(hw, E1000_TXDCTL(0)); 2129 reg |= (1 << 22); 2130 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg); 2131 2132 /* Transmit Descriptor Control 1 */ 2133 reg = E1000_READ_REG(hw, E1000_TXDCTL(1)); 2134 reg |= (1 << 22); 2135 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg); 2136 2137 /* Transmit Arbitration Control 0 */ 2138 reg = E1000_READ_REG(hw, E1000_TARC(0)); 2139 if (hw->mac.type == e1000_ich8lan) 2140 reg |= (1 << 28) | (1 << 29); 2141 reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27); 2142 E1000_WRITE_REG(hw, E1000_TARC(0), reg); 2143 2144 /* Transmit Arbitration Control 1 */ 2145 reg = E1000_READ_REG(hw, E1000_TARC(1)); 2146 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR) 2147 reg &= ~(1 << 28); 2148 else 2149 reg |= (1 << 28); 2150 reg |= (1 << 24) | (1 << 26) | (1 << 30); 2151 E1000_WRITE_REG(hw, E1000_TARC(1), reg); 2152 2153 /* Device Status */ 2154 if (hw->mac.type == e1000_ich8lan) { 2155 reg = E1000_READ_REG(hw, E1000_STATUS); 2156 reg &= ~(1 << 31); 2157 E1000_WRITE_REG(hw, E1000_STATUS, reg); 2158 } 2159 2160 return; 2161 } 2162 2163 /** 2164 * e1000_setup_link_ich8lan - Setup flow control and link settings 2165 * @hw: pointer to the HW structure 2166 * 2167 * Determines which flow control settings to use, then configures flow 2168 * control. Calls the appropriate media-specific link configuration 2169 * function. Assuming the adapter has a valid link partner, a valid link 2170 * should be established. Assumes the hardware has previously been reset 2171 * and the transmitter and receiver are not enabled. 2172 **/ 2173 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw) 2174 { 2175 s32 ret_val = E1000_SUCCESS; 2176 2177 DEBUGFUNC("e1000_setup_link_ich8lan"); 2178 2179 if (hw->phy.ops.check_reset_block(hw)) 2180 goto out; 2181 2182 /* 2183 * ICH parts do not have a word in the NVM to determine 2184 * the default flow control setting, so we explicitly 2185 * set it to full. 2186 */ 2187 if (hw->fc.requested_mode == e1000_fc_default) 2188 hw->fc.requested_mode = e1000_fc_full; 2189 2190 /* 2191 * Save off the requested flow control mode for use later. Depending 2192 * on the link partner's capabilities, we may or may not use this mode. 2193 */ 2194 hw->fc.current_mode = hw->fc.requested_mode; 2195 2196 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", 2197 hw->fc.current_mode); 2198 2199 /* Continue to configure the copper link. */ 2200 ret_val = hw->mac.ops.setup_physical_interface(hw); 2201 if (ret_val) 2202 goto out; 2203 2204 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time); 2205 2206 ret_val = e1000_set_fc_watermarks_generic(hw); 2207 2208 out: 2209 return ret_val; 2210 } 2211 2212 /** 2213 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface 2214 * @hw: pointer to the HW structure 2215 * 2216 * Configures the kumeran interface to the PHY to wait the appropriate time 2217 * when polling the PHY, then call the generic setup_copper_link to finish 2218 * configuring the copper link. 2219 **/ 2220 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw) 2221 { 2222 u32 ctrl; 2223 s32 ret_val; 2224 u16 reg_data; 2225 2226 DEBUGFUNC("e1000_setup_copper_link_ich8lan"); 2227 2228 ctrl = E1000_READ_REG(hw, E1000_CTRL); 2229 ctrl |= E1000_CTRL_SLU; 2230 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 2231 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2232 2233 /* 2234 * Set the mac to wait the maximum time between each iteration 2235 * and increase the max iterations when polling the phy; 2236 * this fixes erroneous timeouts at 10Mbps. 2237 */ 2238 ret_val = e1000_write_kmrn_reg_generic(hw, GG82563_REG(0x34, 4), 2239 0xFFFF); 2240 if (ret_val) 2241 goto out; 2242 ret_val = e1000_read_kmrn_reg_generic(hw, GG82563_REG(0x34, 9), 2243 ®_data); 2244 if (ret_val) 2245 goto out; 2246 reg_data |= 0x3F; 2247 ret_val = e1000_write_kmrn_reg_generic(hw, GG82563_REG(0x34, 9), 2248 reg_data); 2249 if (ret_val) 2250 goto out; 2251 2252 switch (hw->phy.type) { 2253 case e1000_phy_igp_3: 2254 ret_val = e1000_copper_link_setup_igp(hw); 2255 if (ret_val) 2256 goto out; 2257 break; 2258 case e1000_phy_bm: 2259 ret_val = e1000_copper_link_setup_m88(hw); 2260 if (ret_val) 2261 goto out; 2262 break; 2263 case e1000_phy_ife: 2264 ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, 2265 ®_data); 2266 if (ret_val) 2267 goto out; 2268 2269 reg_data &= ~IFE_PMC_AUTO_MDIX; 2270 2271 switch (hw->phy.mdix) { 2272 case 1: 2273 reg_data &= ~IFE_PMC_FORCE_MDIX; 2274 break; 2275 case 2: 2276 reg_data |= IFE_PMC_FORCE_MDIX; 2277 break; 2278 case 0: 2279 default: 2280 reg_data |= IFE_PMC_AUTO_MDIX; 2281 break; 2282 } 2283 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, 2284 reg_data); 2285 if (ret_val) 2286 goto out; 2287 break; 2288 default: 2289 break; 2290 } 2291 ret_val = e1000_setup_copper_link_generic(hw); 2292 2293 out: 2294 return ret_val; 2295 } 2296 2297 /** 2298 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex 2299 * @hw: pointer to the HW structure 2300 * @speed: pointer to store current link speed 2301 * @duplex: pointer to store the current link duplex 2302 * 2303 * Calls the generic get_speed_and_duplex to retrieve the current link 2304 * information and then calls the Kumeran lock loss workaround for links at 2305 * gigabit speeds. 2306 **/ 2307 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed, 2308 u16 *duplex) 2309 { 2310 s32 ret_val; 2311 2312 DEBUGFUNC("e1000_get_link_up_info_ich8lan"); 2313 2314 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex); 2315 if (ret_val) 2316 goto out; 2317 2318 if ((hw->mac.type == e1000_ich8lan) && 2319 (hw->phy.type == e1000_phy_igp_3) && 2320 (*speed == SPEED_1000)) { 2321 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw); 2322 } 2323 2324 out: 2325 return ret_val; 2326 } 2327 2328 /** 2329 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround 2330 * @hw: pointer to the HW structure 2331 * 2332 * Work-around for 82566 Kumeran PCS lock loss: 2333 * On link status change (i.e. PCI reset, speed change) and link is up and 2334 * speed is gigabit- 2335 * 0) if workaround is optionally disabled do nothing 2336 * 1) wait 1ms for Kumeran link to come up 2337 * 2) check Kumeran Diagnostic register PCS lock loss bit 2338 * 3) if not set the link is locked (all is good), otherwise... 2339 * 4) reset the PHY 2340 * 5) repeat up to 10 times 2341 * Note: this is only called for IGP3 copper when speed is 1gb. 2342 **/ 2343 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw) 2344 { 2345 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 2346 u32 phy_ctrl; 2347 s32 ret_val = E1000_SUCCESS; 2348 u16 i, data; 2349 bool link; 2350 2351 DEBUGFUNC("e1000_kmrn_lock_loss_workaround_ich8lan"); 2352 2353 if (!(dev_spec->kmrn_lock_loss_workaround_enabled)) 2354 goto out; 2355 2356 /* 2357 * Make sure link is up before proceeding. If not just return. 2358 * Attempting this while link is negotiating fouled up link 2359 * stability 2360 */ 2361 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 2362 if (!link) { 2363 ret_val = E1000_SUCCESS; 2364 goto out; 2365 } 2366 2367 for (i = 0; i < 10; i++) { 2368 /* read once to clear */ 2369 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data); 2370 if (ret_val) 2371 goto out; 2372 /* and again to get new status */ 2373 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data); 2374 if (ret_val) 2375 goto out; 2376 2377 /* check for PCS lock */ 2378 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS)) { 2379 ret_val = E1000_SUCCESS; 2380 goto out; 2381 } 2382 2383 /* Issue PHY reset */ 2384 hw->phy.ops.reset(hw); 2385 msec_delay_irq(5); 2386 } 2387 /* Disable GigE link negotiation */ 2388 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL); 2389 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE | 2390 E1000_PHY_CTRL_NOND0A_GBE_DISABLE); 2391 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 2392 2393 /* 2394 * Call gig speed drop workaround on Gig disable before accessing 2395 * any PHY registers 2396 */ 2397 e1000_gig_downshift_workaround_ich8lan(hw); 2398 2399 /* unable to acquire PCS lock */ 2400 ret_val = -E1000_ERR_PHY; 2401 2402 out: 2403 return ret_val; 2404 } 2405 2406 /** 2407 * e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state 2408 * @hw: pointer to the HW structure 2409 * @state: boolean value used to set the current Kumeran workaround state 2410 * 2411 * If ICH8, set the current Kumeran workaround state (enabled - TRUE 2412 * /disabled - FALSE). 2413 **/ 2414 void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw, 2415 bool state) 2416 { 2417 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 2418 2419 DEBUGFUNC("e1000_set_kmrn_lock_loss_workaround_ich8lan"); 2420 2421 if (hw->mac.type != e1000_ich8lan) { 2422 DEBUGOUT("Workaround applies to ICH8 only.\n"); 2423 return; 2424 } 2425 2426 dev_spec->kmrn_lock_loss_workaround_enabled = state; 2427 2428 return; 2429 } 2430 2431 /** 2432 * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3 2433 * @hw: pointer to the HW structure 2434 * 2435 * Workaround for 82566 power-down on D3 entry: 2436 * 1) disable gigabit link 2437 * 2) write VR power-down enable 2438 * 3) read it back 2439 * Continue if successful, else issue LCD reset and repeat 2440 **/ 2441 void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw) 2442 { 2443 u32 reg; 2444 u16 data; 2445 u8 retry = 0; 2446 2447 DEBUGFUNC("e1000_igp3_phy_powerdown_workaround_ich8lan"); 2448 2449 if (hw->phy.type != e1000_phy_igp_3) 2450 goto out; 2451 2452 /* Try the workaround twice (if needed) */ 2453 do { 2454 /* Disable link */ 2455 reg = E1000_READ_REG(hw, E1000_PHY_CTRL); 2456 reg |= (E1000_PHY_CTRL_GBE_DISABLE | 2457 E1000_PHY_CTRL_NOND0A_GBE_DISABLE); 2458 E1000_WRITE_REG(hw, E1000_PHY_CTRL, reg); 2459 2460 /* 2461 * Call gig speed drop workaround on Gig disable before 2462 * accessing any PHY registers 2463 */ 2464 if (hw->mac.type == e1000_ich8lan) 2465 e1000_gig_downshift_workaround_ich8lan(hw); 2466 2467 /* Write VR power-down enable */ 2468 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data); 2469 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; 2470 hw->phy.ops.write_reg(hw, IGP3_VR_CTRL, 2471 data | IGP3_VR_CTRL_MODE_SHUTDOWN); 2472 2473 /* Read it back and test */ 2474 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data); 2475 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; 2476 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry) 2477 break; 2478 2479 /* Issue PHY reset and repeat at most one more time */ 2480 reg = E1000_READ_REG(hw, E1000_CTRL); 2481 E1000_WRITE_REG(hw, E1000_CTRL, reg | E1000_CTRL_PHY_RST); 2482 retry++; 2483 } while (retry); 2484 2485 out: 2486 return; 2487 } 2488 2489 /** 2490 * e1000_gig_downshift_workaround_ich8lan - WoL from S5 stops working 2491 * @hw: pointer to the HW structure 2492 * 2493 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC), 2494 * LPLU, Gig disable, MDIC PHY reset): 2495 * 1) Set Kumeran Near-end loopback 2496 * 2) Clear Kumeran Near-end loopback 2497 * Should only be called for ICH8[m] devices with IGP_3 Phy. 2498 **/ 2499 void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw) 2500 { 2501 s32 ret_val = E1000_SUCCESS; 2502 u16 reg_data; 2503 2504 DEBUGFUNC("e1000_gig_downshift_workaround_ich8lan"); 2505 2506 if ((hw->mac.type != e1000_ich8lan) || 2507 (hw->phy.type != e1000_phy_igp_3)) 2508 goto out; 2509 2510 ret_val = e1000_read_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, 2511 ®_data); 2512 if (ret_val) 2513 goto out; 2514 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK; 2515 ret_val = e1000_write_kmrn_reg_generic(hw, 2516 E1000_KMRNCTRLSTA_DIAG_OFFSET, 2517 reg_data); 2518 if (ret_val) 2519 goto out; 2520 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK; 2521 ret_val = e1000_write_kmrn_reg_generic(hw, 2522 E1000_KMRNCTRLSTA_DIAG_OFFSET, 2523 reg_data); 2524 out: 2525 return; 2526 } 2527 2528 /** 2529 * e1000_disable_gig_wol_ich8lan - disable gig during WoL 2530 * @hw: pointer to the HW structure 2531 * 2532 * During S0 to Sx transition, it is possible the link remains at gig 2533 * instead of negotiating to a lower speed. Before going to Sx, set 2534 * 'LPLU Enabled' and 'Gig Disable' to force link speed negotiation 2535 * to a lower speed. 2536 * 2537 * Should only be called for applicable parts. 2538 **/ 2539 void e1000_disable_gig_wol_ich8lan(struct e1000_hw *hw) 2540 { 2541 u32 phy_ctrl; 2542 2543 switch (hw->mac.type) { 2544 case e1000_ich9lan: 2545 case e1000_ich10lan: 2546 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL); 2547 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU | 2548 E1000_PHY_CTRL_GBE_DISABLE; 2549 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 2550 default: 2551 break; 2552 } 2553 2554 return; 2555 } 2556 2557 /** 2558 * e1000_cleanup_led_ich8lan - Restore the default LED operation 2559 * @hw: pointer to the HW structure 2560 * 2561 * Return the LED back to the default configuration. 2562 **/ 2563 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw) 2564 { 2565 s32 ret_val = E1000_SUCCESS; 2566 2567 DEBUGFUNC("e1000_cleanup_led_ich8lan"); 2568 2569 if (hw->phy.type == e1000_phy_ife) 2570 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, 2571 0); 2572 else 2573 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default); 2574 2575 return ret_val; 2576 } 2577 2578 /** 2579 * e1000_led_on_ich8lan - Turn LEDs on 2580 * @hw: pointer to the HW structure 2581 * 2582 * Turn on the LEDs. 2583 **/ 2584 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw) 2585 { 2586 s32 ret_val = E1000_SUCCESS; 2587 2588 DEBUGFUNC("e1000_led_on_ich8lan"); 2589 2590 if (hw->phy.type == e1000_phy_ife) 2591 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, 2592 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON)); 2593 else 2594 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2); 2595 2596 return ret_val; 2597 } 2598 2599 /** 2600 * e1000_led_off_ich8lan - Turn LEDs off 2601 * @hw: pointer to the HW structure 2602 * 2603 * Turn off the LEDs. 2604 **/ 2605 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw) 2606 { 2607 s32 ret_val = E1000_SUCCESS; 2608 2609 DEBUGFUNC("e1000_led_off_ich8lan"); 2610 2611 if (hw->phy.type == e1000_phy_ife) 2612 ret_val = hw->phy.ops.write_reg(hw, 2613 IFE_PHY_SPECIAL_CONTROL_LED, 2614 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF)); 2615 else 2616 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 2617 2618 return ret_val; 2619 } 2620 2621 /** 2622 * e1000_get_cfg_done_ich8lan - Read config done bit 2623 * @hw: pointer to the HW structure 2624 * 2625 * Read the management control register for the config done bit for 2626 * completion status. NOTE: silicon which is EEPROM-less will fail trying 2627 * to read the config done bit, so an error is *ONLY* logged and returns 2628 * E1000_SUCCESS. If we were to return with error, EEPROM-less silicon 2629 * would not be able to be reset or change link. 2630 **/ 2631 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw) 2632 { 2633 s32 ret_val = E1000_SUCCESS; 2634 u32 bank = 0; 2635 2636 e1000_get_cfg_done_generic(hw); 2637 2638 /* If EEPROM is not marked present, init the IGP 3 PHY manually */ 2639 if (hw->mac.type != e1000_ich10lan) { 2640 if (((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0) && 2641 (hw->phy.type == e1000_phy_igp_3)) { 2642 e1000_phy_init_script_igp3(hw); 2643 } 2644 } else { 2645 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) { 2646 /* Maybe we should do a basic PHY config */ 2647 DEBUGOUT("EEPROM not present\n"); 2648 ret_val = -E1000_ERR_CONFIG; 2649 } 2650 } 2651 2652 return ret_val; 2653 } 2654 2655 /** 2656 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down 2657 * @hw: pointer to the HW structure 2658 * 2659 * In the case of a PHY power down to save power, or to turn off link during a 2660 * driver unload, or wake on lan is not enabled, remove the link. 2661 **/ 2662 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw) 2663 { 2664 /* If the management interface is not enabled, then power down */ 2665 if (!(hw->mac.ops.check_mng_mode(hw) || 2666 hw->phy.ops.check_reset_block(hw))) 2667 e1000_power_down_phy_copper(hw); 2668 2669 return; 2670 } 2671 2672 /** 2673 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters 2674 * @hw: pointer to the HW structure 2675 * 2676 * Clears hardware counters specific to the silicon family and calls 2677 * clear_hw_cntrs_generic to clear all general purpose counters. 2678 **/ 2679 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw) 2680 { 2681 DEBUGFUNC("e1000_clear_hw_cntrs_ich8lan"); 2682 2683 e1000_clear_hw_cntrs_base_generic(hw); 2684 2685 E1000_READ_REG(hw, E1000_ALGNERRC); 2686 E1000_READ_REG(hw, E1000_RXERRC); 2687 E1000_READ_REG(hw, E1000_TNCRS); 2688 E1000_READ_REG(hw, E1000_CEXTERR); 2689 E1000_READ_REG(hw, E1000_TSCTC); 2690 E1000_READ_REG(hw, E1000_TSCTFC); 2691 2692 E1000_READ_REG(hw, E1000_MGTPRC); 2693 E1000_READ_REG(hw, E1000_MGTPDC); 2694 E1000_READ_REG(hw, E1000_MGTPTC); 2695 2696 E1000_READ_REG(hw, E1000_IAC); 2697 E1000_READ_REG(hw, E1000_ICRXOC); 2698 } 2699 2700