1 /****************************************************************************** 2 3 Copyright (c) 2001-2010, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 /* 36 * 82571EB Gigabit Ethernet Controller 37 * 82571EB Gigabit Ethernet Controller (Copper) 38 * 82571EB Gigabit Ethernet Controller (Fiber) 39 * 82571EB Dual Port Gigabit Mezzanine Adapter 40 * 82571EB Quad Port Gigabit Mezzanine Adapter 41 * 82571PT Gigabit PT Quad Port Server ExpressModule 42 * 82572EI Gigabit Ethernet Controller (Copper) 43 * 82572EI Gigabit Ethernet Controller (Fiber) 44 * 82572EI Gigabit Ethernet Controller 45 * 82573V Gigabit Ethernet Controller (Copper) 46 * 82573E Gigabit Ethernet Controller (Copper) 47 * 82573L Gigabit Ethernet Controller 48 * 82574L Gigabit Network Connection 49 * 82583V Gigabit Network Connection 50 */ 51 52 #include "e1000_api.h" 53 54 static s32 e1000_init_phy_params_82571(struct e1000_hw *hw); 55 static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw); 56 static s32 e1000_init_mac_params_82571(struct e1000_hw *hw); 57 static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw); 58 static void e1000_release_nvm_82571(struct e1000_hw *hw); 59 static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, 60 u16 words, u16 *data); 61 static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw); 62 static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw); 63 static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw); 64 static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, 65 bool active); 66 static s32 e1000_reset_hw_82571(struct e1000_hw *hw); 67 static s32 e1000_init_hw_82571(struct e1000_hw *hw); 68 static void e1000_clear_vfta_82571(struct e1000_hw *hw); 69 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw); 70 static s32 e1000_led_on_82574(struct e1000_hw *hw); 71 static s32 e1000_setup_link_82571(struct e1000_hw *hw); 72 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw); 73 static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw); 74 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw); 75 static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data); 76 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw); 77 static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw); 78 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw); 79 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw); 80 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw); 81 static s32 e1000_get_hw_semaphore_82573(struct e1000_hw *hw); 82 static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw); 83 static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw); 84 static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw); 85 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw); 86 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, 87 u16 words, u16 *data); 88 static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw); 89 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw); 90 91 /** 92 * e1000_init_phy_params_82571 - Init PHY func ptrs. 93 * @hw: pointer to the HW structure 94 **/ 95 static s32 e1000_init_phy_params_82571(struct e1000_hw *hw) 96 { 97 struct e1000_phy_info *phy = &hw->phy; 98 struct e1000_dev_spec_82571 *dev_spec = &hw->dev_spec._82571; 99 s32 ret_val = E1000_SUCCESS; 100 101 DEBUGFUNC("e1000_init_phy_params_82571"); 102 103 if (hw->phy.media_type != e1000_media_type_copper) { 104 phy->type = e1000_phy_none; 105 goto out; 106 } 107 108 phy->addr = 1; 109 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 110 phy->reset_delay_us = 100; 111 112 phy->ops.check_reset_block = e1000_check_reset_block_generic; 113 phy->ops.reset = e1000_phy_hw_reset_generic; 114 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82571; 115 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic; 116 phy->ops.power_up = e1000_power_up_phy_copper; 117 phy->ops.power_down = e1000_power_down_phy_copper_82571; 118 119 switch (hw->mac.type) { 120 case e1000_82571: 121 case e1000_82572: 122 phy->type = e1000_phy_igp_2; 123 phy->ops.get_cfg_done = e1000_get_cfg_done_82571; 124 phy->ops.get_info = e1000_get_phy_info_igp; 125 phy->ops.check_polarity = e1000_check_polarity_igp; 126 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp; 127 phy->ops.get_cable_length = e1000_get_cable_length_igp_2; 128 phy->ops.read_reg = e1000_read_phy_reg_igp; 129 phy->ops.write_reg = e1000_write_phy_reg_igp; 130 phy->ops.acquire = e1000_get_hw_semaphore_82571; 131 phy->ops.release = e1000_put_hw_semaphore_82571; 132 133 /* This uses above function pointers */ 134 ret_val = e1000_get_phy_id_82571(hw); 135 136 /* Verify PHY ID */ 137 if (phy->id != IGP01E1000_I_PHY_ID) { 138 ret_val = -E1000_ERR_PHY; 139 DEBUGOUT1("PHY ID unknown: type = 0x%08x\n", phy->id); 140 goto out; 141 } 142 break; 143 case e1000_82573: 144 phy->type = e1000_phy_m88; 145 phy->ops.get_cfg_done = e1000_get_cfg_done_generic; 146 phy->ops.get_info = e1000_get_phy_info_m88; 147 phy->ops.check_polarity = e1000_check_polarity_m88; 148 phy->ops.commit = e1000_phy_sw_reset_generic; 149 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88; 150 phy->ops.get_cable_length = e1000_get_cable_length_m88; 151 phy->ops.read_reg = e1000_read_phy_reg_m88; 152 phy->ops.write_reg = e1000_write_phy_reg_m88; 153 phy->ops.acquire = e1000_get_hw_semaphore_82571; 154 phy->ops.release = e1000_put_hw_semaphore_82571; 155 156 /* This uses above function pointers */ 157 ret_val = e1000_get_phy_id_82571(hw); 158 159 /* Verify PHY ID */ 160 if (phy->id != M88E1111_I_PHY_ID) { 161 ret_val = -E1000_ERR_PHY; 162 DEBUGOUT1("PHY ID unknown: type = 0x%08x\n", phy->id); 163 goto out; 164 } 165 break; 166 case e1000_82574: 167 case e1000_82583: 168 E1000_MUTEX_INIT(&dev_spec->swflag_mutex); 169 170 phy->type = e1000_phy_bm; 171 phy->ops.get_cfg_done = e1000_get_cfg_done_generic; 172 phy->ops.get_info = e1000_get_phy_info_m88; 173 phy->ops.check_polarity = e1000_check_polarity_m88; 174 phy->ops.commit = e1000_phy_sw_reset_generic; 175 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88; 176 phy->ops.get_cable_length = e1000_get_cable_length_m88; 177 phy->ops.read_reg = e1000_read_phy_reg_bm2; 178 phy->ops.write_reg = e1000_write_phy_reg_bm2; 179 phy->ops.acquire = e1000_get_hw_semaphore_82574; 180 phy->ops.release = e1000_put_hw_semaphore_82574; 181 182 /* This uses above function pointers */ 183 ret_val = e1000_get_phy_id_82571(hw); 184 /* Verify PHY ID */ 185 if (phy->id != BME1000_E_PHY_ID_R2) { 186 ret_val = -E1000_ERR_PHY; 187 DEBUGOUT1("PHY ID unknown: type = 0x%08x\n", phy->id); 188 goto out; 189 } 190 break; 191 default: 192 ret_val = -E1000_ERR_PHY; 193 goto out; 194 break; 195 } 196 197 out: 198 return ret_val; 199 } 200 201 /** 202 * e1000_init_nvm_params_82571 - Init NVM func ptrs. 203 * @hw: pointer to the HW structure 204 **/ 205 static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw) 206 { 207 struct e1000_nvm_info *nvm = &hw->nvm; 208 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 209 u16 size; 210 211 DEBUGFUNC("e1000_init_nvm_params_82571"); 212 213 nvm->opcode_bits = 8; 214 nvm->delay_usec = 1; 215 switch (nvm->override) { 216 case e1000_nvm_override_spi_large: 217 nvm->page_size = 32; 218 nvm->address_bits = 16; 219 break; 220 case e1000_nvm_override_spi_small: 221 nvm->page_size = 8; 222 nvm->address_bits = 8; 223 break; 224 default: 225 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; 226 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8; 227 break; 228 } 229 230 switch (hw->mac.type) { 231 case e1000_82573: 232 case e1000_82574: 233 case e1000_82583: 234 if (((eecd >> 15) & 0x3) == 0x3) { 235 nvm->type = e1000_nvm_flash_hw; 236 nvm->word_size = 2048; 237 /* 238 * Autonomous Flash update bit must be cleared due 239 * to Flash update issue. 240 */ 241 eecd &= ~E1000_EECD_AUPDEN; 242 E1000_WRITE_REG(hw, E1000_EECD, eecd); 243 break; 244 } 245 /* Fall Through */ 246 default: 247 nvm->type = e1000_nvm_eeprom_spi; 248 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> 249 E1000_EECD_SIZE_EX_SHIFT); 250 /* 251 * Added to a constant, "size" becomes the left-shift value 252 * for setting word_size. 253 */ 254 size += NVM_WORD_SIZE_BASE_SHIFT; 255 256 /* EEPROM access above 16k is unsupported */ 257 if (size > 14) 258 size = 14; 259 nvm->word_size = 1 << size; 260 break; 261 } 262 263 /* Function Pointers */ 264 switch (hw->mac.type) { 265 case e1000_82574: 266 case e1000_82583: 267 nvm->ops.acquire = e1000_get_hw_semaphore_82574; 268 nvm->ops.release = e1000_put_hw_semaphore_82574; 269 break; 270 default: 271 nvm->ops.acquire = e1000_acquire_nvm_82571; 272 nvm->ops.release = e1000_release_nvm_82571; 273 break; 274 } 275 nvm->ops.read = e1000_read_nvm_eerd; 276 nvm->ops.update = e1000_update_nvm_checksum_82571; 277 nvm->ops.validate = e1000_validate_nvm_checksum_82571; 278 nvm->ops.valid_led_default = e1000_valid_led_default_82571; 279 nvm->ops.write = e1000_write_nvm_82571; 280 281 return E1000_SUCCESS; 282 } 283 284 /** 285 * e1000_init_mac_params_82571 - Init MAC func ptrs. 286 * @hw: pointer to the HW structure 287 **/ 288 static s32 e1000_init_mac_params_82571(struct e1000_hw *hw) 289 { 290 struct e1000_mac_info *mac = &hw->mac; 291 u32 swsm = 0; 292 u32 swsm2 = 0; 293 bool force_clear_smbi = FALSE; 294 295 DEBUGFUNC("e1000_init_mac_params_82571"); 296 297 /* Set media type and media-dependent function pointers */ 298 switch (hw->device_id) { 299 case E1000_DEV_ID_82571EB_FIBER: 300 case E1000_DEV_ID_82572EI_FIBER: 301 case E1000_DEV_ID_82571EB_QUAD_FIBER: 302 hw->phy.media_type = e1000_media_type_fiber; 303 mac->ops.setup_physical_interface = 304 e1000_setup_fiber_serdes_link_82571; 305 mac->ops.check_for_link = e1000_check_for_fiber_link_generic; 306 mac->ops.get_link_up_info = 307 e1000_get_speed_and_duplex_fiber_serdes_generic; 308 break; 309 case E1000_DEV_ID_82571EB_SERDES: 310 case E1000_DEV_ID_82571EB_SERDES_DUAL: 311 case E1000_DEV_ID_82571EB_SERDES_QUAD: 312 case E1000_DEV_ID_82572EI_SERDES: 313 hw->phy.media_type = e1000_media_type_internal_serdes; 314 mac->ops.setup_physical_interface = 315 e1000_setup_fiber_serdes_link_82571; 316 mac->ops.check_for_link = e1000_check_for_serdes_link_82571; 317 mac->ops.get_link_up_info = 318 e1000_get_speed_and_duplex_fiber_serdes_generic; 319 break; 320 default: 321 hw->phy.media_type = e1000_media_type_copper; 322 mac->ops.setup_physical_interface = 323 e1000_setup_copper_link_82571; 324 mac->ops.check_for_link = e1000_check_for_copper_link_generic; 325 mac->ops.get_link_up_info = 326 e1000_get_speed_and_duplex_copper_generic; 327 break; 328 } 329 330 /* Set mta register count */ 331 mac->mta_reg_count = 128; 332 /* Set rar entry count */ 333 mac->rar_entry_count = E1000_RAR_ENTRIES; 334 /* Set if part includes ASF firmware */ 335 mac->asf_firmware_present = TRUE; 336 /* Adaptive IFS supported */ 337 mac->adaptive_ifs = TRUE; 338 339 /* Function pointers */ 340 341 /* bus type/speed/width */ 342 mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic; 343 /* reset */ 344 mac->ops.reset_hw = e1000_reset_hw_82571; 345 /* hw initialization */ 346 mac->ops.init_hw = e1000_init_hw_82571; 347 /* link setup */ 348 mac->ops.setup_link = e1000_setup_link_82571; 349 /* multicast address update */ 350 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic; 351 /* writing VFTA */ 352 mac->ops.write_vfta = e1000_write_vfta_generic; 353 /* clearing VFTA */ 354 mac->ops.clear_vfta = e1000_clear_vfta_82571; 355 /* read mac address */ 356 mac->ops.read_mac_addr = e1000_read_mac_addr_82571; 357 /* ID LED init */ 358 mac->ops.id_led_init = e1000_id_led_init_generic; 359 /* blink LED */ 360 mac->ops.blink_led = e1000_blink_led_generic; 361 /* setup LED */ 362 mac->ops.setup_led = e1000_setup_led_generic; 363 /* cleanup LED */ 364 mac->ops.cleanup_led = e1000_cleanup_led_generic; 365 /* turn off LED */ 366 mac->ops.led_off = e1000_led_off_generic; 367 /* clear hardware counters */ 368 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82571; 369 370 /* MAC-specific function pointers */ 371 switch (hw->mac.type) { 372 case e1000_82573: 373 mac->ops.set_lan_id = e1000_set_lan_id_single_port; 374 mac->ops.check_mng_mode = e1000_check_mng_mode_generic; 375 mac->ops.led_on = e1000_led_on_generic; 376 377 /* FWSM register */ 378 mac->has_fwsm = TRUE; 379 /* 380 * ARC supported; valid only if manageability features are 381 * enabled. 382 */ 383 mac->arc_subsystem_valid = 384 (E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK) 385 ? TRUE : FALSE; 386 break; 387 case e1000_82574: 388 case e1000_82583: 389 mac->ops.set_lan_id = e1000_set_lan_id_single_port; 390 mac->ops.check_mng_mode = e1000_check_mng_mode_82574; 391 mac->ops.led_on = e1000_led_on_82574; 392 break; 393 default: 394 mac->ops.check_mng_mode = e1000_check_mng_mode_generic; 395 mac->ops.led_on = e1000_led_on_generic; 396 397 /* FWSM register */ 398 mac->has_fwsm = TRUE; 399 break; 400 } 401 402 /* 403 * Ensure that the inter-port SWSM.SMBI lock bit is clear before 404 * first NVM or PHY acess. This should be done for single-port 405 * devices, and for one port only on dual-port devices so that 406 * for those devices we can still use the SMBI lock to synchronize 407 * inter-port accesses to the PHY & NVM. 408 */ 409 switch (hw->mac.type) { 410 case e1000_82571: 411 case e1000_82572: 412 swsm2 = E1000_READ_REG(hw, E1000_SWSM2); 413 414 if (!(swsm2 & E1000_SWSM2_LOCK)) { 415 /* Only do this for the first interface on this card */ 416 E1000_WRITE_REG(hw, E1000_SWSM2, 417 swsm2 | E1000_SWSM2_LOCK); 418 force_clear_smbi = TRUE; 419 } else 420 force_clear_smbi = FALSE; 421 break; 422 default: 423 force_clear_smbi = TRUE; 424 break; 425 } 426 427 if (force_clear_smbi) { 428 /* Make sure SWSM.SMBI is clear */ 429 swsm = E1000_READ_REG(hw, E1000_SWSM); 430 if (swsm & E1000_SWSM_SMBI) { 431 /* This bit should not be set on a first interface, and 432 * indicates that the bootagent or EFI code has 433 * improperly left this bit enabled 434 */ 435 DEBUGOUT("Please update your 82571 Bootagent\n"); 436 } 437 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_SMBI); 438 } 439 440 /* 441 * Initialze device specific counter of SMBI acquisition 442 * timeouts. 443 */ 444 hw->dev_spec._82571.smb_counter = 0; 445 446 return E1000_SUCCESS; 447 } 448 449 /** 450 * e1000_init_function_pointers_82571 - Init func ptrs. 451 * @hw: pointer to the HW structure 452 * 453 * Called to initialize all function pointers and parameters. 454 **/ 455 void e1000_init_function_pointers_82571(struct e1000_hw *hw) 456 { 457 DEBUGFUNC("e1000_init_function_pointers_82571"); 458 459 hw->mac.ops.init_params = e1000_init_mac_params_82571; 460 hw->nvm.ops.init_params = e1000_init_nvm_params_82571; 461 hw->phy.ops.init_params = e1000_init_phy_params_82571; 462 } 463 464 /** 465 * e1000_get_phy_id_82571 - Retrieve the PHY ID and revision 466 * @hw: pointer to the HW structure 467 * 468 * Reads the PHY registers and stores the PHY ID and possibly the PHY 469 * revision in the hardware structure. 470 **/ 471 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw) 472 { 473 struct e1000_phy_info *phy = &hw->phy; 474 s32 ret_val = E1000_SUCCESS; 475 u16 phy_id = 0; 476 477 DEBUGFUNC("e1000_get_phy_id_82571"); 478 479 switch (hw->mac.type) { 480 case e1000_82571: 481 case e1000_82572: 482 /* 483 * The 82571 firmware may still be configuring the PHY. 484 * In this case, we cannot access the PHY until the 485 * configuration is done. So we explicitly set the 486 * PHY ID. 487 */ 488 phy->id = IGP01E1000_I_PHY_ID; 489 break; 490 case e1000_82573: 491 ret_val = e1000_get_phy_id(hw); 492 break; 493 case e1000_82574: 494 case e1000_82583: 495 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id); 496 if (ret_val) 497 goto out; 498 499 phy->id = (u32)(phy_id << 16); 500 usec_delay(20); 501 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id); 502 if (ret_val) 503 goto out; 504 505 phy->id |= (u32)(phy_id); 506 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); 507 break; 508 default: 509 ret_val = -E1000_ERR_PHY; 510 break; 511 } 512 out: 513 return ret_val; 514 } 515 516 /** 517 * e1000_get_hw_semaphore_82571 - Acquire hardware semaphore 518 * @hw: pointer to the HW structure 519 * 520 * Acquire the HW semaphore to access the PHY or NVM 521 **/ 522 static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw) 523 { 524 u32 swsm; 525 s32 ret_val = E1000_SUCCESS; 526 s32 sw_timeout = hw->nvm.word_size + 1; 527 s32 fw_timeout = hw->nvm.word_size + 1; 528 s32 i = 0; 529 530 DEBUGFUNC("e1000_get_hw_semaphore_82571"); 531 532 /* 533 * If we have timedout 3 times on trying to acquire 534 * the inter-port SMBI semaphore, there is old code 535 * operating on the other port, and it is not 536 * releasing SMBI. Modify the number of times that 537 * we try for the semaphore to interwork with this 538 * older code. 539 */ 540 if (hw->dev_spec._82571.smb_counter > 2) 541 sw_timeout = 1; 542 543 /* Get the SW semaphore */ 544 while (i < sw_timeout) { 545 swsm = E1000_READ_REG(hw, E1000_SWSM); 546 if (!(swsm & E1000_SWSM_SMBI)) 547 break; 548 549 usec_delay(50); 550 i++; 551 } 552 553 if (i == sw_timeout) { 554 DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); 555 hw->dev_spec._82571.smb_counter++; 556 } 557 /* Get the FW semaphore. */ 558 for (i = 0; i < fw_timeout; i++) { 559 swsm = E1000_READ_REG(hw, E1000_SWSM); 560 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI); 561 562 /* Semaphore acquired if bit latched */ 563 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI) 564 break; 565 566 usec_delay(50); 567 } 568 569 if (i == fw_timeout) { 570 /* Release semaphores */ 571 e1000_put_hw_semaphore_82571(hw); 572 DEBUGOUT("Driver can't access the NVM\n"); 573 ret_val = -E1000_ERR_NVM; 574 goto out; 575 } 576 577 out: 578 return ret_val; 579 } 580 581 /** 582 * e1000_put_hw_semaphore_82571 - Release hardware semaphore 583 * @hw: pointer to the HW structure 584 * 585 * Release hardware semaphore used to access the PHY or NVM 586 **/ 587 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw) 588 { 589 u32 swsm; 590 591 DEBUGFUNC("e1000_put_hw_semaphore_generic"); 592 593 swsm = E1000_READ_REG(hw, E1000_SWSM); 594 595 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); 596 597 E1000_WRITE_REG(hw, E1000_SWSM, swsm); 598 } 599 600 /** 601 * e1000_get_hw_semaphore_82573 - Acquire hardware semaphore 602 * @hw: pointer to the HW structure 603 * 604 * Acquire the HW semaphore during reset. 605 * 606 **/ 607 static s32 e1000_get_hw_semaphore_82573(struct e1000_hw *hw) 608 { 609 u32 extcnf_ctrl; 610 s32 ret_val = E1000_SUCCESS; 611 s32 i = 0; 612 613 DEBUGFUNC("e1000_get_hw_semaphore_82573"); 614 615 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 616 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; 617 do { 618 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); 619 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 620 621 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP) 622 break; 623 624 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; 625 626 msec_delay(2); 627 i++; 628 } while (i < MDIO_OWNERSHIP_TIMEOUT); 629 630 if (i == MDIO_OWNERSHIP_TIMEOUT) { 631 /* Release semaphores */ 632 e1000_put_hw_semaphore_82573(hw); 633 DEBUGOUT("Driver can't access the PHY\n"); 634 ret_val = -E1000_ERR_PHY; 635 goto out; 636 } 637 638 out: 639 return ret_val; 640 } 641 642 /** 643 * e1000_put_hw_semaphore_82573 - Release hardware semaphore 644 * @hw: pointer to the HW structure 645 * 646 * Release hardware semaphore used during reset. 647 * 648 **/ 649 static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw) 650 { 651 u32 extcnf_ctrl; 652 653 DEBUGFUNC("e1000_put_hw_semaphore_82573"); 654 655 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 656 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; 657 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); 658 } 659 660 /** 661 * e1000_get_hw_semaphore_82574 - Acquire hardware semaphore 662 * @hw: pointer to the HW structure 663 * 664 * Acquire the HW semaphore to access the PHY or NVM. 665 * 666 **/ 667 static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw) 668 { 669 DEBUGFUNC("e1000_get_hw_semaphore_82574"); 670 671 E1000_MUTEX_LOCK(&hw->dev_spec._82571.swflag_mutex); 672 return e1000_get_hw_semaphore_82573(hw); 673 } 674 675 /** 676 * e1000_put_hw_semaphore_82574 - Release hardware semaphore 677 * @hw: pointer to the HW structure 678 * 679 * Release hardware semaphore used to access the PHY or NVM 680 * 681 **/ 682 static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw) 683 { 684 DEBUGFUNC("e1000_put_hw_semaphore_82574"); 685 686 e1000_put_hw_semaphore_82573(hw); 687 E1000_MUTEX_UNLOCK(&hw->dev_spec._82571.swflag_mutex); 688 } 689 690 /** 691 * e1000_acquire_nvm_82571 - Request for access to the EEPROM 692 * @hw: pointer to the HW structure 693 * 694 * To gain access to the EEPROM, first we must obtain a hardware semaphore. 695 * Then for non-82573 hardware, set the EEPROM access request bit and wait 696 * for EEPROM access grant bit. If the access grant bit is not set, release 697 * hardware semaphore. 698 **/ 699 static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw) 700 { 701 s32 ret_val; 702 703 DEBUGFUNC("e1000_acquire_nvm_82571"); 704 705 ret_val = e1000_get_hw_semaphore_82571(hw); 706 if (ret_val) 707 goto out; 708 709 switch (hw->mac.type) { 710 case e1000_82573: 711 break; 712 default: 713 ret_val = e1000_acquire_nvm_generic(hw); 714 break; 715 } 716 717 if (ret_val) 718 e1000_put_hw_semaphore_82571(hw); 719 720 out: 721 return ret_val; 722 } 723 724 /** 725 * e1000_release_nvm_82571 - Release exclusive access to EEPROM 726 * @hw: pointer to the HW structure 727 * 728 * Stop any current commands to the EEPROM and clear the EEPROM request bit. 729 **/ 730 static void e1000_release_nvm_82571(struct e1000_hw *hw) 731 { 732 DEBUGFUNC("e1000_release_nvm_82571"); 733 734 e1000_release_nvm_generic(hw); 735 e1000_put_hw_semaphore_82571(hw); 736 } 737 738 /** 739 * e1000_write_nvm_82571 - Write to EEPROM using appropriate interface 740 * @hw: pointer to the HW structure 741 * @offset: offset within the EEPROM to be written to 742 * @words: number of words to write 743 * @data: 16 bit word(s) to be written to the EEPROM 744 * 745 * For non-82573 silicon, write data to EEPROM at offset using SPI interface. 746 * 747 * If e1000_update_nvm_checksum is not called after this function, the 748 * EEPROM will most likely contain an invalid checksum. 749 **/ 750 static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words, 751 u16 *data) 752 { 753 s32 ret_val = E1000_SUCCESS; 754 755 DEBUGFUNC("e1000_write_nvm_82571"); 756 757 switch (hw->mac.type) { 758 case e1000_82573: 759 case e1000_82574: 760 case e1000_82583: 761 ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data); 762 break; 763 case e1000_82571: 764 case e1000_82572: 765 ret_val = e1000_write_nvm_spi(hw, offset, words, data); 766 break; 767 default: 768 ret_val = -E1000_ERR_NVM; 769 break; 770 } 771 772 return ret_val; 773 } 774 775 /** 776 * e1000_update_nvm_checksum_82571 - Update EEPROM checksum 777 * @hw: pointer to the HW structure 778 * 779 * Updates the EEPROM checksum by reading/adding each word of the EEPROM 780 * up to the checksum. Then calculates the EEPROM checksum and writes the 781 * value to the EEPROM. 782 **/ 783 static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw) 784 { 785 u32 eecd; 786 s32 ret_val; 787 u16 i; 788 789 DEBUGFUNC("e1000_update_nvm_checksum_82571"); 790 791 ret_val = e1000_update_nvm_checksum_generic(hw); 792 if (ret_val) 793 goto out; 794 795 /* 796 * If our nvm is an EEPROM, then we're done 797 * otherwise, commit the checksum to the flash NVM. 798 */ 799 if (hw->nvm.type != e1000_nvm_flash_hw) 800 goto out; 801 802 /* Check for pending operations. */ 803 for (i = 0; i < E1000_FLASH_UPDATES; i++) { 804 msec_delay(1); 805 if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD) == 0) 806 break; 807 } 808 809 if (i == E1000_FLASH_UPDATES) { 810 ret_val = -E1000_ERR_NVM; 811 goto out; 812 } 813 814 /* Reset the firmware if using STM opcode. */ 815 if ((E1000_READ_REG(hw, E1000_FLOP) & 0xFF00) == E1000_STM_OPCODE) { 816 /* 817 * The enabling of and the actual reset must be done 818 * in two write cycles. 819 */ 820 E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET_ENABLE); 821 E1000_WRITE_FLUSH(hw); 822 E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET); 823 } 824 825 /* Commit the write to flash */ 826 eecd = E1000_READ_REG(hw, E1000_EECD) | E1000_EECD_FLUPD; 827 E1000_WRITE_REG(hw, E1000_EECD, eecd); 828 829 for (i = 0; i < E1000_FLASH_UPDATES; i++) { 830 msec_delay(1); 831 if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD) == 0) 832 break; 833 } 834 835 if (i == E1000_FLASH_UPDATES) { 836 ret_val = -E1000_ERR_NVM; 837 goto out; 838 } 839 840 out: 841 return ret_val; 842 } 843 844 /** 845 * e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum 846 * @hw: pointer to the HW structure 847 * 848 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM 849 * and then verifies that the sum of the EEPROM is equal to 0xBABA. 850 **/ 851 static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw) 852 { 853 DEBUGFUNC("e1000_validate_nvm_checksum_82571"); 854 855 if (hw->nvm.type == e1000_nvm_flash_hw) 856 e1000_fix_nvm_checksum_82571(hw); 857 858 return e1000_validate_nvm_checksum_generic(hw); 859 } 860 861 /** 862 * e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon 863 * @hw: pointer to the HW structure 864 * @offset: offset within the EEPROM to be written to 865 * @words: number of words to write 866 * @data: 16 bit word(s) to be written to the EEPROM 867 * 868 * After checking for invalid values, poll the EEPROM to ensure the previous 869 * command has completed before trying to write the next word. After write 870 * poll for completion. 871 * 872 * If e1000_update_nvm_checksum is not called after this function, the 873 * EEPROM will most likely contain an invalid checksum. 874 **/ 875 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, 876 u16 words, u16 *data) 877 { 878 struct e1000_nvm_info *nvm = &hw->nvm; 879 u32 i, eewr = 0; 880 s32 ret_val = 0; 881 882 DEBUGFUNC("e1000_write_nvm_eewr_82571"); 883 884 /* 885 * A check for invalid values: offset too large, too many words, 886 * and not enough words. 887 */ 888 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 889 (words == 0)) { 890 DEBUGOUT("nvm parameter(s) out of bounds\n"); 891 ret_val = -E1000_ERR_NVM; 892 goto out; 893 } 894 895 for (i = 0; i < words; i++) { 896 eewr = (data[i] << E1000_NVM_RW_REG_DATA) | 897 ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) | 898 E1000_NVM_RW_REG_START; 899 900 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE); 901 if (ret_val) 902 break; 903 904 E1000_WRITE_REG(hw, E1000_EEWR, eewr); 905 906 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE); 907 if (ret_val) 908 break; 909 } 910 911 out: 912 return ret_val; 913 } 914 915 /** 916 * e1000_get_cfg_done_82571 - Poll for configuration done 917 * @hw: pointer to the HW structure 918 * 919 * Reads the management control register for the config done bit to be set. 920 **/ 921 static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw) 922 { 923 s32 timeout = PHY_CFG_TIMEOUT; 924 s32 ret_val = E1000_SUCCESS; 925 926 DEBUGFUNC("e1000_get_cfg_done_82571"); 927 928 while (timeout) { 929 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & 930 E1000_NVM_CFG_DONE_PORT_0) 931 break; 932 msec_delay(1); 933 timeout--; 934 } 935 if (!timeout) { 936 DEBUGOUT("MNG configuration cycle has not completed.\n"); 937 ret_val = -E1000_ERR_RESET; 938 goto out; 939 } 940 941 out: 942 return ret_val; 943 } 944 945 /** 946 * e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state 947 * @hw: pointer to the HW structure 948 * @active: TRUE to enable LPLU, FALSE to disable 949 * 950 * Sets the LPLU D0 state according to the active flag. When activating LPLU 951 * this function also disables smart speed and vice versa. LPLU will not be 952 * activated unless the device autonegotiation advertisement meets standards 953 * of either 10 or 10/100 or 10/100/1000 at all duplexes. This is a function 954 * pointer entry point only called by PHY setup routines. 955 **/ 956 static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active) 957 { 958 struct e1000_phy_info *phy = &hw->phy; 959 s32 ret_val = E1000_SUCCESS; 960 u16 data; 961 962 DEBUGFUNC("e1000_set_d0_lplu_state_82571"); 963 964 if (!(phy->ops.read_reg)) 965 goto out; 966 967 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); 968 if (ret_val) 969 goto out; 970 971 if (active) { 972 data |= IGP02E1000_PM_D0_LPLU; 973 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 974 data); 975 if (ret_val) 976 goto out; 977 978 /* When LPLU is enabled, we should disable SmartSpeed */ 979 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 980 &data); 981 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 982 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 983 data); 984 if (ret_val) 985 goto out; 986 } else { 987 data &= ~IGP02E1000_PM_D0_LPLU; 988 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 989 data); 990 /* 991 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 992 * during Dx states where the power conservation is most 993 * important. During driver activity we should enable 994 * SmartSpeed, so performance is maintained. 995 */ 996 if (phy->smart_speed == e1000_smart_speed_on) { 997 ret_val = phy->ops.read_reg(hw, 998 IGP01E1000_PHY_PORT_CONFIG, 999 &data); 1000 if (ret_val) 1001 goto out; 1002 1003 data |= IGP01E1000_PSCFR_SMART_SPEED; 1004 ret_val = phy->ops.write_reg(hw, 1005 IGP01E1000_PHY_PORT_CONFIG, 1006 data); 1007 if (ret_val) 1008 goto out; 1009 } else if (phy->smart_speed == e1000_smart_speed_off) { 1010 ret_val = phy->ops.read_reg(hw, 1011 IGP01E1000_PHY_PORT_CONFIG, 1012 &data); 1013 if (ret_val) 1014 goto out; 1015 1016 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1017 ret_val = phy->ops.write_reg(hw, 1018 IGP01E1000_PHY_PORT_CONFIG, 1019 data); 1020 if (ret_val) 1021 goto out; 1022 } 1023 } 1024 1025 out: 1026 return ret_val; 1027 } 1028 1029 /** 1030 * e1000_reset_hw_82571 - Reset hardware 1031 * @hw: pointer to the HW structure 1032 * 1033 * This resets the hardware into a known state. 1034 **/ 1035 static s32 e1000_reset_hw_82571(struct e1000_hw *hw) 1036 { 1037 u32 ctrl, ctrl_ext, icr; 1038 s32 ret_val; 1039 1040 DEBUGFUNC("e1000_reset_hw_82571"); 1041 1042 /* 1043 * Prevent the PCI-E bus from sticking if there is no TLP connection 1044 * on the last TLP read/write transaction when MAC is reset. 1045 */ 1046 ret_val = e1000_disable_pcie_master_generic(hw); 1047 if (ret_val) 1048 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 1049 1050 DEBUGOUT("Masking off all interrupts\n"); 1051 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 1052 1053 E1000_WRITE_REG(hw, E1000_RCTL, 0); 1054 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 1055 E1000_WRITE_FLUSH(hw); 1056 1057 msec_delay(10); 1058 1059 /* 1060 * Must acquire the MDIO ownership before MAC reset. 1061 * Ownership defaults to firmware after a reset. 1062 */ 1063 switch (hw->mac.type) { 1064 case e1000_82573: 1065 ret_val = e1000_get_hw_semaphore_82573(hw); 1066 break; 1067 case e1000_82574: 1068 case e1000_82583: 1069 ret_val = e1000_get_hw_semaphore_82574(hw); 1070 break; 1071 default: 1072 break; 1073 } 1074 if (ret_val) 1075 DEBUGOUT("Cannot acquire MDIO ownership\n"); 1076 1077 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1078 1079 DEBUGOUT("Issuing a global reset to MAC\n"); 1080 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 1081 1082 /* Must release MDIO ownership and mutex after MAC reset. */ 1083 switch (hw->mac.type) { 1084 case e1000_82574: 1085 case e1000_82583: 1086 e1000_put_hw_semaphore_82574(hw); 1087 break; 1088 default: 1089 break; 1090 } 1091 1092 if (hw->nvm.type == e1000_nvm_flash_hw) { 1093 usec_delay(10); 1094 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 1095 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 1096 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 1097 E1000_WRITE_FLUSH(hw); 1098 } 1099 1100 ret_val = e1000_get_auto_rd_done_generic(hw); 1101 if (ret_val) 1102 /* We don't want to continue accessing MAC registers. */ 1103 goto out; 1104 1105 /* 1106 * Phy configuration from NVM just starts after EECD_AUTO_RD is set. 1107 * Need to wait for Phy configuration completion before accessing 1108 * NVM and Phy. 1109 */ 1110 1111 switch (hw->mac.type) { 1112 case e1000_82573: 1113 case e1000_82574: 1114 case e1000_82583: 1115 msec_delay(25); 1116 break; 1117 default: 1118 break; 1119 } 1120 1121 /* Clear any pending interrupt events. */ 1122 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 1123 icr = E1000_READ_REG(hw, E1000_ICR); 1124 1125 if (hw->mac.type == e1000_82571) { 1126 /* Install any alternate MAC address into RAR0 */ 1127 ret_val = e1000_check_alt_mac_addr_generic(hw); 1128 if (ret_val) 1129 goto out; 1130 1131 e1000_set_laa_state_82571(hw, TRUE); 1132 } 1133 1134 /* Reinitialize the 82571 serdes link state machine */ 1135 if (hw->phy.media_type == e1000_media_type_internal_serdes) 1136 hw->mac.serdes_link_state = e1000_serdes_link_down; 1137 1138 out: 1139 return ret_val; 1140 } 1141 1142 /** 1143 * e1000_init_hw_82571 - Initialize hardware 1144 * @hw: pointer to the HW structure 1145 * 1146 * This inits the hardware readying it for operation. 1147 **/ 1148 static s32 e1000_init_hw_82571(struct e1000_hw *hw) 1149 { 1150 struct e1000_mac_info *mac = &hw->mac; 1151 u32 reg_data; 1152 s32 ret_val; 1153 u16 i, rar_count = mac->rar_entry_count; 1154 1155 DEBUGFUNC("e1000_init_hw_82571"); 1156 1157 e1000_initialize_hw_bits_82571(hw); 1158 1159 /* Initialize identification LED */ 1160 ret_val = mac->ops.id_led_init(hw); 1161 if (ret_val) 1162 DEBUGOUT("Error initializing identification LED\n"); 1163 /* This is not fatal and we should not stop init due to this */ 1164 1165 /* Disabling VLAN filtering */ 1166 DEBUGOUT("Initializing the IEEE VLAN\n"); 1167 mac->ops.clear_vfta(hw); 1168 1169 /* Setup the receive address. */ 1170 /* 1171 * If, however, a locally administered address was assigned to the 1172 * 82571, we must reserve a RAR for it to work around an issue where 1173 * resetting one port will reload the MAC on the other port. 1174 */ 1175 if (e1000_get_laa_state_82571(hw)) 1176 rar_count--; 1177 e1000_init_rx_addrs_generic(hw, rar_count); 1178 1179 /* Zero out the Multicast HASH table */ 1180 DEBUGOUT("Zeroing the MTA\n"); 1181 for (i = 0; i < mac->mta_reg_count; i++) 1182 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 1183 1184 /* Setup link and flow control */ 1185 ret_val = mac->ops.setup_link(hw); 1186 1187 /* Set the transmit descriptor write-back policy */ 1188 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0)); 1189 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | 1190 E1000_TXDCTL_FULL_TX_DESC_WB | 1191 E1000_TXDCTL_COUNT_DESC; 1192 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data); 1193 1194 /* ...for both queues. */ 1195 switch (mac->type) { 1196 case e1000_82573: 1197 e1000_enable_tx_pkt_filtering_generic(hw); 1198 /* fall through */ 1199 case e1000_82574: 1200 case e1000_82583: 1201 reg_data = E1000_READ_REG(hw, E1000_GCR); 1202 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; 1203 E1000_WRITE_REG(hw, E1000_GCR, reg_data); 1204 break; 1205 default: 1206 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1)); 1207 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | 1208 E1000_TXDCTL_FULL_TX_DESC_WB | 1209 E1000_TXDCTL_COUNT_DESC; 1210 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data); 1211 break; 1212 } 1213 1214 /* 1215 * Clear all of the statistics registers (clear on read). It is 1216 * important that we do this after we have tried to establish link 1217 * because the symbol error count will increment wildly if there 1218 * is no link. 1219 */ 1220 e1000_clear_hw_cntrs_82571(hw); 1221 1222 return ret_val; 1223 } 1224 1225 /** 1226 * e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits 1227 * @hw: pointer to the HW structure 1228 * 1229 * Initializes required hardware-dependent bits needed for normal operation. 1230 **/ 1231 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw) 1232 { 1233 u32 reg; 1234 1235 DEBUGFUNC("e1000_initialize_hw_bits_82571"); 1236 1237 /* Transmit Descriptor Control 0 */ 1238 reg = E1000_READ_REG(hw, E1000_TXDCTL(0)); 1239 reg |= (1 << 22); 1240 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg); 1241 1242 /* Transmit Descriptor Control 1 */ 1243 reg = E1000_READ_REG(hw, E1000_TXDCTL(1)); 1244 reg |= (1 << 22); 1245 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg); 1246 1247 /* Transmit Arbitration Control 0 */ 1248 reg = E1000_READ_REG(hw, E1000_TARC(0)); 1249 reg &= ~(0xF << 27); /* 30:27 */ 1250 switch (hw->mac.type) { 1251 case e1000_82571: 1252 case e1000_82572: 1253 reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26); 1254 break; 1255 default: 1256 break; 1257 } 1258 E1000_WRITE_REG(hw, E1000_TARC(0), reg); 1259 1260 /* Transmit Arbitration Control 1 */ 1261 reg = E1000_READ_REG(hw, E1000_TARC(1)); 1262 switch (hw->mac.type) { 1263 case e1000_82571: 1264 case e1000_82572: 1265 reg &= ~((1 << 29) | (1 << 30)); 1266 reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26); 1267 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR) 1268 reg &= ~(1 << 28); 1269 else 1270 reg |= (1 << 28); 1271 E1000_WRITE_REG(hw, E1000_TARC(1), reg); 1272 break; 1273 default: 1274 break; 1275 } 1276 1277 /* Device Control */ 1278 switch (hw->mac.type) { 1279 case e1000_82573: 1280 case e1000_82574: 1281 case e1000_82583: 1282 reg = E1000_READ_REG(hw, E1000_CTRL); 1283 reg &= ~(1 << 29); 1284 E1000_WRITE_REG(hw, E1000_CTRL, reg); 1285 break; 1286 default: 1287 break; 1288 } 1289 1290 /* Extended Device Control */ 1291 switch (hw->mac.type) { 1292 case e1000_82573: 1293 case e1000_82574: 1294 case e1000_82583: 1295 reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 1296 reg &= ~(1 << 23); 1297 reg |= (1 << 22); 1298 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 1299 break; 1300 default: 1301 break; 1302 } 1303 1304 if (hw->mac.type == e1000_82571) { 1305 reg = E1000_READ_REG(hw, E1000_PBA_ECC); 1306 reg |= E1000_PBA_ECC_CORR_EN; 1307 E1000_WRITE_REG(hw, E1000_PBA_ECC, reg); 1308 } 1309 1310 /* 1311 * Workaround for hardware errata. 1312 * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572 1313 */ 1314 if ((hw->mac.type == e1000_82571) || 1315 (hw->mac.type == e1000_82572)) { 1316 reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 1317 reg &= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN; 1318 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 1319 } 1320 1321 /* PCI-Ex Control Registers */ 1322 switch (hw->mac.type) { 1323 case e1000_82574: 1324 case e1000_82583: 1325 reg = E1000_READ_REG(hw, E1000_GCR); 1326 reg |= (1 << 22); 1327 E1000_WRITE_REG(hw, E1000_GCR, reg); 1328 1329 /* 1330 * Workaround for hardware errata. 1331 * apply workaround for hardware errata documented in errata 1332 * docs Fixes issue where some error prone or unreliable PCIe 1333 * completions are occurring, particularly with ASPM enabled. 1334 * Without fix, issue can cause tx timeouts. 1335 */ 1336 reg = E1000_READ_REG(hw, E1000_GCR2); 1337 reg |= 1; 1338 E1000_WRITE_REG(hw, E1000_GCR2, reg); 1339 break; 1340 default: 1341 break; 1342 } 1343 1344 return; 1345 } 1346 1347 /** 1348 * e1000_clear_vfta_82571 - Clear VLAN filter table 1349 * @hw: pointer to the HW structure 1350 * 1351 * Clears the register array which contains the VLAN filter table by 1352 * setting all the values to 0. 1353 **/ 1354 static void e1000_clear_vfta_82571(struct e1000_hw *hw) 1355 { 1356 u32 offset; 1357 u32 vfta_value = 0; 1358 u32 vfta_offset = 0; 1359 u32 vfta_bit_in_reg = 0; 1360 1361 DEBUGFUNC("e1000_clear_vfta_82571"); 1362 1363 switch (hw->mac.type) { 1364 case e1000_82573: 1365 case e1000_82574: 1366 case e1000_82583: 1367 if (hw->mng_cookie.vlan_id != 0) { 1368 /* 1369 * The VFTA is a 4096b bit-field, each identifying 1370 * a single VLAN ID. The following operations 1371 * determine which 32b entry (i.e. offset) into the 1372 * array we want to set the VLAN ID (i.e. bit) of 1373 * the manageability unit. 1374 */ 1375 vfta_offset = (hw->mng_cookie.vlan_id >> 1376 E1000_VFTA_ENTRY_SHIFT) & E1000_VFTA_ENTRY_MASK; 1377 vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id & 1378 E1000_VFTA_ENTRY_BIT_SHIFT_MASK); 1379 } 1380 break; 1381 default: 1382 break; 1383 } 1384 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 1385 /* 1386 * If the offset we want to clear is the same offset of the 1387 * manageability VLAN ID, then clear all bits except that of 1388 * the manageability unit. 1389 */ 1390 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0; 1391 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value); 1392 E1000_WRITE_FLUSH(hw); 1393 } 1394 } 1395 1396 /** 1397 * e1000_check_mng_mode_82574 - Check manageability is enabled 1398 * @hw: pointer to the HW structure 1399 * 1400 * Reads the NVM Initialization Control Word 2 and returns TRUE 1401 * (>0) if any manageability is enabled, else FALSE (0). 1402 **/ 1403 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw) 1404 { 1405 u16 data; 1406 1407 DEBUGFUNC("e1000_check_mng_mode_82574"); 1408 1409 hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &data); 1410 return (data & E1000_NVM_INIT_CTRL2_MNGM) != 0; 1411 } 1412 1413 /** 1414 * e1000_led_on_82574 - Turn LED on 1415 * @hw: pointer to the HW structure 1416 * 1417 * Turn LED on. 1418 **/ 1419 static s32 e1000_led_on_82574(struct e1000_hw *hw) 1420 { 1421 u32 ctrl; 1422 u32 i; 1423 1424 DEBUGFUNC("e1000_led_on_82574"); 1425 1426 ctrl = hw->mac.ledctl_mode2; 1427 if (!(E1000_STATUS_LU & E1000_READ_REG(hw, E1000_STATUS))) { 1428 /* 1429 * If no link, then turn LED on by setting the invert bit 1430 * for each LED that's "on" (0x0E) in ledctl_mode2. 1431 */ 1432 for (i = 0; i < 4; i++) 1433 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) == 1434 E1000_LEDCTL_MODE_LED_ON) 1435 ctrl |= (E1000_LEDCTL_LED0_IVRT << (i * 8)); 1436 } 1437 E1000_WRITE_REG(hw, E1000_LEDCTL, ctrl); 1438 1439 return E1000_SUCCESS; 1440 } 1441 1442 /** 1443 * e1000_check_phy_82574 - check 82574 phy hung state 1444 * @hw: pointer to the HW structure 1445 * 1446 * Returns whether phy is hung or not 1447 **/ 1448 bool e1000_check_phy_82574(struct e1000_hw *hw) 1449 { 1450 u16 status_1kbt = 0; 1451 u16 receive_errors = 0; 1452 bool phy_hung = FALSE; 1453 s32 ret_val = E1000_SUCCESS; 1454 1455 DEBUGFUNC("e1000_check_phy_82574"); 1456 1457 /* 1458 * Read PHY Receive Error counter first, if its is max - all F's then 1459 * read the Base1000T status register If both are max then PHY is hung. 1460 */ 1461 ret_val = hw->phy.ops.read_reg(hw, E1000_RECEIVE_ERROR_COUNTER, 1462 &receive_errors); 1463 if (ret_val) 1464 goto out; 1465 if (receive_errors == E1000_RECEIVE_ERROR_MAX) { 1466 ret_val = hw->phy.ops.read_reg(hw, E1000_BASE1000T_STATUS, 1467 &status_1kbt); 1468 if (ret_val) 1469 goto out; 1470 if ((status_1kbt & E1000_IDLE_ERROR_COUNT_MASK) == 1471 E1000_IDLE_ERROR_COUNT_MASK) 1472 phy_hung = TRUE; 1473 } 1474 out: 1475 return phy_hung; 1476 } 1477 1478 1479 /** 1480 * e1000_setup_link_82571 - Setup flow control and link settings 1481 * @hw: pointer to the HW structure 1482 * 1483 * Determines which flow control settings to use, then configures flow 1484 * control. Calls the appropriate media-specific link configuration 1485 * function. Assuming the adapter has a valid link partner, a valid link 1486 * should be established. Assumes the hardware has previously been reset 1487 * and the transmitter and receiver are not enabled. 1488 **/ 1489 static s32 e1000_setup_link_82571(struct e1000_hw *hw) 1490 { 1491 DEBUGFUNC("e1000_setup_link_82571"); 1492 1493 /* 1494 * 82573 does not have a word in the NVM to determine 1495 * the default flow control setting, so we explicitly 1496 * set it to full. 1497 */ 1498 switch (hw->mac.type) { 1499 case e1000_82573: 1500 case e1000_82574: 1501 case e1000_82583: 1502 if (hw->fc.requested_mode == e1000_fc_default) 1503 hw->fc.requested_mode = e1000_fc_full; 1504 break; 1505 default: 1506 break; 1507 } 1508 return e1000_setup_link_generic(hw); 1509 } 1510 1511 /** 1512 * e1000_setup_copper_link_82571 - Configure copper link settings 1513 * @hw: pointer to the HW structure 1514 * 1515 * Configures the link for auto-neg or forced speed and duplex. Then we check 1516 * for link, once link is established calls to configure collision distance 1517 * and flow control are called. 1518 **/ 1519 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw) 1520 { 1521 u32 ctrl; 1522 s32 ret_val; 1523 1524 DEBUGFUNC("e1000_setup_copper_link_82571"); 1525 1526 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1527 ctrl |= E1000_CTRL_SLU; 1528 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1529 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1530 1531 switch (hw->phy.type) { 1532 case e1000_phy_m88: 1533 case e1000_phy_bm: 1534 ret_val = e1000_copper_link_setup_m88(hw); 1535 break; 1536 case e1000_phy_igp_2: 1537 ret_val = e1000_copper_link_setup_igp(hw); 1538 break; 1539 default: 1540 ret_val = -E1000_ERR_PHY; 1541 break; 1542 } 1543 1544 if (ret_val) 1545 goto out; 1546 1547 ret_val = e1000_setup_copper_link_generic(hw); 1548 1549 out: 1550 return ret_val; 1551 } 1552 1553 /** 1554 * e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes 1555 * @hw: pointer to the HW structure 1556 * 1557 * Configures collision distance and flow control for fiber and serdes links. 1558 * Upon successful setup, poll for link. 1559 **/ 1560 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw) 1561 { 1562 DEBUGFUNC("e1000_setup_fiber_serdes_link_82571"); 1563 1564 switch (hw->mac.type) { 1565 case e1000_82571: 1566 case e1000_82572: 1567 /* 1568 * If SerDes loopback mode is entered, there is no form 1569 * of reset to take the adapter out of that mode. So we 1570 * have to explicitly take the adapter out of loopback 1571 * mode. This prevents drivers from twiddling their thumbs 1572 * if another tool failed to take it out of loopback mode. 1573 */ 1574 E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK); 1575 break; 1576 default: 1577 break; 1578 } 1579 1580 return e1000_setup_fiber_serdes_link_generic(hw); 1581 } 1582 1583 /** 1584 * e1000_check_for_serdes_link_82571 - Check for link (Serdes) 1585 * @hw: pointer to the HW structure 1586 * 1587 * Reports the link state as up or down. 1588 * 1589 * If autonegotiation is supported by the link partner, the link state is 1590 * determined by the result of autonegotiation. This is the most likely case. 1591 * If autonegotiation is not supported by the link partner, and the link 1592 * has a valid signal, force the link up. 1593 * 1594 * The link state is represented internally here by 4 states: 1595 * 1596 * 1) down 1597 * 2) autoneg_progress 1598 * 3) autoneg_complete (the link sucessfully autonegotiated) 1599 * 4) forced_up (the link has been forced up, it did not autonegotiate) 1600 * 1601 **/ 1602 static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw) 1603 { 1604 struct e1000_mac_info *mac = &hw->mac; 1605 u32 rxcw; 1606 u32 ctrl; 1607 u32 status; 1608 u32 txcw; 1609 u32 i; 1610 s32 ret_val = E1000_SUCCESS; 1611 1612 DEBUGFUNC("e1000_check_for_serdes_link_82571"); 1613 1614 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1615 status = E1000_READ_REG(hw, E1000_STATUS); 1616 rxcw = E1000_READ_REG(hw, E1000_RXCW); 1617 1618 if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) { 1619 1620 /* Receiver is synchronized with no invalid bits. */ 1621 switch (mac->serdes_link_state) { 1622 case e1000_serdes_link_autoneg_complete: 1623 if (!(status & E1000_STATUS_LU)) { 1624 /* 1625 * We have lost link, retry autoneg before 1626 * reporting link failure 1627 */ 1628 mac->serdes_link_state = 1629 e1000_serdes_link_autoneg_progress; 1630 mac->serdes_has_link = FALSE; 1631 DEBUGOUT("AN_UP -> AN_PROG\n"); 1632 } else { 1633 mac->serdes_has_link = TRUE; 1634 } 1635 break; 1636 1637 case e1000_serdes_link_forced_up: 1638 /* 1639 * If we are receiving /C/ ordered sets, re-enable 1640 * auto-negotiation in the TXCW register and disable 1641 * forced link in the Device Control register in an 1642 * attempt to auto-negotiate with our link partner. 1643 * If the partner code word is null, stop forcing 1644 * and restart auto negotiation. 1645 */ 1646 if ((rxcw & E1000_RXCW_C) || !(rxcw & E1000_RXCW_CW)) { 1647 /* Enable autoneg, and unforce link up */ 1648 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 1649 E1000_WRITE_REG(hw, E1000_CTRL, 1650 (ctrl & ~E1000_CTRL_SLU)); 1651 mac->serdes_link_state = 1652 e1000_serdes_link_autoneg_progress; 1653 mac->serdes_has_link = FALSE; 1654 DEBUGOUT("FORCED_UP -> AN_PROG\n"); 1655 } else { 1656 mac->serdes_has_link = TRUE; 1657 } 1658 break; 1659 1660 case e1000_serdes_link_autoneg_progress: 1661 if (rxcw & E1000_RXCW_C) { 1662 /* 1663 * We received /C/ ordered sets, meaning the 1664 * link partner has autonegotiated, and we can 1665 * trust the Link Up (LU) status bit. 1666 */ 1667 if (status & E1000_STATUS_LU) { 1668 mac->serdes_link_state = 1669 e1000_serdes_link_autoneg_complete; 1670 DEBUGOUT("AN_PROG -> AN_UP\n"); 1671 mac->serdes_has_link = TRUE; 1672 } else { 1673 /* Autoneg completed, but failed. */ 1674 mac->serdes_link_state = 1675 e1000_serdes_link_down; 1676 DEBUGOUT("AN_PROG -> DOWN\n"); 1677 } 1678 } else { 1679 /* 1680 * The link partner did not autoneg. 1681 * Force link up and full duplex, and change 1682 * state to forced. 1683 */ 1684 E1000_WRITE_REG(hw, E1000_TXCW, 1685 (mac->txcw & ~E1000_TXCW_ANE)); 1686 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 1687 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1688 1689 /* Configure Flow Control after link up. */ 1690 ret_val = 1691 e1000_config_fc_after_link_up_generic(hw); 1692 if (ret_val) { 1693 DEBUGOUT("Error config flow control\n"); 1694 break; 1695 } 1696 mac->serdes_link_state = 1697 e1000_serdes_link_forced_up; 1698 mac->serdes_has_link = TRUE; 1699 DEBUGOUT("AN_PROG -> FORCED_UP\n"); 1700 } 1701 break; 1702 1703 case e1000_serdes_link_down: 1704 default: 1705 /* 1706 * The link was down but the receiver has now gained 1707 * valid sync, so lets see if we can bring the link 1708 * up. 1709 */ 1710 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 1711 E1000_WRITE_REG(hw, E1000_CTRL, 1712 (ctrl & ~E1000_CTRL_SLU)); 1713 mac->serdes_link_state = 1714 e1000_serdes_link_autoneg_progress; 1715 mac->serdes_has_link = FALSE; 1716 DEBUGOUT("DOWN -> AN_PROG\n"); 1717 break; 1718 } 1719 } else { 1720 if (!(rxcw & E1000_RXCW_SYNCH)) { 1721 mac->serdes_has_link = FALSE; 1722 mac->serdes_link_state = e1000_serdes_link_down; 1723 DEBUGOUT("ANYSTATE -> DOWN\n"); 1724 } else { 1725 /* 1726 * Check several times, if Sync and Config 1727 * both are consistently 1 then simply ignore 1728 * the Invalid bit and restart Autoneg 1729 */ 1730 for (i = 0; i < AN_RETRY_COUNT; i++) { 1731 usec_delay(10); 1732 rxcw = E1000_READ_REG(hw, E1000_RXCW); 1733 if ((rxcw & E1000_RXCW_IV) && 1734 !((rxcw & E1000_RXCW_SYNCH) && 1735 (rxcw & E1000_RXCW_C))) { 1736 mac->serdes_has_link = FALSE; 1737 mac->serdes_link_state = 1738 e1000_serdes_link_down; 1739 DEBUGOUT("ANYSTATE -> DOWN\n"); 1740 break; 1741 } 1742 } 1743 1744 if (i == AN_RETRY_COUNT) { 1745 txcw = E1000_READ_REG(hw, E1000_TXCW); 1746 txcw |= E1000_TXCW_ANE; 1747 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 1748 mac->serdes_link_state = 1749 e1000_serdes_link_autoneg_progress; 1750 mac->serdes_has_link = FALSE; 1751 DEBUGOUT("ANYSTATE -> AN_PROG\n"); 1752 } 1753 } 1754 } 1755 1756 return ret_val; 1757 } 1758 1759 /** 1760 * e1000_valid_led_default_82571 - Verify a valid default LED config 1761 * @hw: pointer to the HW structure 1762 * @data: pointer to the NVM (EEPROM) 1763 * 1764 * Read the EEPROM for the current default LED configuration. If the 1765 * LED configuration is not valid, set to a valid LED configuration. 1766 **/ 1767 static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data) 1768 { 1769 s32 ret_val; 1770 1771 DEBUGFUNC("e1000_valid_led_default_82571"); 1772 1773 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); 1774 if (ret_val) { 1775 DEBUGOUT("NVM Read Error\n"); 1776 goto out; 1777 } 1778 1779 switch (hw->mac.type) { 1780 case e1000_82573: 1781 case e1000_82574: 1782 case e1000_82583: 1783 if (*data == ID_LED_RESERVED_F746) 1784 *data = ID_LED_DEFAULT_82573; 1785 break; 1786 default: 1787 if (*data == ID_LED_RESERVED_0000 || 1788 *data == ID_LED_RESERVED_FFFF) 1789 *data = ID_LED_DEFAULT; 1790 break; 1791 } 1792 1793 out: 1794 return ret_val; 1795 } 1796 1797 /** 1798 * e1000_get_laa_state_82571 - Get locally administered address state 1799 * @hw: pointer to the HW structure 1800 * 1801 * Retrieve and return the current locally administered address state. 1802 **/ 1803 bool e1000_get_laa_state_82571(struct e1000_hw *hw) 1804 { 1805 DEBUGFUNC("e1000_get_laa_state_82571"); 1806 1807 if (hw->mac.type != e1000_82571) 1808 return FALSE; 1809 1810 return hw->dev_spec._82571.laa_is_present; 1811 } 1812 1813 /** 1814 * e1000_set_laa_state_82571 - Set locally administered address state 1815 * @hw: pointer to the HW structure 1816 * @state: enable/disable locally administered address 1817 * 1818 * Enable/Disable the current locally administered address state. 1819 **/ 1820 void e1000_set_laa_state_82571(struct e1000_hw *hw, bool state) 1821 { 1822 DEBUGFUNC("e1000_set_laa_state_82571"); 1823 1824 if (hw->mac.type != e1000_82571) 1825 return; 1826 1827 hw->dev_spec._82571.laa_is_present = state; 1828 1829 /* If workaround is activated... */ 1830 if (state) 1831 /* 1832 * Hold a copy of the LAA in RAR[14] This is done so that 1833 * between the time RAR[0] gets clobbered and the time it 1834 * gets fixed, the actual LAA is in one of the RARs and no 1835 * incoming packets directed to this port are dropped. 1836 * Eventually the LAA will be in RAR[0] and RAR[14]. 1837 */ 1838 e1000_rar_set_generic(hw, hw->mac.addr, 1839 hw->mac.rar_entry_count - 1); 1840 return; 1841 } 1842 1843 /** 1844 * e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum 1845 * @hw: pointer to the HW structure 1846 * 1847 * Verifies that the EEPROM has completed the update. After updating the 1848 * EEPROM, we need to check bit 15 in work 0x23 for the checksum fix. If 1849 * the checksum fix is not implemented, we need to set the bit and update 1850 * the checksum. Otherwise, if bit 15 is set and the checksum is incorrect, 1851 * we need to return bad checksum. 1852 **/ 1853 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw) 1854 { 1855 struct e1000_nvm_info *nvm = &hw->nvm; 1856 s32 ret_val = E1000_SUCCESS; 1857 u16 data; 1858 1859 DEBUGFUNC("e1000_fix_nvm_checksum_82571"); 1860 1861 if (nvm->type != e1000_nvm_flash_hw) 1862 goto out; 1863 1864 /* 1865 * Check bit 4 of word 10h. If it is 0, firmware is done updating 1866 * 10h-12h. Checksum may need to be fixed. 1867 */ 1868 ret_val = nvm->ops.read(hw, 0x10, 1, &data); 1869 if (ret_val) 1870 goto out; 1871 1872 if (!(data & 0x10)) { 1873 /* 1874 * Read 0x23 and check bit 15. This bit is a 1 1875 * when the checksum has already been fixed. If 1876 * the checksum is still wrong and this bit is a 1877 * 1, we need to return bad checksum. Otherwise, 1878 * we need to set this bit to a 1 and update the 1879 * checksum. 1880 */ 1881 ret_val = nvm->ops.read(hw, 0x23, 1, &data); 1882 if (ret_val) 1883 goto out; 1884 1885 if (!(data & 0x8000)) { 1886 data |= 0x8000; 1887 ret_val = nvm->ops.write(hw, 0x23, 1, &data); 1888 if (ret_val) 1889 goto out; 1890 ret_val = nvm->ops.update(hw); 1891 } 1892 } 1893 1894 out: 1895 return ret_val; 1896 } 1897 1898 1899 /** 1900 * e1000_read_mac_addr_82571 - Read device MAC address 1901 * @hw: pointer to the HW structure 1902 **/ 1903 static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw) 1904 { 1905 s32 ret_val = E1000_SUCCESS; 1906 1907 DEBUGFUNC("e1000_read_mac_addr_82571"); 1908 1909 if (hw->mac.type == e1000_82571) { 1910 /* 1911 * If there's an alternate MAC address place it in RAR0 1912 * so that it will override the Si installed default perm 1913 * address. 1914 */ 1915 ret_val = e1000_check_alt_mac_addr_generic(hw); 1916 if (ret_val) 1917 goto out; 1918 } 1919 1920 ret_val = e1000_read_mac_addr_generic(hw); 1921 1922 out: 1923 return ret_val; 1924 } 1925 1926 /** 1927 * e1000_power_down_phy_copper_82571 - Remove link during PHY power down 1928 * @hw: pointer to the HW structure 1929 * 1930 * In the case of a PHY power down to save power, or to turn off link during a 1931 * driver unload, or wake on lan is not enabled, remove the link. 1932 **/ 1933 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw) 1934 { 1935 struct e1000_phy_info *phy = &hw->phy; 1936 struct e1000_mac_info *mac = &hw->mac; 1937 1938 if (!(phy->ops.check_reset_block)) 1939 return; 1940 1941 /* If the management interface is not enabled, then power down */ 1942 if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw))) 1943 e1000_power_down_phy_copper(hw); 1944 1945 return; 1946 } 1947 1948 /** 1949 * e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters 1950 * @hw: pointer to the HW structure 1951 * 1952 * Clears the hardware counters by reading the counter registers. 1953 **/ 1954 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw) 1955 { 1956 DEBUGFUNC("e1000_clear_hw_cntrs_82571"); 1957 1958 e1000_clear_hw_cntrs_base_generic(hw); 1959 1960 E1000_READ_REG(hw, E1000_PRC64); 1961 E1000_READ_REG(hw, E1000_PRC127); 1962 E1000_READ_REG(hw, E1000_PRC255); 1963 E1000_READ_REG(hw, E1000_PRC511); 1964 E1000_READ_REG(hw, E1000_PRC1023); 1965 E1000_READ_REG(hw, E1000_PRC1522); 1966 E1000_READ_REG(hw, E1000_PTC64); 1967 E1000_READ_REG(hw, E1000_PTC127); 1968 E1000_READ_REG(hw, E1000_PTC255); 1969 E1000_READ_REG(hw, E1000_PTC511); 1970 E1000_READ_REG(hw, E1000_PTC1023); 1971 E1000_READ_REG(hw, E1000_PTC1522); 1972 1973 E1000_READ_REG(hw, E1000_ALGNERRC); 1974 E1000_READ_REG(hw, E1000_RXERRC); 1975 E1000_READ_REG(hw, E1000_TNCRS); 1976 E1000_READ_REG(hw, E1000_CEXTERR); 1977 E1000_READ_REG(hw, E1000_TSCTC); 1978 E1000_READ_REG(hw, E1000_TSCTFC); 1979 1980 E1000_READ_REG(hw, E1000_MGTPRC); 1981 E1000_READ_REG(hw, E1000_MGTPDC); 1982 E1000_READ_REG(hw, E1000_MGTPTC); 1983 1984 E1000_READ_REG(hw, E1000_IAC); 1985 E1000_READ_REG(hw, E1000_ICRXOC); 1986 1987 E1000_READ_REG(hw, E1000_ICRXPTC); 1988 E1000_READ_REG(hw, E1000_ICRXATC); 1989 E1000_READ_REG(hw, E1000_ICTXPTC); 1990 E1000_READ_REG(hw, E1000_ICTXATC); 1991 E1000_READ_REG(hw, E1000_ICTXQEC); 1992 E1000_READ_REG(hw, E1000_ICTXQMTC); 1993 E1000_READ_REG(hw, E1000_ICRXDMTC); 1994 } 1995