1 /* 2 * aQuantia Corporation Network Driver 3 * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * (1) Redistributions of source code must retain the above 10 * copyright notice, this list of conditions and the following 11 * disclaimer. 12 * 13 * (2) Redistributions in binary form must reproduce the above 14 * copyright notice, this list of conditions and the following 15 * disclaimer in the documentation and/or other materials provided 16 * with the distribution. 17 * 18 * (3)The name of the author may not be used to endorse or promote 19 * products derived from this software without specific prior 20 * written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS 23 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 26 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 28 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 31 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* File aq_hw_llh.c: Definitions of bitfield and register access functions for 36 * Atlantic registers. 37 */ 38 39 #include "aq_hw.h" 40 #include "aq_hw_llh.h" 41 #include "aq_hw_llh_internal.h" 42 43 44 /* global */ 45 46 void 47 reg_glb_fw_image_id1_set(struct aq_hw* hw, uint32_t value) 48 { 49 AQ_WRITE_REG(hw, glb_fw_image_id1_adr, value); 50 } 51 uint32_t 52 reg_glb_fw_image_id1_get(struct aq_hw* hw) 53 { 54 return AQ_READ_REG(hw, glb_fw_image_id1_adr); 55 } 56 57 void 58 reg_glb_cpu_sem_set(struct aq_hw *aq_hw, uint32_t sem_value, uint32_t sem_index) 59 { 60 AQ_WRITE_REG(aq_hw, glb_cpu_sem_adr(sem_index), sem_value); 61 } 62 63 uint32_t 64 reg_glb_cpu_sem_get(struct aq_hw *aq_hw, uint32_t sem_index) 65 { 66 return AQ_READ_REG(aq_hw, glb_cpu_sem_adr(sem_index)); 67 } 68 69 uint32_t 70 reg_glb_standard_ctl1_get(struct aq_hw* hw) 71 { 72 return AQ_READ_REG(hw, glb_standard_ctl1_adr); 73 } 74 void 75 reg_glb_standard_ctl1_set(struct aq_hw* hw, uint32_t glb_standard_ctl1) 76 { 77 AQ_WRITE_REG(hw, glb_standard_ctl1_adr, glb_standard_ctl1); 78 } 79 80 void 81 reg_global_ctl2_set(struct aq_hw* hw, uint32_t global_ctl2) 82 { 83 AQ_WRITE_REG(hw, glb_ctl2_adr, global_ctl2); 84 } 85 uint32_t 86 reg_global_ctl2_get(struct aq_hw* hw) 87 { 88 return AQ_READ_REG(hw, glb_ctl2_adr); 89 } 90 91 void 92 reg_glb_daisy_chain_status1_set(struct aq_hw* hw, 93 uint32_t glb_daisy_chain_status1) 94 { 95 AQ_WRITE_REG(hw, glb_daisy_chain_status1_adr, glb_daisy_chain_status1); 96 } 97 uint32_t 98 reg_glb_daisy_chain_status1_get(struct aq_hw* hw) 99 { 100 return AQ_READ_REG(hw, glb_daisy_chain_status1_adr); 101 } 102 103 void 104 glb_glb_reg_res_dis_set(struct aq_hw *aq_hw, uint32_t glb_reg_res_dis) 105 { 106 AQ_WRITE_REG_BIT(aq_hw, glb_reg_res_dis_adr, glb_reg_res_dis_msk, 107 glb_reg_res_dis_shift, glb_reg_res_dis); 108 } 109 110 void 111 glb_soft_res_set(struct aq_hw *aq_hw, uint32_t soft_res) 112 { 113 AQ_WRITE_REG_BIT(aq_hw, glb_soft_res_adr, glb_soft_res_msk, 114 glb_soft_res_shift, soft_res); 115 } 116 117 uint32_t 118 glb_soft_res_get(struct aq_hw *aq_hw) 119 { 120 return AQ_READ_REG_BIT(aq_hw, glb_soft_res_adr, glb_soft_res_msk, 121 glb_soft_res_shift); 122 } 123 124 uint32_t 125 reg_rx_dma_stat_counter7get(struct aq_hw *aq_hw) 126 { 127 return AQ_READ_REG(aq_hw, rx_dma_stat_counter7_adr); 128 } 129 130 uint32_t 131 reg_glb_mif_id_get(struct aq_hw *aq_hw) 132 { 133 return AQ_READ_REG(aq_hw, glb_mif_id_adr); 134 } 135 136 137 void 138 mpi_tx_reg_res_dis_set(struct aq_hw* hw, uint32_t mpi_tx_reg_res_dis) 139 { 140 AQ_WRITE_REG_BIT(hw, mpi_tx_reg_res_dis_adr, mpi_tx_reg_res_dis_msk, 141 mpi_tx_reg_res_dis_shift, mpi_tx_reg_res_dis); 142 } 143 uint32_t 144 mpi_tx_reg_res_dis_get(struct aq_hw* hw) 145 { 146 return AQ_READ_REG_BIT(hw, mpi_tx_reg_res_dis_adr, 147 mpi_tx_reg_res_dis_msk, mpi_tx_reg_res_dis_shift); 148 } 149 150 151 /* stats */ 152 uint32_t 153 rpb_rx_dma_drop_pkt_cnt_get(struct aq_hw *aq_hw) 154 { 155 return AQ_READ_REG(aq_hw, rpb_rx_dma_drop_pkt_cnt_adr); 156 } 157 158 uint32_t 159 stats_rx_dma_good_octet_counterlsw_get(struct aq_hw *aq_hw) 160 { 161 return AQ_READ_REG(aq_hw, stats_rx_dma_good_octet_counterlsw__adr); 162 } 163 164 uint32_t 165 stats_rx_dma_good_pkt_counterlsw_get(struct aq_hw *aq_hw) 166 { 167 return AQ_READ_REG(aq_hw, stats_rx_dma_good_pkt_counterlsw__adr); 168 } 169 170 uint32_t 171 stats_tx_dma_good_octet_counterlsw_get(struct aq_hw *aq_hw) 172 { 173 return AQ_READ_REG(aq_hw, stats_tx_dma_good_octet_counterlsw__adr); 174 } 175 176 uint32_t 177 stats_tx_dma_good_pkt_counterlsw_get(struct aq_hw *aq_hw) 178 { 179 return AQ_READ_REG(aq_hw, stats_tx_dma_good_pkt_counterlsw__adr); 180 } 181 182 uint32_t 183 stats_rx_dma_good_octet_countermsw_get(struct aq_hw *aq_hw) 184 { 185 return AQ_READ_REG(aq_hw, stats_rx_dma_good_octet_countermsw__adr); 186 } 187 188 uint32_t 189 stats_rx_dma_good_pkt_countermsw_get(struct aq_hw *aq_hw) 190 { 191 return AQ_READ_REG(aq_hw, stats_rx_dma_good_pkt_countermsw__adr); 192 } 193 194 uint32_t 195 stats_tx_dma_good_octet_countermsw_get(struct aq_hw *aq_hw) 196 { 197 return AQ_READ_REG(aq_hw, stats_tx_dma_good_octet_countermsw__adr); 198 } 199 200 uint32_t 201 stats_tx_dma_good_pkt_countermsw_get(struct aq_hw *aq_hw) 202 { 203 return AQ_READ_REG(aq_hw, stats_tx_dma_good_pkt_countermsw__adr); 204 } 205 206 uint32_t 207 stats_rx_lro_coalesced_pkt_count0_get(struct aq_hw *aq_hw) 208 { 209 return AQ_READ_REG(aq_hw, stats_rx_lo_coalesced_pkt_count0__addr); 210 } 211 212 /* interrupt */ 213 void 214 itr_irq_auto_masklsw_set(struct aq_hw *aq_hw, uint32_t irq_auto_masklsw) 215 { 216 AQ_WRITE_REG(aq_hw, itr_iamrlsw_adr, irq_auto_masklsw); 217 } 218 219 void 220 itr_irq_map_en_rx_set(struct aq_hw *aq_hw, uint32_t irq_map_en_rx, uint32_t rx) 221 { 222 /* register address for bitfield imr_rx{r}_en */ 223 static uint32_t itr_imr_rxren_adr[32] = { 224 0x00002100U, 0x00002100U, 0x00002104U, 0x00002104U, 225 0x00002108U, 0x00002108U, 0x0000210cU, 0x0000210cU, 226 0x00002110U, 0x00002110U, 0x00002114U, 0x00002114U, 227 0x00002118U, 0x00002118U, 0x0000211cU, 0x0000211cU, 228 0x00002120U, 0x00002120U, 0x00002124U, 0x00002124U, 229 0x00002128U, 0x00002128U, 0x0000212cU, 0x0000212cU, 230 0x00002130U, 0x00002130U, 0x00002134U, 0x00002134U, 231 0x00002138U, 0x00002138U, 0x0000213cU, 0x0000213cU 232 }; 233 234 /* bitmask for bitfield imr_rx{r}_en */ 235 static uint32_t itr_imr_rxren_msk[32] = { 236 0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U, 237 0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U, 238 0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U, 239 0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U, 240 0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U, 241 0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U, 242 0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U, 243 0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U 244 }; 245 246 /* lower bit position of bitfield imr_rx{r}_en */ 247 static uint32_t itr_imr_rxren_shift[32] = { 248 15U, 7U, 15U, 7U, 15U, 7U, 15U, 7U, 249 15U, 7U, 15U, 7U, 15U, 7U, 15U, 7U, 250 15U, 7U, 15U, 7U, 15U, 7U, 15U, 7U, 251 15U, 7U, 15U, 7U, 15U, 7U, 15U, 7U 252 }; 253 254 AQ_WRITE_REG_BIT(aq_hw, itr_imr_rxren_adr[rx], itr_imr_rxren_msk[rx], 255 itr_imr_rxren_shift[rx], irq_map_en_rx); 256 } 257 258 void 259 itr_irq_map_en_tx_set(struct aq_hw *aq_hw, uint32_t irq_map_en_tx, uint32_t tx) 260 { 261 /* register address for bitfield imr_tx{t}_en */ 262 static uint32_t itr_imr_txten_adr[32] = { 263 0x00002100U, 0x00002100U, 0x00002104U, 0x00002104U, 264 0x00002108U, 0x00002108U, 0x0000210cU, 0x0000210cU, 265 0x00002110U, 0x00002110U, 0x00002114U, 0x00002114U, 266 0x00002118U, 0x00002118U, 0x0000211cU, 0x0000211cU, 267 0x00002120U, 0x00002120U, 0x00002124U, 0x00002124U, 268 0x00002128U, 0x00002128U, 0x0000212cU, 0x0000212cU, 269 0x00002130U, 0x00002130U, 0x00002134U, 0x00002134U, 270 0x00002138U, 0x00002138U, 0x0000213cU, 0x0000213cU 271 }; 272 273 /* bitmask for bitfield imr_tx{t}_en */ 274 static uint32_t itr_imr_txten_msk[32] = { 275 0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U, 276 0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U, 277 0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U, 278 0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U, 279 0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U, 280 0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U, 281 0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U, 282 0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U 283 }; 284 285 /* lower bit position of bitfield imr_tx{t}_en */ 286 static uint32_t itr_imr_txten_shift[32] = { 287 31U, 23U, 31U, 23U, 31U, 23U, 31U, 23U, 288 31U, 23U, 31U, 23U, 31U, 23U, 31U, 23U, 289 31U, 23U, 31U, 23U, 31U, 23U, 31U, 23U, 290 31U, 23U, 31U, 23U, 31U, 23U, 31U, 23U 291 }; 292 293 AQ_WRITE_REG_BIT(aq_hw, itr_imr_txten_adr[tx], itr_imr_txten_msk[tx], 294 itr_imr_txten_shift[tx], irq_map_en_tx); 295 } 296 297 void 298 itr_irq_map_rx_set(struct aq_hw *aq_hw, uint32_t irq_map_rx, uint32_t rx) 299 { 300 /* register address for bitfield imr_rx{r}[4:0] */ 301 static uint32_t itr_imr_rxr_adr[32] = { 302 0x00002100U, 0x00002100U, 0x00002104U, 0x00002104U, 303 0x00002108U, 0x00002108U, 0x0000210cU, 0x0000210cU, 304 0x00002110U, 0x00002110U, 0x00002114U, 0x00002114U, 305 0x00002118U, 0x00002118U, 0x0000211cU, 0x0000211cU, 306 0x00002120U, 0x00002120U, 0x00002124U, 0x00002124U, 307 0x00002128U, 0x00002128U, 0x0000212cU, 0x0000212cU, 308 0x00002130U, 0x00002130U, 0x00002134U, 0x00002134U, 309 0x00002138U, 0x00002138U, 0x0000213cU, 0x0000213cU 310 }; 311 312 /* bitmask for bitfield imr_rx{r}[4:0] */ 313 static uint32_t itr_imr_rxr_msk[32] = { 314 0x00001f00U, 0x0000001fU, 0x00001f00U, 0x0000001fU, 315 0x00001f00U, 0x0000001fU, 0x00001f00U, 0x0000001fU, 316 0x00001f00U, 0x0000001fU, 0x00001f00U, 0x0000001fU, 317 0x00001f00U, 0x0000001fU, 0x00001f00U, 0x0000001fU, 318 0x00001f00U, 0x0000001fU, 0x00001f00U, 0x0000001fU, 319 0x00001f00U, 0x0000001fU, 0x00001f00U, 0x0000001fU, 320 0x00001f00U, 0x0000001fU, 0x00001f00U, 0x0000001fU, 321 0x00001f00U, 0x0000001fU, 0x00001f00U, 0x0000001fU 322 }; 323 324 /* lower bit position of bitfield imr_rx{r}[4:0] */ 325 static uint32_t itr_imr_rxr_shift[32] = { 326 8U, 0U, 8U, 0U, 8U, 0U, 8U, 0U, 327 8U, 0U, 8U, 0U, 8U, 0U, 8U, 0U, 328 8U, 0U, 8U, 0U, 8U, 0U, 8U, 0U, 329 8U, 0U, 8U, 0U, 8U, 0U, 8U, 0U 330 }; 331 332 AQ_WRITE_REG_BIT(aq_hw, itr_imr_rxr_adr[rx], itr_imr_rxr_msk[rx], 333 itr_imr_rxr_shift[rx], irq_map_rx); 334 } 335 336 void 337 itr_irq_map_tx_set(struct aq_hw *aq_hw, uint32_t irq_map_tx, uint32_t tx) 338 { 339 /* register address for bitfield imr_tx{t}[4:0] */ 340 static uint32_t itr_imr_txt_adr[32] = { 341 0x00002100U, 0x00002100U, 0x00002104U, 0x00002104U, 342 0x00002108U, 0x00002108U, 0x0000210cU, 0x0000210cU, 343 0x00002110U, 0x00002110U, 0x00002114U, 0x00002114U, 344 0x00002118U, 0x00002118U, 0x0000211cU, 0x0000211cU, 345 0x00002120U, 0x00002120U, 0x00002124U, 0x00002124U, 346 0x00002128U, 0x00002128U, 0x0000212cU, 0x0000212cU, 347 0x00002130U, 0x00002130U, 0x00002134U, 0x00002134U, 348 0x00002138U, 0x00002138U, 0x0000213cU, 0x0000213cU 349 }; 350 351 /* bitmask for bitfield imr_tx{t}[4:0] */ 352 static uint32_t itr_imr_txt_msk[32] = { 353 0x1f000000U, 0x001f0000U, 0x1f000000U, 0x001f0000U, 354 0x1f000000U, 0x001f0000U, 0x1f000000U, 0x001f0000U, 355 0x1f000000U, 0x001f0000U, 0x1f000000U, 0x001f0000U, 356 0x1f000000U, 0x001f0000U, 0x1f000000U, 0x001f0000U, 357 0x1f000000U, 0x001f0000U, 0x1f000000U, 0x001f0000U, 358 0x1f000000U, 0x001f0000U, 0x1f000000U, 0x001f0000U, 359 0x1f000000U, 0x001f0000U, 0x1f000000U, 0x001f0000U, 360 0x1f000000U, 0x001f0000U, 0x1f000000U, 0x001f0000U 361 }; 362 363 /* lower bit position of bitfield imr_tx{t}[4:0] */ 364 static uint32_t itr_imr_txt_shift[32] = { 365 24U, 16U, 24U, 16U, 24U, 16U, 24U, 16U, 366 24U, 16U, 24U, 16U, 24U, 16U, 24U, 16U, 367 24U, 16U, 24U, 16U, 24U, 16U, 24U, 16U, 368 24U, 16U, 24U, 16U, 24U, 16U, 24U, 16U 369 }; 370 371 AQ_WRITE_REG_BIT(aq_hw, itr_imr_txt_adr[tx], itr_imr_txt_msk[tx], 372 itr_imr_txt_shift[tx], irq_map_tx); 373 } 374 375 void 376 itr_irq_msk_clearlsw_set(struct aq_hw *aq_hw, uint32_t irq_msk_clearlsw) 377 { 378 AQ_WRITE_REG(aq_hw, itr_imcrlsw_adr, irq_msk_clearlsw); 379 } 380 381 void 382 itr_irq_msk_setlsw_set(struct aq_hw *aq_hw, uint32_t irq_msk_setlsw) 383 { 384 AQ_WRITE_REG(aq_hw, itr_imsrlsw_adr, irq_msk_setlsw); 385 } 386 387 void 388 itr_irq_reg_res_dis_set(struct aq_hw *aq_hw, uint32_t irq_reg_res_dis) 389 { 390 AQ_WRITE_REG_BIT(aq_hw, itr_reg_res_dsbl_adr, itr_reg_res_dsbl_msk, 391 itr_reg_res_dsbl_shift, irq_reg_res_dis); 392 } 393 394 void 395 itr_irq_status_clearlsw_set(struct aq_hw *aq_hw, uint32_t irq_status_clearlsw) 396 { 397 AQ_WRITE_REG(aq_hw, itr_iscrlsw_adr, irq_status_clearlsw); 398 } 399 400 uint32_t 401 itr_irq_statuslsw_get(struct aq_hw *aq_hw) 402 { 403 return AQ_READ_REG(aq_hw, itr_isrlsw_adr); 404 } 405 406 uint32_t 407 itr_res_irq_get(struct aq_hw *aq_hw) 408 { 409 return AQ_READ_REG_BIT(aq_hw, itr_res_adr, itr_res_msk, itr_res_shift); 410 } 411 412 void 413 itr_res_irq_set(struct aq_hw *aq_hw, uint32_t res_irq) 414 { 415 AQ_WRITE_REG_BIT(aq_hw, itr_res_adr, itr_res_msk, itr_res_shift, 416 res_irq); 417 } 418 419 void 420 itr_link_int_map_en_set(struct aq_hw *aq_hw, uint32_t link_int_en_map_en) 421 { 422 AQ_WRITE_REG_BIT(aq_hw, itrImrLinkEn_ADR, itrImrLinkEn_MSK, 423 itrImrLinkEn_SHIFT, link_int_en_map_en); 424 } 425 426 uint32_t 427 itr_link_int_map_en_get(struct aq_hw *aq_hw) 428 { 429 return AQ_READ_REG_BIT(aq_hw, itrImrLinkEn_ADR, itrImrLinkEn_MSK, 430 itrImrLinkEn_SHIFT); 431 } 432 433 void 434 itr_link_int_map_set(struct aq_hw *aq_hw, uint32_t link_int_map) 435 { 436 AQ_WRITE_REG_BIT(aq_hw, itrImrLink_ADR, itrImrLink_MSK, 437 itrImrLink_SHIFT, link_int_map); 438 } 439 440 uint32_t 441 itr_link_int_map_get(struct aq_hw *aq_hw) 442 { 443 return AQ_READ_REG_BIT(aq_hw, itrImrLink_ADR, itrImrLink_MSK, 444 itrImrLink_SHIFT); 445 } 446 447 void 448 itr_mif_int_map_en_set(struct aq_hw *aq_hw, uint32_t mifInterruptMappingEnable, 449 uint32_t mif) 450 { 451 AQ_WRITE_REG_BIT(aq_hw, itrImrMifMEn_ADR(mif), itrImrMifMEn_MSK(mif), 452 itrImrMifMEn_SHIFT(mif), mifInterruptMappingEnable); 453 } 454 455 uint32_t 456 itr_mif_int_map_en_get(struct aq_hw *aq_hw, uint32_t mif) 457 { 458 return AQ_READ_REG_BIT(aq_hw, itrImrMifMEn_ADR(mif), 459 itrImrMifMEn_MSK(mif), itrImrMifMEn_SHIFT(mif)); 460 } 461 462 void 463 itr_mif_int_map_set(struct aq_hw *aq_hw, uint32_t mifInterruptMapping, 464 uint32_t mif) 465 { 466 AQ_WRITE_REG_BIT(aq_hw, itrImrMifM_ADR(mif), itrImrMifM_MSK(mif), 467 itrImrMifM_SHIFT(mif), mifInterruptMapping); 468 } 469 470 uint32_t 471 itr_mif_int_map_get(struct aq_hw *aq_hw, uint32_t mif) 472 { 473 return AQ_READ_REG_BIT(aq_hw, itrImrMifM_ADR(mif), itrImrMifM_MSK(mif), 474 itrImrMifM_SHIFT(mif)); 475 } 476 477 void 478 itr_irq_mode_set(struct aq_hw *aq_hw, uint32_t irq_mode) 479 { 480 AQ_WRITE_REG_BIT(aq_hw, itrIntMode_ADR, itrIntMode_MSK, 481 itrIntMode_SHIFT, irq_mode); 482 } 483 484 void 485 itr_irq_status_cor_en_set(struct aq_hw *aq_hw, uint32_t irq_status_cor_en) 486 { 487 AQ_WRITE_REG_BIT(aq_hw, itrIsrCorEn_ADR, itrIsrCorEn_MSK, 488 itrIsrCorEn_SHIFT, irq_status_cor_en); 489 } 490 491 void 492 itr_irq_auto_mask_clr_en_set(struct aq_hw *aq_hw, uint32_t irq_auto_mask_clr_en) 493 { 494 AQ_WRITE_REG_BIT(aq_hw, itrIamrClrEn_ADR, itrIamrClrEn_MSK, 495 itrIamrClrEn_SHIFT, irq_auto_mask_clr_en); 496 } 497 498 /* rdm */ 499 void 500 rdm_cpu_id_set(struct aq_hw *aq_hw, uint32_t cpuid, uint32_t dca) 501 { 502 AQ_WRITE_REG_BIT(aq_hw, rdm_dcadcpuid_adr(dca), rdm_dcadcpuid_msk, 503 rdm_dcadcpuid_shift, cpuid); 504 } 505 506 void 507 rdm_rx_dca_en_set(struct aq_hw *aq_hw, uint32_t rx_dca_en) 508 { 509 AQ_WRITE_REG_BIT(aq_hw, rdm_dca_en_adr, rdm_dca_en_msk, 510 rdm_dca_en_shift, rx_dca_en); 511 } 512 513 void 514 rdm_rx_dca_mode_set(struct aq_hw *aq_hw, uint32_t rx_dca_mode) 515 { 516 AQ_WRITE_REG_BIT(aq_hw, rdm_dca_mode_adr, rdm_dca_mode_msk, 517 rdm_dca_mode_shift, rx_dca_mode); 518 } 519 520 void 521 rdm_rx_desc_data_buff_size_set(struct aq_hw *aq_hw, 522 uint32_t rx_desc_data_buff_size, uint32_t descriptor) 523 { 524 AQ_WRITE_REG_BIT(aq_hw, rdm_descddata_size_adr(descriptor), 525 rdm_descddata_size_msk, rdm_descddata_size_shift, 526 rx_desc_data_buff_size); 527 } 528 529 void 530 rdm_rx_desc_dca_en_set(struct aq_hw *aq_hw, uint32_t rx_desc_dca_en, 531 uint32_t dca) 532 { 533 AQ_WRITE_REG_BIT(aq_hw, rdm_dcaddesc_en_adr(dca), rdm_dcaddesc_en_msk, 534 rdm_dcaddesc_en_shift, rx_desc_dca_en); 535 } 536 537 void 538 rdm_rx_desc_en_set(struct aq_hw *aq_hw, uint32_t rx_desc_en, 539 uint32_t descriptor) 540 { 541 AQ_WRITE_REG_BIT(aq_hw, rdm_descden_adr(descriptor), rdm_descden_msk, 542 rdm_descden_shift, rx_desc_en); 543 } 544 545 void 546 rdm_rx_desc_head_buff_size_set(struct aq_hw *aq_hw, 547 uint32_t rx_desc_head_buff_size, uint32_t descriptor) 548 { 549 AQ_WRITE_REG_BIT(aq_hw, rdm_descdhdr_size_adr(descriptor), 550 rdm_descdhdr_size_msk, rdm_descdhdr_size_shift, 551 rx_desc_head_buff_size); 552 } 553 554 void 555 rdm_rx_desc_head_splitting_set(struct aq_hw *aq_hw, 556 uint32_t rx_desc_head_splitting, uint32_t descriptor) 557 { 558 AQ_WRITE_REG_BIT(aq_hw, rdm_descdhdr_split_adr(descriptor), 559 rdm_descdhdr_split_msk, rdm_descdhdr_split_shift, 560 rx_desc_head_splitting); 561 } 562 563 uint32_t 564 rdm_rx_desc_head_ptr_get(struct aq_hw *aq_hw, uint32_t descriptor) 565 { 566 return AQ_READ_REG_BIT(aq_hw, rdm_descdhd_adr(descriptor), 567 rdm_descdhd_msk, rdm_descdhd_shift); 568 } 569 570 void 571 rdm_rx_desc_len_set(struct aq_hw *aq_hw, uint32_t rx_desc_len, 572 uint32_t descriptor) 573 { 574 AQ_WRITE_REG_BIT(aq_hw, rdm_descdlen_adr(descriptor), rdm_descdlen_msk, 575 rdm_descdlen_shift, rx_desc_len); 576 } 577 578 void 579 rdm_rx_desc_res_set(struct aq_hw *aq_hw, uint32_t rx_desc_res, 580 uint32_t descriptor) 581 { 582 AQ_WRITE_REG_BIT(aq_hw, rdm_descdreset_adr(descriptor), 583 rdm_descdreset_msk, rdm_descdreset_shift, rx_desc_res); 584 } 585 586 void 587 rdm_rx_desc_wr_wb_irq_en_set(struct aq_hw *aq_hw, 588 uint32_t rx_desc_wr_wb_irq_en) 589 { 590 AQ_WRITE_REG_BIT(aq_hw, rdm_int_desc_wrb_en_adr, 591 rdm_int_desc_wrb_en_msk, rdm_int_desc_wrb_en_shift, 592 rx_desc_wr_wb_irq_en); 593 } 594 595 void 596 rdm_rx_head_dca_en_set(struct aq_hw *aq_hw, uint32_t rx_head_dca_en, 597 uint32_t dca) 598 { 599 AQ_WRITE_REG_BIT(aq_hw, rdm_dcadhdr_en_adr(dca), rdm_dcadhdr_en_msk, 600 rdm_dcadhdr_en_shift, rx_head_dca_en); 601 } 602 603 void 604 rdm_rx_pld_dca_en_set(struct aq_hw *aq_hw, uint32_t rx_pld_dca_en, uint32_t dca) 605 { 606 AQ_WRITE_REG_BIT(aq_hw, rdm_dcadpay_en_adr(dca), rdm_dcadpay_en_msk, 607 rdm_dcadpay_en_shift, rx_pld_dca_en); 608 } 609 610 void 611 rdm_rdm_intr_moder_en_set(struct aq_hw *aq_hw, uint32_t rdm_intr_moder_en) 612 { 613 AQ_WRITE_REG_BIT(aq_hw, rdm_int_rim_en_adr, rdm_int_rim_en_msk, 614 rdm_int_rim_en_shift, rdm_intr_moder_en); 615 } 616 617 /* reg */ 618 void 619 reg_gen_irq_map_set(struct aq_hw *aq_hw, uint32_t gen_intr_map, uint32_t regidx) 620 { 621 AQ_WRITE_REG(aq_hw, gen_intr_map_adr(regidx), gen_intr_map); 622 } 623 624 uint32_t 625 reg_gen_irq_status_get(struct aq_hw *aq_hw) 626 { 627 return AQ_READ_REG(aq_hw, gen_intr_stat_adr); 628 } 629 630 void 631 reg_irq_glb_ctl_set(struct aq_hw *aq_hw, uint32_t intr_glb_ctl) 632 { 633 AQ_WRITE_REG(aq_hw, intr_glb_ctl_adr, intr_glb_ctl); 634 } 635 636 void 637 reg_irq_thr_set(struct aq_hw *aq_hw, uint32_t intr_thr, uint32_t throttle) 638 { 639 AQ_WRITE_REG(aq_hw, intr_thr_adr(throttle), intr_thr); 640 } 641 642 void 643 reg_rx_dma_desc_base_addresslswset(struct aq_hw *aq_hw, 644 uint32_t rx_dma_desc_base_addrlsw, uint32_t descriptor) 645 { 646 AQ_WRITE_REG(aq_hw, rx_dma_desc_base_addrlsw_adr(descriptor), 647 rx_dma_desc_base_addrlsw); 648 } 649 650 void 651 reg_rx_dma_desc_base_addressmswset(struct aq_hw *aq_hw, 652 uint32_t rx_dma_desc_base_addrmsw, uint32_t descriptor) 653 { 654 AQ_WRITE_REG(aq_hw, rx_dma_desc_base_addrmsw_adr(descriptor), 655 rx_dma_desc_base_addrmsw); 656 } 657 658 uint32_t 659 reg_rx_dma_desc_status_get(struct aq_hw *aq_hw, uint32_t descriptor) 660 { 661 return AQ_READ_REG(aq_hw, rx_dma_desc_stat_adr(descriptor)); 662 } 663 664 void 665 reg_rx_dma_desc_tail_ptr_set(struct aq_hw *aq_hw, 666 uint32_t rx_dma_desc_tail_ptr, uint32_t descriptor) 667 { 668 AQ_WRITE_REG(aq_hw, rx_dma_desc_tail_ptr_adr(descriptor), 669 rx_dma_desc_tail_ptr); 670 } 671 672 uint32_t 673 reg_rx_dma_desc_tail_ptr_get(struct aq_hw *aq_hw, uint32_t descriptor) 674 { 675 return AQ_READ_REG(aq_hw, rx_dma_desc_tail_ptr_adr(descriptor)); 676 } 677 678 void 679 reg_rx_flr_mcst_flr_msk_set(struct aq_hw *aq_hw, uint32_t rx_flr_mcst_flr_msk) 680 { 681 AQ_WRITE_REG(aq_hw, rx_flr_mcst_flr_msk_adr, rx_flr_mcst_flr_msk); 682 } 683 684 void 685 reg_rx_flr_mcst_flr_set(struct aq_hw *aq_hw, uint32_t rx_flr_mcst_flr, 686 uint32_t filter) 687 { 688 AQ_WRITE_REG(aq_hw, rx_flr_mcst_flr_adr(filter), rx_flr_mcst_flr); 689 } 690 691 void 692 reg_rx_flr_rss_control1set(struct aq_hw *aq_hw, uint32_t rx_flr_rss_control1) 693 { 694 AQ_WRITE_REG(aq_hw, rx_flr_rss_control1_adr, rx_flr_rss_control1); 695 } 696 697 void 698 reg_rx_flr_control2_set(struct aq_hw *aq_hw, uint32_t rx_filter_control2) 699 { 700 AQ_WRITE_REG(aq_hw, rx_flr_control2_adr, rx_filter_control2); 701 } 702 703 void 704 reg_rx_intr_moder_ctrl_set(struct aq_hw *aq_hw, 705 uint32_t rx_intr_moderation_ctl, uint32_t queue) 706 { 707 AQ_WRITE_REG(aq_hw, rx_intr_moderation_ctl_adr(queue), 708 rx_intr_moderation_ctl); 709 } 710 711 void 712 reg_tx_dma_debug_ctl_set(struct aq_hw *aq_hw, uint32_t tx_dma_debug_ctl) 713 { 714 AQ_WRITE_REG(aq_hw, tx_dma_debug_ctl_adr, tx_dma_debug_ctl); 715 } 716 717 void 718 reg_tx_dma_desc_base_addresslswset(struct aq_hw *aq_hw, 719 uint32_t tx_dma_desc_base_addrlsw, uint32_t descriptor) 720 { 721 AQ_WRITE_REG(aq_hw, tx_dma_desc_base_addrlsw_adr(descriptor), 722 tx_dma_desc_base_addrlsw); 723 } 724 725 void 726 reg_tx_dma_desc_base_addressmswset(struct aq_hw *aq_hw, 727 uint32_t tx_dma_desc_base_addrmsw, uint32_t descriptor) 728 { 729 AQ_WRITE_REG(aq_hw, tx_dma_desc_base_addrmsw_adr(descriptor), 730 tx_dma_desc_base_addrmsw); 731 } 732 733 void 734 reg_tx_dma_desc_tail_ptr_set(struct aq_hw *aq_hw, 735 uint32_t tx_dma_desc_tail_ptr, uint32_t descriptor) 736 { 737 //wmb(); 738 739 AQ_WRITE_REG(aq_hw, tx_dma_desc_tail_ptr_adr(descriptor), 740 tx_dma_desc_tail_ptr); 741 } 742 743 uint32_t 744 reg_tx_dma_desc_tail_ptr_get(struct aq_hw *aq_hw, uint32_t descriptor) 745 { 746 return AQ_READ_REG(aq_hw, tx_dma_desc_tail_ptr_adr(descriptor)); 747 } 748 749 void 750 reg_tx_intr_moder_ctrl_set(struct aq_hw *aq_hw, 751 uint32_t tx_intr_moderation_ctl, uint32_t queue) 752 { 753 AQ_WRITE_REG(aq_hw, tx_intr_moderation_ctl_adr(queue), 754 tx_intr_moderation_ctl); 755 } 756 757 /* RPB: rx packet buffer */ 758 void 759 rpb_dma_sys_lbk_set(struct aq_hw *aq_hw, uint32_t dma_sys_lbk) 760 { 761 AQ_WRITE_REG_BIT(aq_hw, rpb_dma_sys_lbk_adr, rpb_dma_sys_lbk_msk, 762 rpb_dma_sys_lbk_shift, dma_sys_lbk); 763 } 764 765 void 766 rpb_rpf_rx_traf_class_mode_set(struct aq_hw *aq_hw, 767 uint32_t rx_traf_class_mode) 768 { 769 AQ_WRITE_REG_BIT(aq_hw, rpb_rpf_rx_tc_mode_adr, rpb_rpf_rx_tc_mode_msk, 770 rpb_rpf_rx_tc_mode_shift, rx_traf_class_mode); 771 } 772 773 void 774 rpb_rx_buff_en_set(struct aq_hw *aq_hw, uint32_t rx_buff_en) 775 { 776 AQ_WRITE_REG_BIT(aq_hw, rpb_rx_buf_en_adr, rpb_rx_buf_en_msk, 777 rpb_rx_buf_en_shift, rx_buff_en); 778 } 779 780 void 781 rpb_rx_buff_hi_threshold_per_tc_set(struct aq_hw *aq_hw, 782 uint32_t rx_buff_hi_threshold_per_tc, uint32_t buffer) 783 { 784 AQ_WRITE_REG_BIT(aq_hw, rpb_rxbhi_thresh_adr(buffer), 785 rpb_rxbhi_thresh_msk, rpb_rxbhi_thresh_shift, 786 rx_buff_hi_threshold_per_tc); 787 } 788 789 void 790 rpb_rx_buff_lo_threshold_per_tc_set(struct aq_hw *aq_hw, 791 uint32_t rx_buff_lo_threshold_per_tc, uint32_t buffer) 792 { 793 AQ_WRITE_REG_BIT(aq_hw, rpb_rxblo_thresh_adr(buffer), 794 rpb_rxblo_thresh_msk, rpb_rxblo_thresh_shift, 795 rx_buff_lo_threshold_per_tc); 796 } 797 798 void 799 rpb_rx_flow_ctl_mode_set(struct aq_hw *aq_hw, uint32_t rx_flow_ctl_mode) 800 { 801 AQ_WRITE_REG_BIT(aq_hw, rpb_rx_fc_mode_adr, rpb_rx_fc_mode_msk, 802 rpb_rx_fc_mode_shift, rx_flow_ctl_mode); 803 } 804 805 void 806 rpb_rx_pkt_buff_size_per_tc_set(struct aq_hw *aq_hw, 807 uint32_t rx_pkt_buff_size_per_tc, uint32_t buffer) 808 { 809 AQ_WRITE_REG_BIT(aq_hw, rpb_rxbbuf_size_adr(buffer), 810 rpb_rxbbuf_size_msk, rpb_rxbbuf_size_shift, 811 rx_pkt_buff_size_per_tc); 812 } 813 814 void 815 rpb_rx_xoff_en_per_tc_set(struct aq_hw *aq_hw, uint32_t rx_xoff_en_per_tc, 816 uint32_t buffer) 817 { 818 AQ_WRITE_REG_BIT(aq_hw, rpb_rxbxoff_en_adr(buffer), 819 rpb_rxbxoff_en_msk, rpb_rxbxoff_en_shift, rx_xoff_en_per_tc); 820 } 821 822 /* rpf */ 823 824 void 825 rpfl2broadcast_count_threshold_set(struct aq_hw *aq_hw, 826 uint32_t l2broadcast_count_threshold) 827 { 828 AQ_WRITE_REG_BIT(aq_hw, rpfl2bc_thresh_adr, rpfl2bc_thresh_msk, 829 rpfl2bc_thresh_shift, l2broadcast_count_threshold); 830 } 831 832 void 833 rpfl2broadcast_en_set(struct aq_hw *aq_hw, uint32_t l2broadcast_en) 834 { 835 AQ_WRITE_REG_BIT(aq_hw, rpfl2bc_en_adr, rpfl2bc_en_msk, 836 rpfl2bc_en_shift, l2broadcast_en); 837 } 838 839 void 840 rpfl2broadcast_flr_act_set(struct aq_hw *aq_hw, uint32_t l2broadcast_flr_act) 841 { 842 AQ_WRITE_REG_BIT(aq_hw, rpfl2bc_act_adr, rpfl2bc_act_msk, 843 rpfl2bc_act_shift, l2broadcast_flr_act); 844 } 845 846 void 847 rpfl2multicast_flr_en_set(struct aq_hw *aq_hw, uint32_t l2multicast_flr_en, 848 uint32_t filter) 849 { 850 AQ_WRITE_REG_BIT(aq_hw, rpfl2mc_enf_adr(filter), rpfl2mc_enf_msk, 851 rpfl2mc_enf_shift, l2multicast_flr_en); 852 } 853 854 void 855 rpfl2promiscuous_mode_en_set(struct aq_hw *aq_hw, 856 uint32_t l2promiscuous_mode_en) 857 { 858 AQ_WRITE_REG_BIT(aq_hw, rpfl2promis_mode_adr, rpfl2promis_mode_msk, 859 rpfl2promis_mode_shift, l2promiscuous_mode_en); 860 } 861 862 void 863 rpfl2unicast_flr_act_set(struct aq_hw *aq_hw, uint32_t l2unicast_flr_act, 864 uint32_t filter) 865 { 866 AQ_WRITE_REG_BIT(aq_hw, rpfl2uc_actf_adr(filter), rpfl2uc_actf_msk, 867 rpfl2uc_actf_shift, l2unicast_flr_act); 868 } 869 870 void 871 rpfl2_uc_flr_en_set(struct aq_hw *aq_hw, uint32_t l2unicast_flr_en, 872 uint32_t filter) 873 { 874 AQ_WRITE_REG_BIT(aq_hw, rpfl2uc_enf_adr(filter), rpfl2uc_enf_msk, 875 rpfl2uc_enf_shift, l2unicast_flr_en); 876 } 877 878 void 879 rpfl2unicast_dest_addresslsw_set(struct aq_hw *aq_hw, 880 uint32_t l2unicast_dest_addresslsw, uint32_t filter) 881 { 882 AQ_WRITE_REG(aq_hw, rpfl2uc_daflsw_adr(filter), 883 l2unicast_dest_addresslsw); 884 } 885 886 void 887 rpfl2unicast_dest_addressmsw_set(struct aq_hw *aq_hw, 888 uint32_t l2unicast_dest_addressmsw, uint32_t filter) 889 { 890 AQ_WRITE_REG_BIT(aq_hw, rpfl2uc_dafmsw_adr(filter), rpfl2uc_dafmsw_msk, 891 rpfl2uc_dafmsw_shift, l2unicast_dest_addressmsw); 892 } 893 894 void 895 rpfl2_accept_all_mc_packets_set(struct aq_hw *aq_hw, 896 uint32_t l2_accept_all_mc_packets) 897 { 898 AQ_WRITE_REG_BIT(aq_hw, rpfl2mc_accept_all_adr, rpfl2mc_accept_all_msk, 899 rpfl2mc_accept_all_shift, l2_accept_all_mc_packets); 900 } 901 902 void 903 rpf_rpb_user_priority_tc_map_set(struct aq_hw *aq_hw, 904 uint32_t user_priority_tc_map, uint32_t tc) 905 { 906 /* register address for bitfield rx_tc_up{t}[2:0] */ 907 static uint32_t rpf_rpb_rx_tc_upt_adr[8] = { 908 0x000054c4U, 0x000054c4U, 0x000054c4U, 0x000054c4U, 909 0x000054c4U, 0x000054c4U, 0x000054c4U, 0x000054c4U 910 }; 911 912 /* bitmask for bitfield rx_tc_up{t}[2:0] */ 913 static uint32_t rpf_rpb_rx_tc_upt_msk[8] = { 914 0x00000007U, 0x00000070U, 0x00000700U, 0x00007000U, 915 0x00070000U, 0x00700000U, 0x07000000U, 0x70000000U 916 }; 917 918 /* lower bit position of bitfield rx_tc_up{t}[2:0] */ 919 static uint32_t rpf_rpb_rx_tc_upt_shft[8] = { 920 0U, 4U, 8U, 12U, 16U, 20U, 24U, 28U 921 }; 922 923 AQ_WRITE_REG_BIT(aq_hw, rpf_rpb_rx_tc_upt_adr[tc], 924 rpf_rpb_rx_tc_upt_msk[tc], rpf_rpb_rx_tc_upt_shft[tc], 925 user_priority_tc_map); 926 } 927 928 void 929 rpf_rss_key_addr_set(struct aq_hw *aq_hw, uint32_t rss_key_addr) 930 { 931 AQ_WRITE_REG_BIT(aq_hw, rpf_rss_key_addr_adr, rpf_rss_key_addr_msk, 932 rpf_rss_key_addr_shift, rss_key_addr); 933 } 934 935 void 936 rpf_rss_key_wr_data_set(struct aq_hw *aq_hw, uint32_t rss_key_wr_data) 937 { 938 AQ_WRITE_REG(aq_hw, rpf_rss_key_wr_data_adr, rss_key_wr_data); 939 } 940 941 uint32_t 942 rpf_rss_key_rd_data_get(struct aq_hw *aq_hw) 943 { 944 return AQ_READ_REG(aq_hw, rpf_rss_key_rd_data_adr); 945 } 946 947 uint32_t 948 rpf_rss_key_wr_en_get(struct aq_hw *aq_hw) 949 { 950 return AQ_READ_REG_BIT(aq_hw, rpf_rss_key_wr_eni_adr, 951 rpf_rss_key_wr_eni_msk, rpf_rss_key_wr_eni_shift); 952 } 953 954 void 955 rpf_rss_key_wr_en_set(struct aq_hw *aq_hw, uint32_t rss_key_wr_en) 956 { 957 AQ_WRITE_REG_BIT(aq_hw, rpf_rss_key_wr_eni_adr, 958 rpf_rss_key_wr_eni_msk, rpf_rss_key_wr_eni_shift, 959 rss_key_wr_en); 960 } 961 962 void 963 rpf_rss_redir_tbl_addr_set(struct aq_hw *aq_hw, uint32_t rss_redir_tbl_addr) 964 { 965 AQ_WRITE_REG_BIT(aq_hw, rpf_rss_redir_addr_adr, rpf_rss_redir_addr_msk, 966 rpf_rss_redir_addr_shift, rss_redir_tbl_addr); 967 } 968 969 void 970 rpf_rss_redir_tbl_wr_data_set(struct aq_hw *aq_hw, 971 uint32_t rss_redir_tbl_wr_data) 972 { 973 AQ_WRITE_REG_BIT(aq_hw, rpf_rss_redir_wr_data_adr, 974 rpf_rss_redir_wr_data_msk, rpf_rss_redir_wr_data_shift, 975 rss_redir_tbl_wr_data); 976 } 977 978 uint32_t 979 rpf_rss_redir_wr_en_get(struct aq_hw *aq_hw) 980 { 981 return AQ_READ_REG_BIT(aq_hw, rpf_rss_redir_wr_eni_adr, 982 rpf_rss_redir_wr_eni_msk, rpf_rss_redir_wr_eni_shift); 983 } 984 985 void 986 rpf_rss_redir_wr_en_set(struct aq_hw *aq_hw, uint32_t rss_redir_wr_en) 987 { 988 AQ_WRITE_REG_BIT(aq_hw, rpf_rss_redir_wr_eni_adr, 989 rpf_rss_redir_wr_eni_msk, rpf_rss_redir_wr_eni_shift, 990 rss_redir_wr_en); 991 } 992 993 void 994 rpf_tpo_to_rpf_sys_lbk_set(struct aq_hw *aq_hw, uint32_t tpo_to_rpf_sys_lbk) 995 { 996 AQ_WRITE_REG_BIT(aq_hw, rpf_tpo_rpf_sys_lbk_adr, 997 rpf_tpo_rpf_sys_lbk_msk, rpf_tpo_rpf_sys_lbk_shift, 998 tpo_to_rpf_sys_lbk); 999 } 1000 1001 1002 void 1003 hw_atl_rpf_vlan_inner_etht_set(struct aq_hw_s *aq_hw, uint32_t vlan_inner_etht) 1004 { 1005 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_INNER_TPID_ADR, 1006 HW_ATL_RPF_VL_INNER_TPID_MSK, 1007 HW_ATL_RPF_VL_INNER_TPID_SHIFT, 1008 vlan_inner_etht); 1009 } 1010 1011 void 1012 hw_atl_rpf_vlan_outer_etht_set(struct aq_hw_s *aq_hw, uint32_t vlan_outer_etht) 1013 { 1014 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_OUTER_TPID_ADR, 1015 HW_ATL_RPF_VL_OUTER_TPID_MSK, 1016 HW_ATL_RPF_VL_OUTER_TPID_SHIFT, 1017 vlan_outer_etht); 1018 } 1019 1020 void 1021 hw_atl_rpf_vlan_prom_mode_en_set(struct aq_hw_s *aq_hw, 1022 uint32_t vlan_prom_mode_en) 1023 { 1024 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_PROMIS_MODE_ADR, 1025 HW_ATL_RPF_VL_PROMIS_MODE_MSK, 1026 HW_ATL_RPF_VL_PROMIS_MODE_SHIFT, 1027 vlan_prom_mode_en); 1028 } 1029 1030 void 1031 hw_atl_rpf_vlan_accept_untagged_packets_set(struct aq_hw_s *aq_hw, 1032 uint32_t vlan_acc_untagged_packets) 1033 { 1034 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_ADR, 1035 HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_MSK, 1036 HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_SHIFT, 1037 vlan_acc_untagged_packets); 1038 } 1039 1040 void 1041 hw_atl_rpf_vlan_untagged_act_set(struct aq_hw_s *aq_hw, 1042 uint32_t vlan_untagged_act) 1043 { 1044 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_UNTAGGED_ACT_ADR, 1045 HW_ATL_RPF_VL_UNTAGGED_ACT_MSK, 1046 HW_ATL_RPF_VL_UNTAGGED_ACT_SHIFT, 1047 vlan_untagged_act); 1048 } 1049 1050 void 1051 hw_atl_rpf_vlan_flr_en_set(struct aq_hw_s *aq_hw, uint32_t vlan_flr_en, 1052 uint32_t filter) 1053 { 1054 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_EN_F_ADR(filter), 1055 HW_ATL_RPF_VL_EN_F_MSK, 1056 HW_ATL_RPF_VL_EN_F_SHIFT, 1057 vlan_flr_en); 1058 } 1059 1060 void 1061 hw_atl_rpf_vlan_flr_act_set(struct aq_hw_s *aq_hw, uint32_t vlan_flr_act, 1062 uint32_t filter) 1063 { 1064 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_ACT_F_ADR(filter), 1065 HW_ATL_RPF_VL_ACT_F_MSK, 1066 HW_ATL_RPF_VL_ACT_F_SHIFT, 1067 vlan_flr_act); 1068 } 1069 1070 void 1071 hw_atl_rpf_vlan_id_flr_set(struct aq_hw_s *aq_hw, uint32_t vlan_id_flr, 1072 uint32_t filter) 1073 { 1074 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_ID_F_ADR(filter), 1075 HW_ATL_RPF_VL_ID_F_MSK, 1076 HW_ATL_RPF_VL_ID_F_SHIFT, 1077 vlan_id_flr); 1078 } 1079 1080 void 1081 hw_atl_rpf_vlan_rxq_en_flr_set(struct aq_hw_s *aq_hw, uint32_t vlan_rxq_en, 1082 uint32_t filter) 1083 { 1084 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_RXQ_EN_F_ADR(filter), 1085 HW_ATL_RPF_VL_RXQ_EN_F_MSK, 1086 HW_ATL_RPF_VL_RXQ_EN_F_SHIFT, 1087 vlan_rxq_en); 1088 } 1089 1090 void 1091 hw_atl_rpf_vlan_rxq_flr_set(struct aq_hw_s *aq_hw, uint32_t vlan_rxq, 1092 uint32_t filter) 1093 { 1094 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_RXQ_F_ADR(filter), 1095 HW_ATL_RPF_VL_RXQ_F_MSK, 1096 HW_ATL_RPF_VL_RXQ_F_SHIFT, 1097 vlan_rxq); 1098 }; 1099 1100 void 1101 hw_atl_rpf_etht_flr_en_set(struct aq_hw_s *aq_hw, uint32_t etht_flr_en, 1102 uint32_t filter) 1103 { 1104 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_ENF_ADR(filter), 1105 HW_ATL_RPF_ET_ENF_MSK, 1106 HW_ATL_RPF_ET_ENF_SHIFT, etht_flr_en); 1107 } 1108 1109 void 1110 hw_atl_rpf_etht_user_priority_en_set(struct aq_hw_s *aq_hw, 1111 uint32_t etht_user_priority_en, uint32_t filter) 1112 { 1113 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_UPFEN_ADR(filter), 1114 HW_ATL_RPF_ET_UPFEN_MSK, HW_ATL_RPF_ET_UPFEN_SHIFT, 1115 etht_user_priority_en); 1116 } 1117 1118 void 1119 hw_atl_rpf_etht_rx_queue_en_set(struct aq_hw_s *aq_hw, 1120 uint32_t etht_rx_queue_en, uint32_t filter) 1121 { 1122 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_RXQFEN_ADR(filter), 1123 HW_ATL_RPF_ET_RXQFEN_MSK, 1124 HW_ATL_RPF_ET_RXQFEN_SHIFT, 1125 etht_rx_queue_en); 1126 } 1127 1128 void 1129 hw_atl_rpf_etht_user_priority_set(struct aq_hw_s *aq_hw, 1130 uint32_t etht_user_priority, uint32_t filter) 1131 { 1132 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_UPF_ADR(filter), 1133 HW_ATL_RPF_ET_UPF_MSK, 1134 HW_ATL_RPF_ET_UPF_SHIFT, etht_user_priority); 1135 } 1136 1137 void 1138 hw_atl_rpf_etht_rx_queue_set(struct aq_hw_s *aq_hw, uint32_t etht_rx_queue, 1139 uint32_t filter) 1140 { 1141 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_RXQF_ADR(filter), 1142 HW_ATL_RPF_ET_RXQF_MSK, 1143 HW_ATL_RPF_ET_RXQF_SHIFT, etht_rx_queue); 1144 } 1145 1146 void 1147 hw_atl_rpf_etht_mgt_queue_set(struct aq_hw_s *aq_hw, uint32_t etht_mgt_queue, 1148 uint32_t filter) 1149 { 1150 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_MNG_RXQF_ADR(filter), 1151 HW_ATL_RPF_ET_MNG_RXQF_MSK, 1152 HW_ATL_RPF_ET_MNG_RXQF_SHIFT, 1153 etht_mgt_queue); 1154 } 1155 1156 void 1157 hw_atl_rpf_etht_flr_act_set(struct aq_hw_s *aq_hw, uint32_t etht_flr_act, 1158 uint32_t filter) 1159 { 1160 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_ACTF_ADR(filter), 1161 HW_ATL_RPF_ET_ACTF_MSK, 1162 HW_ATL_RPF_ET_ACTF_SHIFT, etht_flr_act); 1163 } 1164 1165 void 1166 hw_atl_rpf_etht_flr_set(struct aq_hw_s *aq_hw, uint32_t etht_flr, 1167 uint32_t filter) 1168 { 1169 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_VALF_ADR(filter), 1170 HW_ATL_RPF_ET_VALF_MSK, 1171 HW_ATL_RPF_ET_VALF_SHIFT, etht_flr); 1172 } 1173 1174 void 1175 hw_atl_rpf_l3_l4_enf_set(struct aq_hw_s *aq_hw, uint32_t val, uint32_t filter) 1176 { 1177 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_L3_L4_ENF_ADR(filter), 1178 HW_ATL_RPF_L3_L4_ENF_MSK, 1179 HW_ATL_RPF_L3_L4_ENF_SHIFT, val); 1180 } 1181 1182 void 1183 hw_atl_rpf_l3_v6_enf_set(struct aq_hw_s *aq_hw, uint32_t val, uint32_t filter) 1184 { 1185 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_L3_V6_ENF_ADR(filter), 1186 HW_ATL_RPF_L3_V6_ENF_MSK, 1187 HW_ATL_RPF_L3_V6_ENF_SHIFT, val); 1188 } 1189 1190 void 1191 hw_atl_rpf_l3_saf_en_set(struct aq_hw_s *aq_hw, uint32_t val, uint32_t filter) 1192 { 1193 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_L3_SAF_EN_ADR(filter), 1194 HW_ATL_RPF_L3_SAF_EN_MSK, 1195 HW_ATL_RPF_L3_SAF_EN_SHIFT, val); 1196 } 1197 1198 void 1199 hw_atl_rpf_l3_daf_en_set(struct aq_hw_s *aq_hw, uint32_t val, uint32_t filter) 1200 { 1201 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_L3_DAF_EN_ADR(filter), 1202 HW_ATL_RPF_L3_DAF_EN_MSK, 1203 HW_ATL_RPF_L3_DAF_EN_SHIFT, val); 1204 } 1205 1206 void 1207 hw_atl_rpf_l4_spf_en_set(struct aq_hw_s *aq_hw, uint32_t val, uint32_t filter) 1208 { 1209 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_L4_SPF_EN_ADR(filter), 1210 HW_ATL_RPF_L4_SPF_EN_MSK, 1211 HW_ATL_RPF_L4_SPF_EN_SHIFT, val); 1212 } 1213 1214 void 1215 hw_atl_rpf_l4_dpf_en_set(struct aq_hw_s *aq_hw, uint32_t val, uint32_t filter) 1216 { 1217 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_L4_DPF_EN_ADR(filter), 1218 HW_ATL_RPF_L4_DPF_EN_MSK, 1219 HW_ATL_RPF_L4_DPF_EN_SHIFT, val); 1220 } 1221 1222 void 1223 hw_atl_rpf_l4_protf_en_set(struct aq_hw_s *aq_hw, uint32_t val, uint32_t filter) 1224 { 1225 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_L4_PROTF_EN_ADR(filter), 1226 HW_ATL_RPF_L4_PROTF_EN_MSK, 1227 HW_ATL_RPF_L4_PROTF_EN_SHIFT, val); 1228 } 1229 1230 void 1231 hw_atl_rpf_l3_arpf_en_set(struct aq_hw_s *aq_hw, uint32_t val, uint32_t filter) 1232 { 1233 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_L3_ARPF_EN_ADR(filter), 1234 HW_ATL_RPF_L3_ARPF_EN_MSK, 1235 HW_ATL_RPF_L3_ARPF_EN_SHIFT, val); 1236 } 1237 1238 void 1239 hw_atl_rpf_l3_l4_rxqf_en_set(struct aq_hw_s *aq_hw, uint32_t val, 1240 uint32_t filter) 1241 { 1242 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_L3_L4_RXQF_EN_ADR(filter), 1243 HW_ATL_RPF_L3_L4_RXQF_EN_MSK, 1244 HW_ATL_RPF_L3_L4_RXQF_EN_SHIFT, val); 1245 } 1246 1247 void 1248 hw_atl_rpf_l3_l4_mng_rxqf_set(struct aq_hw_s *aq_hw, uint32_t val, 1249 uint32_t filter) 1250 { 1251 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_L3_L4_MNG_RXQF_ADR(filter), 1252 HW_ATL_RPF_L3_L4_MNG_RXQF_MSK, 1253 HW_ATL_RPF_L3_L4_MNG_RXQF_SHIFT, val); 1254 } 1255 1256 void 1257 hw_atl_rpf_l3_l4_actf_set(struct aq_hw_s *aq_hw, uint32_t val, uint32_t filter) 1258 { 1259 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_L3_L4_ACTF_ADR(filter), 1260 HW_ATL_RPF_L3_L4_ACTF_MSK, 1261 HW_ATL_RPF_L3_L4_ACTF_SHIFT, val); 1262 } 1263 1264 void 1265 hw_atl_rpf_l3_l4_rxqf_set(struct aq_hw_s *aq_hw, uint32_t val, uint32_t filter) 1266 { 1267 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_L3_L4_RXQF_ADR(filter), 1268 HW_ATL_RPF_L3_L4_RXQF_MSK, 1269 HW_ATL_RPF_L3_L4_RXQF_SHIFT, val); 1270 } 1271 1272 void 1273 hw_atl_rpf_l4_protf_set(struct aq_hw_s *aq_hw, uint32_t val, uint32_t filter) 1274 { 1275 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_L4_PROTF_ADR(filter), 1276 HW_ATL_RPF_L4_PROTF_MSK, 1277 HW_ATL_RPF_L4_PROTF_SHIFT, val); 1278 } 1279 1280 void 1281 hw_atl_rpf_l4_spd_set(struct aq_hw_s *aq_hw, uint32_t val, uint32_t filter) 1282 { 1283 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_L4_SPD_ADR(filter), 1284 HW_ATL_RPF_L4_SPD_MSK, 1285 HW_ATL_RPF_L4_SPD_SHIFT, val); 1286 } 1287 1288 void 1289 hw_atl_rpf_l4_dpd_set(struct aq_hw_s *aq_hw, uint32_t val, uint32_t filter) 1290 { 1291 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_L4_DPD_ADR(filter), 1292 HW_ATL_RPF_L4_DPD_MSK, 1293 HW_ATL_RPF_L4_DPD_SHIFT, val); 1294 } 1295 1296 void 1297 rpf_vlan_inner_etht_set(struct aq_hw *aq_hw, uint32_t vlan_inner_etht) 1298 { 1299 AQ_WRITE_REG_BIT(aq_hw, rpf_vl_inner_tpid_adr, rpf_vl_inner_tpid_msk, 1300 rpf_vl_inner_tpid_shift, vlan_inner_etht); 1301 } 1302 1303 void 1304 rpf_vlan_outer_etht_set(struct aq_hw *aq_hw, uint32_t vlan_outer_etht) 1305 { 1306 AQ_WRITE_REG_BIT(aq_hw, rpf_vl_outer_tpid_adr, rpf_vl_outer_tpid_msk, 1307 rpf_vl_outer_tpid_shift, vlan_outer_etht); 1308 } 1309 1310 void 1311 rpf_vlan_prom_mode_en_set(struct aq_hw *aq_hw, uint32_t vlan_prom_mode_en) 1312 { 1313 AQ_WRITE_REG_BIT(aq_hw, rpf_vl_promis_mode_adr, rpf_vl_promis_mode_msk, 1314 rpf_vl_promis_mode_shift, vlan_prom_mode_en); 1315 } 1316 1317 void 1318 rpf_vlan_accept_untagged_packets_set(struct aq_hw *aq_hw, 1319 uint32_t vlan_accept_untagged_packets) 1320 { 1321 AQ_WRITE_REG_BIT(aq_hw, rpf_vl_accept_untagged_mode_adr, 1322 rpf_vl_accept_untagged_mode_msk, rpf_vl_accept_untagged_mode_shift, 1323 vlan_accept_untagged_packets); 1324 } 1325 1326 void 1327 rpf_vlan_untagged_act_set(struct aq_hw *aq_hw, uint32_t vlan_untagged_act) 1328 { 1329 AQ_WRITE_REG_BIT(aq_hw, rpf_vl_untagged_act_adr, 1330 rpf_vl_untagged_act_msk, rpf_vl_untagged_act_shift, 1331 vlan_untagged_act); 1332 } 1333 1334 void 1335 rpf_vlan_flr_en_set(struct aq_hw *aq_hw, uint32_t vlan_flr_en, uint32_t filter) 1336 { 1337 AQ_WRITE_REG_BIT(aq_hw, rpf_vl_en_f_adr(filter), rpf_vl_en_f_msk, 1338 rpf_vl_en_f_shift, vlan_flr_en); 1339 } 1340 1341 void 1342 rpf_vlan_flr_act_set(struct aq_hw *aq_hw, uint32_t vlan_flr_act, 1343 uint32_t filter) 1344 { 1345 AQ_WRITE_REG_BIT(aq_hw, rpf_vl_act_f_adr(filter), rpf_vl_act_f_msk, 1346 rpf_vl_act_f_shift, vlan_flr_act); 1347 } 1348 1349 void 1350 rpf_vlan_id_flr_set(struct aq_hw *aq_hw, uint32_t vlan_id_flr, uint32_t filter) 1351 { 1352 AQ_WRITE_REG_BIT(aq_hw, rpf_vl_id_f_adr(filter), rpf_vl_id_f_msk, 1353 rpf_vl_id_f_shift, vlan_id_flr); 1354 } 1355 1356 void 1357 rpf_etht_flr_en_set(struct aq_hw *aq_hw, uint32_t etht_flr_en, uint32_t filter) 1358 { 1359 AQ_WRITE_REG_BIT(aq_hw, rpf_et_enf_adr(filter), rpf_et_enf_msk, 1360 rpf_et_enf_shift, etht_flr_en); 1361 } 1362 1363 void 1364 rpf_etht_user_priority_en_set(struct aq_hw *aq_hw, 1365 uint32_t etht_user_priority_en, uint32_t filter) 1366 { 1367 AQ_WRITE_REG_BIT(aq_hw, rpf_et_upfen_adr(filter), rpf_et_upfen_msk, 1368 rpf_et_upfen_shift, etht_user_priority_en); 1369 } 1370 1371 void 1372 rpf_etht_rx_queue_en_set(struct aq_hw *aq_hw, uint32_t etht_rx_queue_en, 1373 uint32_t filter) 1374 { 1375 AQ_WRITE_REG_BIT(aq_hw, rpf_et_rxqfen_adr(filter), rpf_et_rxqfen_msk, 1376 rpf_et_rxqfen_shift, etht_rx_queue_en); 1377 } 1378 1379 void 1380 rpf_etht_user_priority_set(struct aq_hw *aq_hw, uint32_t etht_user_priority, 1381 uint32_t filter) 1382 { 1383 AQ_WRITE_REG_BIT(aq_hw, rpf_et_upf_adr(filter), rpf_et_upf_msk, 1384 rpf_et_upf_shift, etht_user_priority); 1385 } 1386 1387 void 1388 rpf_etht_rx_queue_set(struct aq_hw *aq_hw, uint32_t etht_rx_queue, 1389 uint32_t filter) 1390 { 1391 AQ_WRITE_REG_BIT(aq_hw, rpf_et_rxqf_adr(filter), rpf_et_rxqf_msk, 1392 rpf_et_rxqf_shift, etht_rx_queue); 1393 } 1394 1395 void 1396 rpf_etht_mgt_queue_set(struct aq_hw *aq_hw, uint32_t etht_mgt_queue, 1397 uint32_t filter) 1398 { 1399 AQ_WRITE_REG_BIT(aq_hw, rpf_et_mng_rxqf_adr(filter), 1400 rpf_et_mng_rxqf_msk, rpf_et_mng_rxqf_shift, etht_mgt_queue); 1401 } 1402 1403 void 1404 rpf_etht_flr_act_set(struct aq_hw *aq_hw, uint32_t etht_flr_act, 1405 uint32_t filter) 1406 { 1407 AQ_WRITE_REG_BIT(aq_hw, rpf_et_actf_adr(filter), rpf_et_actf_msk, 1408 rpf_et_actf_shift, etht_flr_act); 1409 } 1410 1411 void 1412 rpf_etht_flr_set(struct aq_hw *aq_hw, uint32_t etht_flr, uint32_t filter) 1413 { 1414 AQ_WRITE_REG_BIT(aq_hw, rpf_et_valf_adr(filter), rpf_et_valf_msk, 1415 rpf_et_valf_shift, etht_flr); 1416 } 1417 1418 /* RPO: rx packet offload */ 1419 void 1420 rpo_ipv4header_crc_offload_en_set(struct aq_hw *aq_hw, 1421 uint32_t ipv4header_crc_offload_en) 1422 { 1423 AQ_WRITE_REG_BIT(aq_hw, rpo_ipv4chk_en_adr, rpo_ipv4chk_en_msk, 1424 rpo_ipv4chk_en_shift, ipv4header_crc_offload_en); 1425 } 1426 1427 void 1428 rpo_rx_desc_vlan_stripping_set(struct aq_hw *aq_hw, 1429 uint32_t rx_desc_vlan_stripping, uint32_t descriptor) 1430 { 1431 AQ_WRITE_REG_BIT(aq_hw, rpo_descdvl_strip_adr(descriptor), 1432 rpo_descdvl_strip_msk, rpo_descdvl_strip_shift, 1433 rx_desc_vlan_stripping); 1434 } 1435 1436 void 1437 rpo_tcp_udp_crc_offload_en_set(struct aq_hw *aq_hw, 1438 uint32_t tcp_udp_crc_offload_en) 1439 { 1440 AQ_WRITE_REG_BIT(aq_hw, rpol4chk_en_adr, rpol4chk_en_msk, 1441 rpol4chk_en_shift, tcp_udp_crc_offload_en); 1442 } 1443 1444 void 1445 rpo_lro_en_set(struct aq_hw *aq_hw, uint32_t lro_en) 1446 { 1447 AQ_WRITE_REG(aq_hw, rpo_lro_en_adr, lro_en); 1448 } 1449 1450 void 1451 rpo_lro_patch_optimization_en_set(struct aq_hw *aq_hw, 1452 uint32_t lro_patch_optimization_en) 1453 { 1454 AQ_WRITE_REG_BIT(aq_hw, rpo_lro_ptopt_en_adr, rpo_lro_ptopt_en_msk, 1455 rpo_lro_ptopt_en_shift, lro_patch_optimization_en); 1456 } 1457 1458 void 1459 rpo_lro_qsessions_lim_set(struct aq_hw *aq_hw, uint32_t lro_qsessions_lim) 1460 { 1461 AQ_WRITE_REG_BIT(aq_hw, rpo_lro_qses_lmt_adr, rpo_lro_qses_lmt_msk, 1462 rpo_lro_qses_lmt_shift, lro_qsessions_lim); 1463 } 1464 1465 void 1466 rpo_lro_total_desc_lim_set(struct aq_hw *aq_hw, uint32_t lro_total_desc_lim) 1467 { 1468 AQ_WRITE_REG_BIT(aq_hw, rpo_lro_tot_dsc_lmt_adr, 1469 rpo_lro_tot_dsc_lmt_msk, rpo_lro_tot_dsc_lmt_shift, 1470 lro_total_desc_lim); 1471 } 1472 1473 void 1474 rpo_lro_min_pay_of_first_pkt_set(struct aq_hw *aq_hw, 1475 uint32_t lro_min_pld_of_first_pkt) 1476 { 1477 AQ_WRITE_REG_BIT(aq_hw, rpo_lro_pkt_min_adr, rpo_lro_pkt_min_msk, 1478 rpo_lro_pkt_min_shift, lro_min_pld_of_first_pkt); 1479 } 1480 1481 void 1482 rpo_lro_pkt_lim_set(struct aq_hw *aq_hw, uint32_t lro_pkt_lim) 1483 { 1484 AQ_WRITE_REG(aq_hw, rpo_lro_rsc_max_adr, lro_pkt_lim); 1485 } 1486 1487 void 1488 rpo_lro_max_num_of_descriptors_set(struct aq_hw *aq_hw, 1489 uint32_t lro_max_number_of_descriptors, uint32_t lro) 1490 { 1491 /* Register address for bitfield lro{L}_des_max[1:0] */ 1492 static uint32_t rpo_lro_ldes_max_adr[32] = { 1493 0x000055A0U, 0x000055A0U, 0x000055A0U, 0x000055A0U, 1494 0x000055A0U, 0x000055A0U, 0x000055A0U, 0x000055A0U, 1495 0x000055A4U, 0x000055A4U, 0x000055A4U, 0x000055A4U, 1496 0x000055A4U, 0x000055A4U, 0x000055A4U, 0x000055A4U, 1497 0x000055A8U, 0x000055A8U, 0x000055A8U, 0x000055A8U, 1498 0x000055A8U, 0x000055A8U, 0x000055A8U, 0x000055A8U, 1499 0x000055ACU, 0x000055ACU, 0x000055ACU, 0x000055ACU, 1500 0x000055ACU, 0x000055ACU, 0x000055ACU, 0x000055ACU 1501 }; 1502 1503 /* Bitmask for bitfield lro{L}_des_max[1:0] */ 1504 static uint32_t rpo_lro_ldes_max_msk[32] = { 1505 0x00000003U, 0x00000030U, 0x00000300U, 0x00003000U, 1506 0x00030000U, 0x00300000U, 0x03000000U, 0x30000000U, 1507 0x00000003U, 0x00000030U, 0x00000300U, 0x00003000U, 1508 0x00030000U, 0x00300000U, 0x03000000U, 0x30000000U, 1509 0x00000003U, 0x00000030U, 0x00000300U, 0x00003000U, 1510 0x00030000U, 0x00300000U, 0x03000000U, 0x30000000U, 1511 0x00000003U, 0x00000030U, 0x00000300U, 0x00003000U, 1512 0x00030000U, 0x00300000U, 0x03000000U, 0x30000000U 1513 }; 1514 1515 /* Lower bit position of bitfield lro{L}_des_max[1:0] */ 1516 static uint32_t rpo_lro_ldes_max_shift[32] = { 1517 0U, 4U, 8U, 12U, 16U, 20U, 24U, 28U, 1518 0U, 4U, 8U, 12U, 16U, 20U, 24U, 28U, 1519 0U, 4U, 8U, 12U, 16U, 20U, 24U, 28U, 1520 0U, 4U, 8U, 12U, 16U, 20U, 24U, 28U 1521 }; 1522 1523 AQ_WRITE_REG_BIT(aq_hw, rpo_lro_ldes_max_adr[lro], 1524 rpo_lro_ldes_max_msk[lro], rpo_lro_ldes_max_shift[lro], 1525 lro_max_number_of_descriptors); 1526 } 1527 1528 void 1529 rpo_lro_time_base_divider_set(struct aq_hw *aq_hw, 1530 uint32_t lro_time_base_divider) 1531 { 1532 AQ_WRITE_REG_BIT(aq_hw, rpo_lro_tb_div_adr, rpo_lro_tb_div_msk, 1533 rpo_lro_tb_div_shift, lro_time_base_divider); 1534 } 1535 1536 void 1537 rpo_lro_inactive_interval_set(struct aq_hw *aq_hw, 1538 uint32_t lro_inactive_interval) 1539 { 1540 AQ_WRITE_REG_BIT(aq_hw, rpo_lro_ina_ival_adr, rpo_lro_ina_ival_msk, 1541 rpo_lro_ina_ival_shift, lro_inactive_interval); 1542 } 1543 1544 void 1545 rpo_lro_max_coalescing_interval_set(struct aq_hw *aq_hw, 1546 uint32_t lro_max_coalescing_interval) 1547 { 1548 AQ_WRITE_REG_BIT(aq_hw, rpo_lro_max_ival_adr, rpo_lro_max_ival_msk, 1549 rpo_lro_max_ival_shift, lro_max_coalescing_interval); 1550 } 1551 1552 /* rx */ 1553 void 1554 rx_rx_reg_res_dis_set(struct aq_hw *aq_hw, uint32_t rx_reg_res_dis) 1555 { 1556 AQ_WRITE_REG_BIT(aq_hw, rx_reg_res_dsbl_adr, rx_reg_res_dsbl_msk, 1557 rx_reg_res_dsbl_shift, rx_reg_res_dis); 1558 } 1559 1560 /* tdm */ 1561 void 1562 tdm_cpu_id_set(struct aq_hw *aq_hw, uint32_t cpuid, uint32_t dca) 1563 { 1564 AQ_WRITE_REG_BIT(aq_hw, tdm_dcadcpuid_adr(dca), tdm_dcadcpuid_msk, 1565 tdm_dcadcpuid_shift, cpuid); 1566 } 1567 1568 void 1569 tdm_large_send_offload_en_set(struct aq_hw *aq_hw, 1570 uint32_t large_send_offload_en) 1571 { 1572 AQ_WRITE_REG(aq_hw, tdm_lso_en_adr, large_send_offload_en); 1573 } 1574 1575 void 1576 tdm_tx_dca_en_set(struct aq_hw *aq_hw, uint32_t tx_dca_en) 1577 { 1578 AQ_WRITE_REG_BIT(aq_hw, tdm_dca_en_adr, tdm_dca_en_msk, 1579 tdm_dca_en_shift, tx_dca_en); 1580 } 1581 1582 void 1583 tdm_tx_dca_mode_set(struct aq_hw *aq_hw, uint32_t tx_dca_mode) 1584 { 1585 AQ_WRITE_REG_BIT(aq_hw, tdm_dca_mode_adr, tdm_dca_mode_msk, 1586 tdm_dca_mode_shift, tx_dca_mode); 1587 } 1588 1589 void 1590 tdm_tx_desc_dca_en_set(struct aq_hw *aq_hw, uint32_t tx_desc_dca_en, 1591 uint32_t dca) 1592 { 1593 AQ_WRITE_REG_BIT(aq_hw, tdm_dcaddesc_en_adr(dca), tdm_dcaddesc_en_msk, 1594 tdm_dcaddesc_en_shift, tx_desc_dca_en); 1595 } 1596 1597 void 1598 tdm_tx_desc_en_set(struct aq_hw *aq_hw, uint32_t tx_desc_en, 1599 uint32_t descriptor) 1600 { 1601 AQ_WRITE_REG_BIT(aq_hw, tdm_descden_adr(descriptor), tdm_descden_msk, 1602 tdm_descden_shift, tx_desc_en); 1603 } 1604 1605 uint32_t 1606 tdm_tx_desc_head_ptr_get(struct aq_hw *aq_hw, uint32_t descriptor) 1607 { 1608 return AQ_READ_REG_BIT(aq_hw, tdm_descdhd_adr(descriptor), 1609 tdm_descdhd_msk, tdm_descdhd_shift); 1610 } 1611 1612 void 1613 tdm_tx_desc_len_set(struct aq_hw *aq_hw, uint32_t tx_desc_len, 1614 uint32_t descriptor) 1615 { 1616 AQ_WRITE_REG_BIT(aq_hw, tdm_descdlen_adr(descriptor), tdm_descdlen_msk, 1617 tdm_descdlen_shift, tx_desc_len); 1618 } 1619 1620 void 1621 tdm_tx_desc_wr_wb_irq_en_set(struct aq_hw *aq_hw, uint32_t tx_desc_wr_wb_irq_en) 1622 { 1623 AQ_WRITE_REG_BIT(aq_hw, tdm_int_desc_wrb_en_adr, 1624 tdm_int_desc_wrb_en_msk, tdm_int_desc_wrb_en_shift, 1625 tx_desc_wr_wb_irq_en); 1626 } 1627 1628 void 1629 tdm_tx_desc_wr_wb_threshold_set(struct aq_hw *aq_hw, 1630 uint32_t tx_desc_wr_wb_threshold, uint32_t descriptor) 1631 { 1632 AQ_WRITE_REG_BIT(aq_hw, tdm_descdwrb_thresh_adr(descriptor), 1633 tdm_descdwrb_thresh_msk, tdm_descdwrb_thresh_shift, 1634 tx_desc_wr_wb_threshold); 1635 } 1636 1637 void 1638 tdm_tdm_intr_moder_en_set(struct aq_hw *aq_hw, uint32_t tdm_irq_moderation_en) 1639 { 1640 AQ_WRITE_REG_BIT(aq_hw, tdm_int_mod_en_adr, tdm_int_mod_en_msk, 1641 tdm_int_mod_en_shift, tdm_irq_moderation_en); 1642 } 1643 1644 /* thm */ 1645 void 1646 thm_lso_tcp_flag_of_first_pkt_set(struct aq_hw *aq_hw, 1647 uint32_t lso_tcp_flag_of_first_pkt) 1648 { 1649 AQ_WRITE_REG_BIT(aq_hw, thm_lso_tcp_flag_first_adr, 1650 thm_lso_tcp_flag_first_msk, thm_lso_tcp_flag_first_shift, 1651 lso_tcp_flag_of_first_pkt); 1652 } 1653 1654 void 1655 thm_lso_tcp_flag_of_last_pkt_set(struct aq_hw *aq_hw, 1656 uint32_t lso_tcp_flag_of_last_pkt) 1657 { 1658 AQ_WRITE_REG_BIT(aq_hw, thm_lso_tcp_flag_last_adr, 1659 thm_lso_tcp_flag_last_msk, thm_lso_tcp_flag_last_shift, 1660 lso_tcp_flag_of_last_pkt); 1661 } 1662 1663 void 1664 thm_lso_tcp_flag_of_middle_pkt_set(struct aq_hw *aq_hw, 1665 uint32_t lso_tcp_flag_of_middle_pkt) 1666 { 1667 AQ_WRITE_REG_BIT(aq_hw, thm_lso_tcp_flag_mid_adr, 1668 thm_lso_tcp_flag_mid_msk, thm_lso_tcp_flag_mid_shift, 1669 lso_tcp_flag_of_middle_pkt); 1670 } 1671 1672 /* TPB: tx packet buffer */ 1673 void 1674 tpb_tx_buff_en_set(struct aq_hw *aq_hw, uint32_t tx_buff_en) 1675 { 1676 AQ_WRITE_REG_BIT(aq_hw, tpb_tx_buf_en_adr, tpb_tx_buf_en_msk, 1677 tpb_tx_buf_en_shift, tx_buff_en); 1678 } 1679 1680 void 1681 tpb_tx_tc_mode_set(struct aq_hw *aq_hw, uint32_t tc_mode) 1682 { 1683 AQ_WRITE_REG_BIT(aq_hw, tpb_tx_tc_mode_adr, tpb_tx_tc_mode_msk, 1684 tpb_tx_tc_mode_shift, tc_mode); 1685 } 1686 1687 void 1688 tpb_tx_buff_hi_threshold_per_tc_set(struct aq_hw *aq_hw, 1689 uint32_t tx_buff_hi_threshold_per_tc, uint32_t buffer) 1690 { 1691 AQ_WRITE_REG_BIT(aq_hw, tpb_txbhi_thresh_adr(buffer), 1692 tpb_txbhi_thresh_msk, tpb_txbhi_thresh_shift, 1693 tx_buff_hi_threshold_per_tc); 1694 } 1695 1696 void 1697 tpb_tx_buff_lo_threshold_per_tc_set(struct aq_hw *aq_hw, 1698 uint32_t tx_buff_lo_threshold_per_tc, uint32_t buffer) 1699 { 1700 AQ_WRITE_REG_BIT(aq_hw, tpb_txblo_thresh_adr(buffer), 1701 tpb_txblo_thresh_msk, tpb_txblo_thresh_shift, 1702 tx_buff_lo_threshold_per_tc); 1703 } 1704 1705 void 1706 tpb_tx_dma_sys_lbk_en_set(struct aq_hw *aq_hw, uint32_t tx_dma_sys_lbk_en) 1707 { 1708 AQ_WRITE_REG_BIT(aq_hw, tpb_dma_sys_lbk_adr, tpb_dma_sys_lbk_msk, 1709 tpb_dma_sys_lbk_shift, tx_dma_sys_lbk_en); 1710 } 1711 1712 void 1713 rdm_rx_dma_desc_cache_init_tgl(struct aq_hw *aq_hw) 1714 { 1715 AQ_WRITE_REG_BIT(aq_hw, rdm_rx_dma_desc_cache_init_adr, 1716 rdm_rx_dma_desc_cache_init_msk, rdm_rx_dma_desc_cache_init_shift, 1717 AQ_READ_REG_BIT(aq_hw, rdm_rx_dma_desc_cache_init_adr, 1718 rdm_rx_dma_desc_cache_init_msk, 1719 rdm_rx_dma_desc_cache_init_shift) ^ 1 1720 ); 1721 } 1722 1723 void 1724 tpb_tx_pkt_buff_size_per_tc_set(struct aq_hw *aq_hw, 1725 uint32_t tx_pkt_buff_size_per_tc, uint32_t buffer) 1726 { 1727 AQ_WRITE_REG_BIT(aq_hw, tpb_txbbuf_size_adr(buffer), 1728 tpb_txbbuf_size_msk, tpb_txbbuf_size_shift, 1729 tx_pkt_buff_size_per_tc); 1730 } 1731 1732 void 1733 tpb_tx_path_scp_ins_en_set(struct aq_hw *aq_hw, uint32_t tx_path_scp_ins_en) 1734 { 1735 AQ_WRITE_REG_BIT(aq_hw, tpb_tx_scp_ins_en_adr, tpb_tx_scp_ins_en_msk, 1736 tpb_tx_scp_ins_en_shift, tx_path_scp_ins_en); 1737 } 1738 1739 /* TPO: tx packet offload */ 1740 void 1741 tpo_ipv4header_crc_offload_en_set(struct aq_hw *aq_hw, 1742 uint32_t ipv4header_crc_offload_en) 1743 { 1744 AQ_WRITE_REG_BIT(aq_hw, tpo_ipv4chk_en_adr, tpo_ipv4chk_en_msk, 1745 tpo_ipv4chk_en_shift, ipv4header_crc_offload_en); 1746 } 1747 1748 void 1749 tpo_tcp_udp_crc_offload_en_set(struct aq_hw *aq_hw, 1750 uint32_t tcp_udp_crc_offload_en) 1751 { 1752 AQ_WRITE_REG_BIT(aq_hw, tpol4chk_en_adr, tpol4chk_en_msk, 1753 tpol4chk_en_shift, tcp_udp_crc_offload_en); 1754 } 1755 1756 void 1757 tpo_tx_pkt_sys_lbk_en_set(struct aq_hw *aq_hw, uint32_t tx_pkt_sys_lbk_en) 1758 { 1759 AQ_WRITE_REG_BIT(aq_hw, tpo_pkt_sys_lbk_adr, tpo_pkt_sys_lbk_msk, 1760 tpo_pkt_sys_lbk_shift, tx_pkt_sys_lbk_en); 1761 } 1762 1763 /* TPS: tx packet scheduler */ 1764 void 1765 tps_tx_pkt_shed_data_arb_mode_set(struct aq_hw *aq_hw, 1766 uint32_t tx_pkt_shed_data_arb_mode) 1767 { 1768 AQ_WRITE_REG_BIT(aq_hw, tps_data_tc_arb_mode_adr, 1769 tps_data_tc_arb_mode_msk, tps_data_tc_arb_mode_shift, 1770 tx_pkt_shed_data_arb_mode); 1771 } 1772 1773 void 1774 tps_tx_pkt_shed_desc_rate_curr_time_res_set(struct aq_hw *aq_hw, 1775 uint32_t curr_time_res) 1776 { 1777 AQ_WRITE_REG_BIT(aq_hw, tps_desc_rate_ta_rst_adr, 1778 tps_desc_rate_ta_rst_msk, tps_desc_rate_ta_rst_shift, 1779 curr_time_res); 1780 } 1781 1782 void 1783 tps_tx_pkt_shed_desc_rate_lim_set(struct aq_hw *aq_hw, 1784 uint32_t tx_pkt_shed_desc_rate_lim) 1785 { 1786 AQ_WRITE_REG_BIT(aq_hw, tps_desc_rate_lim_adr, tps_desc_rate_lim_msk, 1787 tps_desc_rate_lim_shift, tx_pkt_shed_desc_rate_lim); 1788 } 1789 1790 void 1791 tps_tx_pkt_shed_desc_tc_arb_mode_set(struct aq_hw *aq_hw, 1792 uint32_t tx_pkt_shed_desc_tc_arb_mode) 1793 { 1794 AQ_WRITE_REG_BIT(aq_hw, tps_desc_tc_arb_mode_adr, 1795 tps_desc_tc_arb_mode_msk, tps_desc_tc_arb_mode_shift, 1796 tx_pkt_shed_desc_tc_arb_mode); 1797 } 1798 1799 void 1800 tps_tx_pkt_shed_desc_tc_max_credit_set(struct aq_hw *aq_hw, 1801 uint32_t tx_pkt_shed_desc_tc_max_credit, uint32_t tc) 1802 { 1803 AQ_WRITE_REG_BIT(aq_hw, tps_desc_tctcredit_max_adr(tc), 1804 tps_desc_tctcredit_max_msk, tps_desc_tctcredit_max_shift, 1805 tx_pkt_shed_desc_tc_max_credit); 1806 } 1807 1808 void 1809 tps_tx_pkt_shed_desc_tc_weight_set(struct aq_hw *aq_hw, 1810 uint32_t tx_pkt_shed_desc_tc_weight, uint32_t tc) 1811 { 1812 AQ_WRITE_REG_BIT(aq_hw, tps_desc_tctweight_adr(tc), 1813 tps_desc_tctweight_msk, tps_desc_tctweight_shift, 1814 tx_pkt_shed_desc_tc_weight); 1815 } 1816 1817 void 1818 tps_tx_pkt_shed_desc_vm_arb_mode_set(struct aq_hw *aq_hw, 1819 uint32_t tx_pkt_shed_desc_vm_arb_mode) 1820 { 1821 AQ_WRITE_REG_BIT(aq_hw, tps_desc_vm_arb_mode_adr, 1822 tps_desc_vm_arb_mode_msk, tps_desc_vm_arb_mode_shift, 1823 tx_pkt_shed_desc_vm_arb_mode); 1824 } 1825 1826 void 1827 tps_tx_pkt_shed_tc_data_max_credit_set(struct aq_hw *aq_hw, 1828 uint32_t tx_pkt_shed_tc_data_max_credit, uint32_t tc) 1829 { 1830 AQ_WRITE_REG_BIT(aq_hw, tps_data_tctcredit_max_adr(tc), 1831 tps_data_tctcredit_max_msk, tps_data_tctcredit_max_shift, 1832 tx_pkt_shed_tc_data_max_credit); 1833 } 1834 1835 void 1836 tps_tx_pkt_shed_tc_data_weight_set(struct aq_hw *aq_hw, 1837 uint32_t tx_pkt_shed_tc_data_weight, uint32_t tc) 1838 { 1839 AQ_WRITE_REG_BIT(aq_hw, tps_data_tctweight_adr(tc), 1840 tps_data_tctweight_msk, tps_data_tctweight_shift, 1841 tx_pkt_shed_tc_data_weight); 1842 } 1843 1844 /* tx */ 1845 void 1846 tx_tx_reg_res_dis_set(struct aq_hw *aq_hw, uint32_t tx_reg_res_dis) 1847 { 1848 AQ_WRITE_REG_BIT(aq_hw, tx_reg_res_dsbl_adr, tx_reg_res_dsbl_msk, 1849 tx_reg_res_dsbl_shift, tx_reg_res_dis); 1850 } 1851 1852 /* msm */ 1853 uint32_t 1854 msm_reg_access_status_get(struct aq_hw *aq_hw) 1855 { 1856 return AQ_READ_REG_BIT(aq_hw, msm_reg_access_busy_adr, 1857 msm_reg_access_busy_msk, msm_reg_access_busy_shift); 1858 } 1859 1860 void 1861 msm_reg_addr_for_indirect_addr_set(struct aq_hw *aq_hw, 1862 uint32_t reg_addr_for_indirect_addr) 1863 { 1864 AQ_WRITE_REG_BIT(aq_hw, msm_reg_addr_adr, msm_reg_addr_msk, 1865 msm_reg_addr_shift, reg_addr_for_indirect_addr); 1866 } 1867 1868 void 1869 msm_reg_rd_strobe_set(struct aq_hw *aq_hw, uint32_t reg_rd_strobe) 1870 { 1871 AQ_WRITE_REG_BIT(aq_hw, msm_reg_rd_strobe_adr, msm_reg_rd_strobe_msk, 1872 msm_reg_rd_strobe_shift, reg_rd_strobe); 1873 } 1874 1875 uint32_t 1876 msm_reg_rd_data_get(struct aq_hw *aq_hw) 1877 { 1878 return AQ_READ_REG(aq_hw, msm_reg_rd_data_adr); 1879 } 1880 1881 void 1882 msm_reg_wr_data_set(struct aq_hw *aq_hw, uint32_t reg_wr_data) 1883 { 1884 AQ_WRITE_REG(aq_hw, msm_reg_wr_data_adr, reg_wr_data); 1885 } 1886 1887 void 1888 msm_reg_wr_strobe_set(struct aq_hw *aq_hw, uint32_t reg_wr_strobe) 1889 { 1890 AQ_WRITE_REG_BIT(aq_hw, msm_reg_wr_strobe_adr, msm_reg_wr_strobe_msk, 1891 msm_reg_wr_strobe_shift, reg_wr_strobe); 1892 } 1893 1894 /* pci */ 1895 void 1896 pci_pci_reg_res_dis_set(struct aq_hw *aq_hw, uint32_t pci_reg_res_dis) 1897 { 1898 AQ_WRITE_REG_BIT(aq_hw, pci_reg_res_dsbl_adr, pci_reg_res_dsbl_msk, 1899 pci_reg_res_dsbl_shift, pci_reg_res_dis); 1900 } 1901 1902 uint32_t 1903 reg_glb_cpu_scratch_scp_get(struct aq_hw *hw, uint32_t glb_cpu_scratch_scp_idx) 1904 { 1905 return AQ_READ_REG(hw, 1906 glb_cpu_scratch_scp_adr(glb_cpu_scratch_scp_idx)); 1907 } 1908 void 1909 reg_glb_cpu_scratch_scp_set(struct aq_hw *aq_hw, uint32_t glb_cpu_scratch_scp, 1910 uint32_t scratch_scp) 1911 { 1912 AQ_WRITE_REG(aq_hw, glb_cpu_scratch_scp_adr(scratch_scp), 1913 glb_cpu_scratch_scp); 1914 } 1915 1916 uint32_t 1917 reg_glb_cpu_no_reset_scratchpad_get(struct aq_hw *hw, uint32_t index) 1918 { 1919 return AQ_READ_REG(hw, glb_cpu_no_reset_scratchpad_adr(index)); 1920 } 1921 void 1922 reg_glb_cpu_no_reset_scratchpad_set(struct aq_hw* hw, uint32_t value, 1923 uint32_t index) 1924 { 1925 AQ_WRITE_REG(hw, glb_cpu_no_reset_scratchpad_adr(index), value); 1926 } 1927 1928 void 1929 reg_mif_power_gating_enable_control_set(struct aq_hw* hw, uint32_t value) 1930 { 1931 AQ_WRITE_REG(hw, mif_power_gating_enable_control_adr, value); 1932 1933 } 1934 uint32_t 1935 reg_mif_power_gating_enable_control_get(struct aq_hw* hw) 1936 { 1937 return AQ_READ_REG(hw, mif_power_gating_enable_control_adr); 1938 } 1939 1940 1941 void 1942 reg_glb_general_provisioning9_set(struct aq_hw* hw, uint32_t value) 1943 { 1944 AQ_WRITE_REG(hw, glb_general_provisioning9_adr, value); 1945 } 1946 uint32_t 1947 reg_glb_general_provisioning9_get(struct aq_hw* hw) 1948 { 1949 return AQ_READ_REG(hw, glb_general_provisioning9_adr); 1950 } 1951 1952 void 1953 reg_glb_nvr_provisioning2_set(struct aq_hw* hw, uint32_t value) 1954 { 1955 AQ_WRITE_REG(hw, glb_nvr_provisioning2_adr, value); 1956 } 1957 uint32_t 1958 reg_glb_nvr_provisioning2_get(struct aq_hw* hw) 1959 { 1960 return AQ_READ_REG(hw, glb_nvr_provisioning2_adr); 1961 } 1962 1963 void 1964 reg_glb_nvr_interface1_set(struct aq_hw* hw, uint32_t value) 1965 { 1966 AQ_WRITE_REG(hw, glb_nvr_interface1_adr, value); 1967 } 1968 uint32_t 1969 reg_glb_nvr_interface1_get(struct aq_hw* hw) 1970 { 1971 return AQ_READ_REG(hw, glb_nvr_interface1_adr); 1972 } 1973 1974 /* get mif up mailbox busy */ 1975 uint32_t 1976 mif_mcp_up_mailbox_busy_get(struct aq_hw *hw) 1977 { 1978 return AQ_READ_REG_BIT(hw, mif_mcp_up_mailbox_busy_adr, 1979 mif_mcp_up_mailbox_busy_msk, mif_mcp_up_mailbox_busy_shift); 1980 } 1981 1982 /* set mif up mailbox execute operation */ 1983 void 1984 mif_mcp_up_mailbox_execute_operation_set(struct aq_hw* hw, uint32_t value) 1985 { 1986 AQ_WRITE_REG_BIT(hw, mif_mcp_up_mailbox_execute_operation_adr, 1987 mif_mcp_up_mailbox_execute_operation_msk, 1988 mif_mcp_up_mailbox_execute_operation_shift, value); 1989 } 1990 /* get mif uP mailbox address */ 1991 uint32_t 1992 mif_mcp_up_mailbox_addr_get(struct aq_hw *hw) 1993 { 1994 return AQ_READ_REG(hw, mif_mcp_up_mailbox_addr_adr); 1995 } 1996 /* set mif uP mailbox address */ 1997 void 1998 mif_mcp_up_mailbox_addr_set(struct aq_hw *hw, uint32_t value) 1999 { 2000 AQ_WRITE_REG(hw, mif_mcp_up_mailbox_addr_adr, value); 2001 } 2002 2003 /* get mif uP mailbox data */ 2004 uint32_t 2005 mif_mcp_up_mailbox_data_get(struct aq_hw *hw) 2006 { 2007 return AQ_READ_REG(hw, mif_mcp_up_mailbox_data_adr); 2008 } 2009 2010 void 2011 hw_atl_rpfl3l4_ipv4_dest_addr_clear(struct aq_hw_s *aq_hw, uint8_t location) 2012 { 2013 aq_hw_write_reg(aq_hw, HW_ATL_RX_GET_ADDR_DESTA_FL3L4(location), 0U); 2014 } 2015 2016 void 2017 hw_atl_rpfl3l4_ipv4_src_addr_clear(struct aq_hw_s *aq_hw, uint8_t location) 2018 { 2019 aq_hw_write_reg(aq_hw, HW_ATL_RX_GET_ADDR_SRCA_FL3L4(location), 0U); 2020 } 2021 2022 void 2023 hw_atl_rpfl3l4_cmd_clear(struct aq_hw_s *aq_hw, uint8_t location) 2024 { 2025 aq_hw_write_reg(aq_hw, HW_ATL_RX_GET_ADDR_CTRL_FL3L4(location), 0U); 2026 } 2027 2028 void 2029 hw_atl_rpfl3l4_ipv6_dest_addr_clear(struct aq_hw_s *aq_hw, uint8_t location) 2030 { 2031 int i; 2032 2033 for (i = 0; i < 4; ++i) 2034 aq_hw_write_reg(aq_hw, 2035 HW_ATL_RX_GET_ADDR_DESTA_FL3L4(location + i), 0U); 2036 } 2037 2038 void 2039 hw_atl_rpfl3l4_ipv6_src_addr_clear(struct aq_hw_s *aq_hw, uint8_t location) 2040 { 2041 int i; 2042 2043 for (i = 0; i < 4; ++i) 2044 aq_hw_write_reg(aq_hw, 2045 HW_ATL_RX_GET_ADDR_SRCA_FL3L4(location + i), 0U); 2046 } 2047 2048 void 2049 hw_atl_rpfl3l4_ipv4_dest_addr_set(struct aq_hw_s *aq_hw, uint8_t location, 2050 uint32_t ipv4_dest) 2051 { 2052 aq_hw_write_reg(aq_hw, HW_ATL_RX_GET_ADDR_DESTA_FL3L4(location), 2053 ipv4_dest); 2054 } 2055 2056 void 2057 hw_atl_rpfl3l4_ipv4_src_addr_set(struct aq_hw_s *aq_hw, uint8_t location, 2058 uint32_t ipv4_src) 2059 { 2060 aq_hw_write_reg(aq_hw, HW_ATL_RX_GET_ADDR_SRCA_FL3L4(location), 2061 ipv4_src); 2062 } 2063 2064 void 2065 hw_atl_rpfl3l4_cmd_set(struct aq_hw_s *aq_hw, uint8_t location, uint32_t cmd) 2066 { 2067 aq_hw_write_reg(aq_hw, HW_ATL_RX_GET_ADDR_CTRL_FL3L4(location), cmd); 2068 } 2069 2070 void 2071 hw_atl_rpfl3l4_ipv6_src_addr_set(struct aq_hw_s *aq_hw, uint8_t location, 2072 uint32_t *ipv6_src) 2073 { 2074 int i; 2075 2076 for (i = 0; i < 4; ++i) 2077 aq_hw_write_reg(aq_hw, 2078 HW_ATL_RX_GET_ADDR_SRCA_FL3L4(location + i), ipv6_src[i]); 2079 } 2080 2081 void 2082 hw_atl_rpfl3l4_ipv6_dest_addr_set(struct aq_hw_s *aq_hw, uint8_t location, 2083 uint32_t *ipv6_dest) 2084 { 2085 int i; 2086 2087 for (i = 0; i < 4; ++i) 2088 aq_hw_write_reg(aq_hw, 2089 HW_ATL_RX_GET_ADDR_DESTA_FL3L4(location + i), ipv6_dest[i]); 2090 } 2091