1493d26c5SEd Maste /** 2493d26c5SEd Maste * aQuantia Corporation Network Driver 3493d26c5SEd Maste * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved 4493d26c5SEd Maste * 5493d26c5SEd Maste * Redistribution and use in source and binary forms, with or without 6493d26c5SEd Maste * modification, are permitted provided that the following conditions 7493d26c5SEd Maste * are met: 8493d26c5SEd Maste * 9493d26c5SEd Maste * (1) Redistributions of source code must retain the above 10493d26c5SEd Maste * copyright notice, this list of conditions and the following 11493d26c5SEd Maste * disclaimer. 12493d26c5SEd Maste * 13493d26c5SEd Maste * (2) Redistributions in binary form must reproduce the above 14493d26c5SEd Maste * copyright notice, this list of conditions and the following 15493d26c5SEd Maste * disclaimer in the documentation and/or other materials provided 16493d26c5SEd Maste * with the distribution. 17493d26c5SEd Maste * 18493d26c5SEd Maste * (3) The name of the author may not be used to endorse or promote 19493d26c5SEd Maste * products derived from this software without specific prior 20493d26c5SEd Maste * written permission. 21493d26c5SEd Maste * 22493d26c5SEd Maste * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS 23493d26c5SEd Maste * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 24493d26c5SEd Maste * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25493d26c5SEd Maste * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 26493d26c5SEd Maste * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27493d26c5SEd Maste * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 28493d26c5SEd Maste * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29493d26c5SEd Maste * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30493d26c5SEd Maste * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 31493d26c5SEd Maste * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32493d26c5SEd Maste * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33493d26c5SEd Maste */ 34493d26c5SEd Maste #ifndef AQ_FW_H 35493d26c5SEd Maste #define AQ_FW_H 36493d26c5SEd Maste 37493d26c5SEd Maste struct aq_hw; 38493d26c5SEd Maste 39493d26c5SEd Maste typedef enum aq_fw_link_speed 40493d26c5SEd Maste { 41493d26c5SEd Maste aq_fw_none = 0, 42493d26c5SEd Maste aq_fw_100M = (1 << 0), 43493d26c5SEd Maste aq_fw_1G = (1 << 1), 44493d26c5SEd Maste aq_fw_2G5 = (1 << 2), 45493d26c5SEd Maste aq_fw_5G = (1 << 3), 46493d26c5SEd Maste aq_fw_10G = (1 << 4), 47493d26c5SEd Maste } aq_fw_link_speed_t; 48493d26c5SEd Maste 49493d26c5SEd Maste typedef enum aq_fw_link_fc 50493d26c5SEd Maste { 51493d26c5SEd Maste aq_fw_fc_none = 0, 52493d26c5SEd Maste aq_fw_fc_ENABLE_RX = BIT(0), 53493d26c5SEd Maste aq_fw_fc_ENABLE_TX = BIT(1), 54493d26c5SEd Maste aq_fw_fc_ENABLE_ALL = aq_fw_fc_ENABLE_RX | aq_fw_fc_ENABLE_TX, 55493d26c5SEd Maste } aq_fw_link_fc_t; 56493d26c5SEd Maste 5796156003SEd Maste #define aq_fw_speed_auto \ 5896156003SEd Maste (aq_fw_100M | aq_fw_1G | aq_fw_2G5 | aq_fw_5G | aq_fw_10G) 59493d26c5SEd Maste 60493d26c5SEd Maste struct aq_firmware_ops 61493d26c5SEd Maste { 62493d26c5SEd Maste int (*reset)(struct aq_hw* hal); 63493d26c5SEd Maste 64493d26c5SEd Maste int (*set_mode)(struct aq_hw* hal, enum aq_hw_fw_mpi_state_e mode, aq_fw_link_speed_t speed); 65493d26c5SEd Maste int (*get_mode)(struct aq_hw* hal, enum aq_hw_fw_mpi_state_e* mode, aq_fw_link_speed_t* speed, aq_fw_link_fc_t* fc); 66493d26c5SEd Maste 6796156003SEd Maste int (*get_mac_addr)(struct aq_hw* hal, uint8_t* mac_addr); 68493d26c5SEd Maste int (*get_stats)(struct aq_hw* hal, struct aq_hw_stats_s* stats); 69493d26c5SEd Maste 7096156003SEd Maste int (*led_control)(struct aq_hw* hal, uint32_t mode); 71493d26c5SEd Maste }; 72493d26c5SEd Maste 73493d26c5SEd Maste 74493d26c5SEd Maste int aq_fw_reset(struct aq_hw* hw); 75493d26c5SEd Maste int aq_fw_ops_init(struct aq_hw* hw); 76493d26c5SEd Maste 77493d26c5SEd Maste #endif // AQ_FW_H 78