1# SPDX-License-Identifier: GPL-2.0-only 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/soc/qcom/qcom,rpmh-rsc.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm RPMH RSC 8 9maintainers: 10 - Bjorn Andersson <bjorn.andersson@linaro.org> 11 12description: | 13 Resource Power Manager Hardened (RPMH) is the mechanism for communicating 14 with the hardened resource accelerators on Qualcomm SoCs. Requests to the 15 resources can be written to the Trigger Command Set (TCS) registers and 16 using a (addr, val) pair and triggered. Messages in the TCS are then sent in 17 sequence over an internal bus. 18 19 The hardware block (Direct Resource Voter or DRV) is a part of the h/w entity 20 (Resource State Coordinator a.k.a RSC) that can handle multiple sleep and 21 active/wake resource requests. Multiple such DRVs can exist in a SoC and can 22 be written to from Linux. The structure of each DRV follows the same template 23 with a few variations that are captured by the properties here. 24 25 A TCS may be triggered from Linux or triggered by the F/W after all the CPUs 26 have powered off to facilitate idle power saving. TCS could be classified as:: 27 ACTIVE - Triggered by Linux 28 SLEEP - Triggered by F/W 29 WAKE - Triggered by F/W 30 CONTROL - Triggered by F/W 31 See also:: <dt-bindings/soc/qcom,rpmh-rsc.h> 32 33 The order in which they are described in the DT, should match the hardware 34 configuration. 35 36 Requests can be made for the state of a resource, when the subsystem is 37 active or idle. When all subsystems like Modem, GPU, CPU are idle, the 38 resource state will be an aggregate of the sleep votes from each of those 39 subsystems. Clients may request a sleep value for their shared resources in 40 addition to the active mode requests. 41 42 Drivers that want to use the RSC to communicate with RPMH must specify their 43 bindings as child nodes of the RSC controllers they wish to communicate with. 44 45properties: 46 compatible: 47 oneOf: 48 - items: 49 - enum: 50 - qcom,sc7180-rpmh-apps-rsc 51 - qcom,sdm845-rpmh-apps-rsc 52 - const: qcom,rpmh-rsc 53 - const: qcom,rpmh-rsc 54 55 interrupts: 56 minItems: 1 57 maxItems: 4 58 description: 59 The interrupt that trips when a message complete/response is received for 60 this DRV from the accelerators. 61 Number of interrupts must match number of DRV blocks. 62 63 label: 64 description: 65 Name for the RSC. The name would be used in trace logs. 66 67 qcom,drv-id: 68 $ref: /schemas/types.yaml#/definitions/uint32 69 description: 70 The ID of the DRV in the RSC block that will be used by this controller. 71 72 qcom,tcs-config: 73 $ref: /schemas/types.yaml#/definitions/uint32-matrix 74 minItems: 4 75 maxItems: 4 76 items: 77 items: 78 - description: | 79 TCS type:: 80 - ACTIVE_TCS 81 - SLEEP_TCS 82 - WAKE_TCS 83 - CONTROL_TCS 84 enum: [ 0, 1, 2, 3 ] 85 - description: Number of TCS 86 description: | 87 The tuple defining the configuration of TCS. Must have two cells which 88 describe each TCS type. The order of the TCS must match the hardware 89 configuration. 90 91 qcom,tcs-offset: 92 $ref: /schemas/types.yaml#/definitions/uint32 93 description: 94 The offset of the TCS blocks. 95 96 reg: 97 minItems: 1 98 maxItems: 4 99 100 reg-names: 101 minItems: 1 102 items: 103 - const: drv-0 104 - const: drv-1 105 - const: drv-2 106 - const: drv-3 107 108 power-domains: 109 maxItems: 1 110 111 bcm-voter: 112 $ref: /schemas/interconnect/qcom,bcm-voter.yaml# 113 114 clock-controller: 115 $ref: /schemas/clock/qcom,rpmhcc.yaml# 116 117 power-controller: 118 $ref: /schemas/power/qcom,rpmpd.yaml# 119 120patternProperties: 121 '^regulators(-[0-9])?$': 122 $ref: /schemas/regulator/qcom,rpmh-regulator.yaml# 123 unevaluatedProperties: false 124 125required: 126 - compatible 127 - interrupts 128 - qcom,drv-id 129 - qcom,tcs-config 130 - qcom,tcs-offset 131 - reg 132 - reg-names 133 134allOf: 135 # Some platforms may lack a OSI-mode PSCI implementation, which implies the 136 # system power domain can't provide feedback about entering power collapse 137 - if: 138 not: 139 properties: 140 compatible: 141 contains: 142 enum: 143 - qcom,sc7180-rpmh-apps-rsc 144 - qcom,sdm845-rpmh-apps-rsc 145 then: 146 required: 147 - power-domains 148 149additionalProperties: false 150 151examples: 152 - | 153 // For a TCS whose RSC base address is 0x179C0000 and is at a DRV id of 154 // 2, the register offsets for DRV2 start at 0D00, the register 155 // calculations are like this:: 156 // DRV0: 0x179C0000 157 // DRV2: 0x179C0000 + 0x10000 = 0x179D0000 158 // DRV2: 0x179C0000 + 0x10000 * 2 = 0x179E0000 159 // TCS-OFFSET: 0xD00 160 #include <dt-bindings/interrupt-controller/arm-gic.h> 161 #include <dt-bindings/soc/qcom,rpmh-rsc.h> 162 163 rsc@179c0000 { 164 compatible = "qcom,rpmh-rsc"; 165 reg = <0x179c0000 0x10000>, 166 <0x179d0000 0x10000>, 167 <0x179e0000 0x10000>; 168 reg-names = "drv-0", "drv-1", "drv-2"; 169 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 170 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 171 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 172 label = "apps_rsc"; 173 qcom,tcs-offset = <0xd00>; 174 qcom,drv-id = <2>; 175 qcom,tcs-config = <ACTIVE_TCS 2>, 176 <SLEEP_TCS 3>, 177 <WAKE_TCS 3>, 178 <CONTROL_TCS 1>; 179 power-domains = <&CLUSTER_PD>; 180 }; 181 182 - | 183 // For a TCS whose RSC base address is 0xAF20000 and is at DRV id of 0, the 184 // register offsets for DRV0 start at 01C00, the register calculations are 185 // like this:: 186 // DRV0: 0xAF20000 187 // TCS-OFFSET: 0x1C00 188 #include <dt-bindings/interrupt-controller/arm-gic.h> 189 #include <dt-bindings/soc/qcom,rpmh-rsc.h> 190 191 rsc@af20000 { 192 compatible = "qcom,rpmh-rsc"; 193 reg = <0xaf20000 0x10000>; 194 reg-names = "drv-0"; 195 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; 196 label = "disp_rsc"; 197 qcom,tcs-offset = <0x1c00>; 198 qcom,drv-id = <0>; 199 qcom,tcs-config = <ACTIVE_TCS 0>, 200 <SLEEP_TCS 1>, 201 <WAKE_TCS 1>, 202 <CONTROL_TCS 0>; 203 power-domains = <&CLUSTER_PD>; 204 }; 205 206 - | 207 #include <dt-bindings/interrupt-controller/arm-gic.h> 208 #include <dt-bindings/soc/qcom,rpmh-rsc.h> 209 #include <dt-bindings/power/qcom-rpmpd.h> 210 211 rsc@18200000 { 212 compatible = "qcom,rpmh-rsc"; 213 reg = <0x18200000 0x10000>, 214 <0x18210000 0x10000>, 215 <0x18220000 0x10000>; 216 reg-names = "drv-0", "drv-1", "drv-2"; 217 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 218 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 219 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 220 label = "apps_rsc"; 221 qcom,tcs-offset = <0xd00>; 222 qcom,drv-id = <2>; 223 qcom,tcs-config = <ACTIVE_TCS 2>, 224 <SLEEP_TCS 3>, 225 <WAKE_TCS 3>, 226 <CONTROL_TCS 0>; 227 power-domains = <&CLUSTER_PD>; 228 229 clock-controller { 230 compatible = "qcom,sm8350-rpmh-clk"; 231 #clock-cells = <1>; 232 clock-names = "xo"; 233 clocks = <&xo_board>; 234 }; 235 236 power-controller { 237 compatible = "qcom,sm8350-rpmhpd"; 238 #power-domain-cells = <1>; 239 operating-points-v2 = <&rpmhpd_opp_table>; 240 241 rpmhpd_opp_table: opp-table { 242 compatible = "operating-points-v2"; 243 244 rpmhpd_opp_ret: opp1 { 245 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 246 }; 247 248 rpmhpd_opp_min_svs: opp2 { 249 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 250 }; 251 252 rpmhpd_opp_low_svs: opp3 { 253 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 254 }; 255 256 rpmhpd_opp_svs: opp4 { 257 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 258 }; 259 260 rpmhpd_opp_svs_l1: opp5 { 261 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 262 }; 263 264 rpmhpd_opp_nom: opp6 { 265 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 266 }; 267 268 rpmhpd_opp_nom_l1: opp7 { 269 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 270 }; 271 272 rpmhpd_opp_nom_l2: opp8 { 273 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 274 }; 275 276 rpmhpd_opp_turbo: opp9 { 277 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 278 }; 279 280 rpmhpd_opp_turbo_l1: opp10 { 281 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 282 }; 283 }; 284 }; 285 286 bcm-voter { 287 compatible = "qcom,bcm-voter"; 288 }; 289 }; 290