xref: /src/sys/contrib/device-tree/Bindings/net/allwinner,sun8i-a83t-emac.yaml (revision 833e5d42ab135b0238e61c5b3c19b8619677cbfa) 
1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/allwinner,sun8i-a83t-emac.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Allwinner A83t EMAC
8
9maintainers:
10  - Chen-Yu Tsai <wens@csie.org>
11  - Maxime Ripard <mripard@kernel.org>
12
13properties:
14  compatible:
15    oneOf:
16      - const: allwinner,sun8i-a83t-emac
17      - const: allwinner,sun8i-h3-emac
18      - const: allwinner,sun8i-r40-gmac
19      - const: allwinner,sun8i-v3s-emac
20      - const: allwinner,sun50i-a64-emac
21      - items:
22          - enum:
23              - allwinner,sun20i-d1-emac
24              - allwinner,sun50i-a100-emac
25              - allwinner,sun50i-h6-emac
26              - allwinner,sun50i-h616-emac0
27              - allwinner,sun55i-a523-gmac0
28          - const: allwinner,sun50i-a64-emac
29
30  reg:
31    maxItems: 1
32
33  interrupts:
34    maxItems: 1
35
36  interrupt-names:
37    const: macirq
38
39  clocks:
40    maxItems: 1
41
42  clock-names:
43    const: stmmaceth
44
45  phy-supply:
46    description: PHY regulator
47
48  syscon:
49    $ref: /schemas/types.yaml#/definitions/phandle
50    description:
51      Phandle to the device containing the EMAC or GMAC clock
52      register
53
54required:
55  - compatible
56  - reg
57  - interrupts
58  - interrupt-names
59  - clocks
60  - clock-names
61  - resets
62  - reset-names
63  - phy-handle
64  - phy-mode
65  - syscon
66
67allOf:
68  - $ref: snps,dwmac.yaml#
69  - if:
70      properties:
71        compatible:
72          contains:
73            enum:
74              - allwinner,sun8i-a83t-emac
75              - allwinner,sun8i-h3-emac
76              - allwinner,sun8i-v3s-emac
77              - allwinner,sun50i-a64-emac
78
79    then:
80      properties:
81        allwinner,tx-delay-ps:
82          default: 0
83          minimum: 0
84          maximum: 700
85          multipleOf: 100
86          description:
87            External RGMII PHY TX clock delay chain value in ps.
88
89        allwinner,rx-delay-ps:
90          default: 0
91          minimum: 0
92          maximum: 3100
93          multipleOf: 100
94          description:
95            External RGMII PHY TX clock delay chain value in ps.
96
97  - if:
98      properties:
99        compatible:
100          contains:
101            enum:
102              - allwinner,sun8i-r40-gmac
103
104    then:
105      properties:
106        allwinner,rx-delay-ps:
107          default: 0
108          minimum: 0
109          maximum: 700
110          multipleOf: 100
111          description:
112            External RGMII PHY TX clock delay chain value in ps.
113
114  - if:
115      properties:
116        compatible:
117          contains:
118            enum:
119              - allwinner,sun8i-h3-emac
120              - allwinner,sun8i-v3s-emac
121
122    then:
123      properties:
124        allwinner,leds-active-low:
125          $ref: /schemas/types.yaml#/definitions/flag
126          description:
127            EPHY LEDs are active low.
128
129        mdio-mux:
130          type: object
131          unevaluatedProperties: false
132
133          properties:
134            compatible:
135              const: allwinner,sun8i-h3-mdio-mux
136
137            mdio-parent-bus:
138              $ref: /schemas/types.yaml#/definitions/phandle
139              description:
140                Phandle to EMAC MDIO.
141
142            "#address-cells":
143              const: 1
144
145            "#size-cells":
146              const: 0
147
148            mdio@1:
149              $ref: mdio.yaml#
150              unevaluatedProperties: false
151              description: Internal MDIO Bus
152
153              properties:
154                compatible:
155                  const: allwinner,sun8i-h3-mdio-internal
156
157                reg:
158                  const: 1
159
160              patternProperties:
161                "^ethernet-phy@[0-9a-f]$":
162                  type: object
163                  $ref: ethernet-phy.yaml#
164                  unevaluatedProperties: false
165                  description:
166                    Integrated PHY node
167
168                  properties:
169                    clocks:
170                      maxItems: 1
171
172                    resets:
173                      maxItems: 1
174
175                  required:
176                    - clocks
177                    - resets
178
179
180            mdio@2:
181              $ref: mdio.yaml#
182              unevaluatedProperties: false
183              description: External MDIO Bus (H3 only)
184
185              properties:
186                reg:
187                  const: 2
188
189          required:
190            - compatible
191            - mdio-parent-bus
192            - mdio@1
193
194unevaluatedProperties: false
195
196examples:
197  - |
198    ethernet@1c0b000 {
199        compatible = "allwinner,sun8i-h3-emac";
200        syscon = <&syscon>;
201        reg = <0x01c0b000 0x104>;
202        interrupts = <0 82 1>;
203        interrupt-names = "macirq";
204        resets = <&ccu 12>;
205        reset-names = "stmmaceth";
206        clocks = <&ccu 27>;
207        clock-names = "stmmaceth";
208
209        phy-handle = <&int_mii_phy>;
210        phy-mode = "mii";
211        allwinner,leds-active-low;
212
213        mdio1: mdio {
214            #address-cells = <1>;
215            #size-cells = <0>;
216            compatible = "snps,dwmac-mdio";
217        };
218
219        mdio-mux {
220            compatible = "allwinner,sun8i-h3-mdio-mux";
221            #address-cells = <1>;
222            #size-cells = <0>;
223
224            mdio-parent-bus = <&mdio1>;
225
226            int_mii_phy: mdio@1 {
227                compatible = "allwinner,sun8i-h3-mdio-internal";
228                reg = <1>;
229                #address-cells = <1>;
230                #size-cells = <0>;
231
232                ethernet-phy@1 {
233                    reg = <1>;
234                    clocks = <&ccu 67>;
235                    resets = <&ccu 39>;
236                    phy-is-integrated;
237                };
238            };
239
240            mdio@2 {
241                reg = <2>;
242                #address-cells = <1>;
243                #size-cells = <0>;
244            };
245        };
246    };
247
248  - |
249    ethernet@1c0b000 {
250        compatible = "allwinner,sun8i-h3-emac";
251        syscon = <&syscon>;
252        reg = <0x01c0b000 0x104>;
253        interrupts = <0 82 1>;
254        interrupt-names = "macirq";
255        resets = <&ccu 12>;
256        reset-names = "stmmaceth";
257        clocks = <&ccu 27>;
258        clock-names = "stmmaceth";
259
260        phy-handle = <&ext_rgmii_phy>;
261        phy-mode = "rgmii";
262        allwinner,leds-active-low;
263
264        mdio2: mdio {
265            #address-cells = <1>;
266            #size-cells = <0>;
267            compatible = "snps,dwmac-mdio";
268        };
269
270        mdio-mux {
271            compatible = "allwinner,sun8i-h3-mdio-mux";
272            #address-cells = <1>;
273            #size-cells = <0>;
274            mdio-parent-bus = <&mdio2>;
275
276            mdio@1 {
277                compatible = "allwinner,sun8i-h3-mdio-internal";
278                reg = <1>;
279                #address-cells = <1>;
280                #size-cells = <0>;
281
282                ethernet-phy@1 {
283                    reg = <1>;
284                    clocks = <&ccu 67>;
285                    resets = <&ccu 39>;
286                };
287            };
288
289            mdio@2 {
290                reg = <2>;
291                #address-cells = <1>;
292                #size-cells = <0>;
293
294                ext_rgmii_phy: ethernet-phy@1 {
295                    reg = <1>;
296                };
297            };
298        };
299    };
300
301  - |
302    ethernet@1c0b000 {
303        compatible = "allwinner,sun8i-a83t-emac";
304        syscon = <&syscon>;
305        reg = <0x01c0b000 0x104>;
306        interrupts = <0 82 1>;
307        interrupt-names = "macirq";
308        resets = <&ccu 13>;
309        reset-names = "stmmaceth";
310        clocks = <&ccu 27>;
311        clock-names = "stmmaceth";
312        phy-handle = <&ext_rgmii_phy1>;
313        phy-mode = "rgmii";
314
315        mdio {
316            compatible = "snps,dwmac-mdio";
317            #address-cells = <1>;
318            #size-cells = <0>;
319
320            ext_rgmii_phy1: ethernet-phy@1 {
321                reg = <1>;
322            };
323        };
324    };
325
326...
327